Another lump of target-arm patches. I still have some patches in

my to-review queue, but this is a big enough set that I wanted

to send it out.

The following changes since commit 04bb7fe2bf55bdf66d5b7a5a719b40bbb4048178:

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180208' into staging (2018-02-08 17:41:15 +0000)

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180209

for you to fetch changes up to bbba7757bacc9f890a3f028d328b4b429dbe78ec:

hw/core/generic-loader: Allow PC to be set on command line (2018-02-09 10:55:40 +0000)

* Support M profile derived exceptions on exception entry and exit

* Implement AArch64 v8.2 crypto insns (SHA-512, SHA-3, SM3, SM4)

* Implement working i.MX6 SD controller

* Various devices preparatory to i.MX7 support

* Preparatory patches for SVE emulation

* v8M: Fix bug in implementation of 'TT' insn

* Give useful error if user tries to use userspace GICv3 with KVM

Andrey Smirnov (10):

sdhci: Add i.MX specific subtype of SDHCI

hw: i.MX: Convert i.MX6 to use TYPE_IMX_USDHC

i.MX: Add code to emulate i.MX7 CCM, PMU and ANALOG IP blocks

i.MX: Add code to emulate i.MX2 watchdog IP block

i.MX: Add code to emulate i.MX7 SNVS IP-block

i.MX: Add code to emulate GPCv2 IP block

i.MX: Add i.MX7 GPT variant

i.MX: Add implementation of i.MX7 GPR IP block

usb: Add basic code to emulate Chipidea USB IP

hw/arm: Move virt's PSCI DT fixup code to arm/boot.c

Ard Biesheuvel (5):

target/arm: implement SHA-512 instructions

target/arm: implement SHA-3 instructions

target/arm: implement SM3 instructions

target/arm: implement SM4 instructions

target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add code to emulate Chipidea USB IP (used in i.MX SoCs). Tested to

work against:

-usb -drive if=none,id=stick,file=usb.img,format=raw -device \

usb-storage,bus=usb-bus.0,drive=stick

Cc: Peter Maydell <peter.maydell@linaro.org>

Cc: Jason Wang <jasowang@redhat.com>

Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>

Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com>

Cc: Michael S. Tsirkin <mst@redhat.com>

Cc: qemu-devel@nongnu.org

Cc: qemu-arm@nongnu.org

Cc: yurovsky@gmail.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/usb/Makefile.objs | 1 +

include/hw/usb/chipidea.h | 16 +++++

hw/usb/chipidea.c | 176 ++++++++++++++++++++++++++++++++++++++++++++++

3 files changed, 193 insertions(+)

create mode 100644 include/hw/usb/chipidea.h

create mode 100644 hw/usb/chipidea.c

diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/usb/Makefile.objs

+++ b/hw/usb/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_USB_XHCI_NEC) += hcd-xhci-nec.o

common-obj-$(CONFIG_USB_MUSB) += hcd-musb.o

obj-$(CONFIG_TUSB6010) += tusb6010.o

+obj-$(CONFIG_IMX) += chipidea.o

# emulated usb devices

common-obj-$(CONFIG_USB) += dev-hub.o

diff --git a/include/hw/usb/chipidea.h b/include/hw/usb/chipidea.h

+++ b/include/hw/usb/chipidea.h

+#ifndef CHIPIDEA_H

+#define CHIPIDEA_H

+#include "hw/usb/hcd-ehci.h"

+typedef struct ChipideaState {

+ /*< private >*/

+ EHCISysBusState parent_obj;

+ MemoryRegion iomem[3];

+} ChipideaState;

+

+#define TYPE_CHIPIDEA "usb-chipidea"

+#define CHIPIDEA(obj) OBJECT_CHECK(ChipideaState, (obj), TYPE_CHIPIDEA)

+

+#endif /* CHIPIDEA_H */

diff --git a/hw/usb/chipidea.c b/hw/usb/chipidea.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/usb/chipidea.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Copyright (c) 2018, Impinj, Inc.

+ *

+ * Chipidea USB block emulation code

+ *

+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+#include "qemu/osdep.h"

+#include "hw/usb/hcd-ehci.h"

+#include "hw/usb/chipidea.h"

+#include "qemu/log.h"

+

+enum {

+ CHIPIDEA_USBx_DCIVERSION = 0x000,

+ CHIPIDEA_USBx_DCCPARAMS = 0x004,

+ CHIPIDEA_USBx_DCCPARAMS_HC = BIT(8),

+};

+

+static uint64_t chipidea_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ return 0;

+}

+

+static void chipidea_write(void *opaque, hwaddr offset,

+ uint64_t value, unsigned size)

+{

+}

+

+static const struct MemoryRegionOps chipidea_ops = {

+ .read = chipidea_read,

+ .write = chipidea_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .impl = {

+ /*

+ * Our device would not work correctly if the guest was doing

+ * unaligned access. This might not be a limitation on the

+ * real device but in practice there is no reason for a guest

+ * to access this device unaligned.

+ */

+ .min_access_size = 4,

+ .max_access_size = 4,

+ .unaligned = false,

+ },

+};

+

+static uint64_t chipidea_dc_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ switch (offset) {

+ case CHIPIDEA_USBx_DCIVERSION:

+ return 0x1;

+ case CHIPIDEA_USBx_DCCPARAMS:

+ /*

+ * Real hardware (at least i.MX7) will also report the

+ * controller as "Device Capable" (and 8 supported endpoints),

+ * but there doesn't seem to be much point in doing so, since

+ * we don't emulate that part.

+ */

+ return CHIPIDEA_USBx_DCCPARAMS_HC;

+ }

+

+ return 0;

+}

+

+static void chipidea_dc_write(void *opaque, hwaddr offset,

+ uint64_t value, unsigned size)

+{

+}

+

+static const struct MemoryRegionOps chipidea_dc_ops = {

+ .read = chipidea_dc_read,

+ .write = chipidea_dc_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .impl = {

+ /*

+ * Our device would not work correctly if the guest was doing

+ * unaligned access. This might not be a limitation on the real

+ * device but in practice there is no reason for a guest to access

+ * this device unaligned.

+ */

+ .min_access_size = 4,

+ .max_access_size = 4,

+ .unaligned = false,

+ },

+};

+

+static void chipidea_init(Object *obj)

+{

+ EHCIState *ehci = &SYS_BUS_EHCI(obj)->ehci;

+ ChipideaState *ci = CHIPIDEA(obj);

+ int i;

+

+ for (i = 0; i < ARRAY_SIZE(ci->iomem); i++) {

+ const struct {

+ const char *name;

+ hwaddr offset;

+ uint64_t size;

+ const struct MemoryRegionOps *ops;

+ } regions[ARRAY_SIZE(ci->iomem)] = {

+ /*

+ * Registers located between offsets 0x000 and 0xFC

+ */

+ {

+ .name = TYPE_CHIPIDEA ".misc",

+ .offset = 0x000,

+ .size = 0x100,

+ .ops = &chipidea_ops,

+ },

+ /*

+ * Registers located between offsets 0x1A4 and 0x1DC

+ */

+ {

+ .name = TYPE_CHIPIDEA ".endpoints",

+ .offset = 0x1A4,

+ .size = 0x1DC - 0x1A4 + 4,

+ .ops = &chipidea_ops,

+ },

+ /*

+ * USB_x_DCIVERSION and USB_x_DCCPARAMS

+ */

+ {

+ .name = TYPE_CHIPIDEA ".dc",

+ .offset = 0x120,

+ .size = 8,

+ .ops = &chipidea_dc_ops,

+ },

+ };

+

+ memory_region_init_io(&ci->iomem[i],

+ obj,

+ regions[i].ops,

+ ci,

+ regions[i].name,

+ regions[i].size);

+

+ memory_region_add_subregion(&ehci->mem,

+ regions[i].offset,

+ &ci->iomem[i]);

+ }

+}

+

+static void chipidea_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+ SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);

+

+ /*

+ * Offsets used were taken from i.MX7Dual Applications Processor

+ * Reference Manual, Rev 0.1, p. 3177, Table 11-59

+ */

+ sec->capsbase = 0x100;

+ sec->opregbase = 0x140;

+ sec->portnr = 1;

+

+ set_bit(DEVICE_CATEGORY_USB, dc->categories);

+ dc->desc = "Chipidea USB Module";

+}

+

+static const TypeInfo chipidea_info = {

+ .name = TYPE_CHIPIDEA,

+ .parent = TYPE_SYS_BUS_EHCI,

+ .instance_size = sizeof(ChipideaState),

+ .instance_init = chipidea_init,

+ .class_init = chipidea_class_init,

+};

+

+static void chipidea_register_type(void)

+{

+ type_register_static(&chipidea_info);

+}

+type_init(chipidea_register_type)

2.16.1

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add minimal code needed to allow upstream Linux guest to boot.

Cc: Peter Maydell <peter.maydell@linaro.org>

Cc: Jason Wang <jasowang@redhat.com>

Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>

Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com>

Cc: Michael S. Tsirkin <mst@redhat.com>

Cc: qemu-devel@nongnu.org

Cc: qemu-arm@nongnu.org

Cc: yurovsky@gmail.com

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/misc/Makefile.objs | 1 +

include/hw/misc/imx7_gpr.h | 28 ++++++++++

hw/misc/imx7_gpr.c | 124 +++++++++++++++++++++++++++++++++++++++++++++

hw/misc/trace-events | 4 ++

4 files changed, 157 insertions(+)

create mode 100644 include/hw/misc/imx7_gpr.h

create mode 100644 hw/misc/imx7_gpr.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/Makefile.objs

+++ b/hw/misc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IMX) += imx6_src.o

obj-$(CONFIG_IMX) += imx7_ccm.o

obj-$(CONFIG_IMX) += imx2_wdt.o

obj-$(CONFIG_IMX) += imx7_snvs.o

+obj-$(CONFIG_IMX) += imx7_gpr.o

obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o

obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o

obj-$(CONFIG_MAINSTONE) += mst_fpga.o

diff --git a/include/hw/misc/imx7_gpr.h b/include/hw/misc/imx7_gpr.h

+++ b/include/hw/misc/imx7_gpr.h

+/*

+ * Copyright (c) 2017, Impinj, Inc.

+ *

+ * i.MX7 GPR IP block emulation code

+ *

+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+#ifndef IMX7_GPR_H

+#define IMX7_GPR_H

+#include "qemu/bitops.h"

+#include "hw/sysbus.h"

+#define TYPE_IMX7_GPR "imx7.gpr"

+#define IMX7_GPR(obj) OBJECT_CHECK(IMX7GPRState, (obj), TYPE_IMX7_GPR)

+

+typedef struct IMX7GPRState {

+ /* <private> */

+ SysBusDevice parent_obj;

+

+ MemoryRegion mmio;

+} IMX7GPRState;

+

+#endif /* IMX7_GPR_H */

diff --git a/hw/misc/imx7_gpr.c b/hw/misc/imx7_gpr.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/misc/imx7_gpr.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Copyright (c) 2018, Impinj, Inc.

+ *

+ * i.MX7 GPR IP block emulation code

+ *

+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ *

+ * Bare minimum emulation code needed to support being able to shut

+ * down linux guest gracefully.

+ */

+

+#include "qemu/osdep.h"

+#include "hw/misc/imx7_gpr.h"

+#include "qemu/log.h"

+#include "sysemu/sysemu.h"

+

+#include "trace.h"

+

+enum IMX7GPRRegisters {

+ IOMUXC_GPR0 = 0x00,

+ IOMUXC_GPR1 = 0x04,

+ IOMUXC_GPR2 = 0x08,

+ IOMUXC_GPR3 = 0x0c,

+ IOMUXC_GPR4 = 0x10,

+ IOMUXC_GPR5 = 0x14,

+ IOMUXC_GPR6 = 0x18,

+ IOMUXC_GPR7 = 0x1c,

+ IOMUXC_GPR8 = 0x20,

+ IOMUXC_GPR9 = 0x24,

+ IOMUXC_GPR10 = 0x28,

+ IOMUXC_GPR11 = 0x2c,

+ IOMUXC_GPR12 = 0x30,

+ IOMUXC_GPR13 = 0x34,

+ IOMUXC_GPR14 = 0x38,

+ IOMUXC_GPR15 = 0x3c,

+ IOMUXC_GPR16 = 0x40,

+ IOMUXC_GPR17 = 0x44,

+ IOMUXC_GPR18 = 0x48,

+ IOMUXC_GPR19 = 0x4c,

+ IOMUXC_GPR20 = 0x50,

+ IOMUXC_GPR21 = 0x54,

+ IOMUXC_GPR22 = 0x58,

+};

+

+#define IMX7D_GPR1_IRQ_MASK BIT(12)

+#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK BIT(13)

+#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK BIT(14)

+#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)

+#define IMX7D_GPR1_ENET1_CLK_DIR_MASK BIT(17)

+#define IMX7D_GPR1_ENET2_CLK_DIR_MASK BIT(18)

+#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)

+

+#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI BIT(4)

+#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5)

+#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31)

+

+

+static uint64_t imx7_gpr_read(void *opaque, hwaddr offset, unsigned size)

+{

+ trace_imx7_gpr_read(offset);

+

+ if (offset == IOMUXC_GPR22) {

+ return IMX7D_GPR22_PCIE_PHY_PLL_LOCKED;

+ }

+

+ return 0;

+}

+

+static void imx7_gpr_write(void *opaque, hwaddr offset,

+ uint64_t v, unsigned size)

+{

+ trace_imx7_gpr_write(offset, v);

+}

+

+static const struct MemoryRegionOps imx7_gpr_ops = {

+ .read = imx7_gpr_read,

+ .write = imx7_gpr_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .impl = {

+ /*

+ * Our device would not work correctly if the guest was doing

+ * unaligned access. This might not be a limitation on the

+ * real device but in practice there is no reason for a guest

+ * to access this device unaligned.

+ */

+ .min_access_size = 4,

+ .max_access_size = 4,

+ .unaligned = false,

+ },

+};

+

+static void imx7_gpr_init(Object *obj)

+{

+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);

+ IMX7GPRState *s = IMX7_GPR(obj);

+

+ memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s,

+ TYPE_IMX7_GPR, 64 * 1024);

+ sysbus_init_mmio(sd, &s->mmio);

+}

+

+static void imx7_gpr_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->desc = "i.MX7 General Purpose Registers Module";

+}

+

+static const TypeInfo imx7_gpr_info = {

+ .name = TYPE_IMX7_GPR,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(IMX7GPRState),

+ .instance_init = imx7_gpr_init,

+ .class_init = imx7_gpr_class_init,

+};

+

+static void imx7_gpr_register_type(void)

+{

+ type_register_static(&imx7_gpr_info);

+}

+type_init(imx7_gpr_register_type)

diff --git a/hw/misc/trace-events b/hw/misc/trace-events

--- a/hw/misc/trace-events

+++ b/hw/misc/trace-events

@@ -XXX,XX +XXX,XX @@ mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC

msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32

msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32

msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"

+

+#hw/misc/imx7_gpr.c

+imx7_gpr_read(uint64_t offset) "addr 0x%08" HWADDR_PRIx

+imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" HWADDR_PRIx "value 0x%08" HWADDR_PRIx

2.16.1

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Add minimal code needed to allow upstream Linux guest to boot.

Cc: Peter Maydell <peter.maydell@linaro.org>

Cc: Jason Wang <jasowang@redhat.com>

Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>

Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com>

Cc: Michael S. Tsirkin <mst@redhat.com>

Cc: qemu-devel@nongnu.org

Cc: qemu-arm@nongnu.org

Cc: yurovsky@gmail.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/intc/Makefile.objs | 2 +-

include/hw/intc/imx_gpcv2.h | 22 ++++++++

hw/intc/imx_gpcv2.c | 125 ++++++++++++++++++++++++++++++++++++++++++++

3 files changed, 148 insertions(+), 1 deletion(-)

create mode 100644 include/hw/intc/imx_gpcv2.h

create mode 100644 hw/intc/imx_gpcv2.c

diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/Makefile.objs

+++ b/hw/intc/Makefile.objs

@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XILINX) += xilinx_intc.o

common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-intc.o

common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-ipi.o

common-obj-$(CONFIG_ETRAXFS) += etraxfs_pic.o

-common-obj-$(CONFIG_IMX) += imx_avic.o

+common-obj-$(CONFIG_IMX) += imx_avic.o imx_gpcv2.o

common-obj-$(CONFIG_LM32) += lm32_pic.o

common-obj-$(CONFIG_REALVIEW) += realview_gic.o

common-obj-$(CONFIG_SLAVIO) += slavio_intctl.o

diff --git a/include/hw/intc/imx_gpcv2.h b/include/hw/intc/imx_gpcv2.h

+++ b/include/hw/intc/imx_gpcv2.h

+#ifndef IMX_GPCV2_H

+#define IMX_GPCV2_H

+#include "hw/sysbus.h"

+enum IMXGPCv2Registers {

+ GPC_NUM = 0xE00 / sizeof(uint32_t),

+};

+typedef struct IMXGPCv2State {

+ /*< private >*/

+ SysBusDevice parent_obj;

+

+ /*< public >*/

+ MemoryRegion iomem;

+ uint32_t regs[GPC_NUM];

+} IMXGPCv2State;

+

+#define TYPE_IMX_GPCV2 "imx-gpcv2"

+#define IMX_GPCV2(obj) OBJECT_CHECK(IMXGPCv2State, (obj), TYPE_IMX_GPCV2)

+

+#endif /* IMX_GPCV2_H */

diff --git a/hw/intc/imx_gpcv2.c b/hw/intc/imx_gpcv2.c

new file mode 100644

index XXXXXXX..XXXXXXX

--- /dev/null

+++ b/hw/intc/imx_gpcv2.c

@@ -XXX,XX +XXX,XX @@

+/*

+ * Copyright (c) 2018, Impinj, Inc.

+ *

+ * i.MX7 GPCv2 block emulation code

+ *

+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+#include "qemu/osdep.h"

+#include "hw/intc/imx_gpcv2.h"

+#include "qemu/log.h"

+

+#define GPC_PU_PGC_SW_PUP_REQ 0x0f8

+#define GPC_PU_PGC_SW_PDN_REQ 0x104

+

+#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)

+#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)

+#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)

+#define PCIE_PHY_SW_Pxx_REQ BIT(1)

+#define MIPI_PHY_SW_Pxx_REQ BIT(0)

+

+

+static void imx_gpcv2_reset(DeviceState *dev)

+{

+ IMXGPCv2State *s = IMX_GPCV2(dev);

+

+ memset(s->regs, 0, sizeof(s->regs));

+}

+

+static uint64_t imx_gpcv2_read(void *opaque, hwaddr offset,

+ unsigned size)

+{

+ IMXGPCv2State *s = opaque;

+

+ return s->regs[offset / sizeof(uint32_t)];

+}

+

+static void imx_gpcv2_write(void *opaque, hwaddr offset,

+ uint64_t value, unsigned size)

+{

+ IMXGPCv2State *s = opaque;

+ const size_t idx = offset / sizeof(uint32_t);

+

+ s->regs[idx] = value;

+

+ /*

+ * Real HW will clear those bits once as a way to indicate that

+ * power up request is complete

+ */

+ if (offset == GPC_PU_PGC_SW_PUP_REQ ||

+ offset == GPC_PU_PGC_SW_PDN_REQ) {

+ s->regs[idx] &= ~(USB_HSIC_PHY_SW_Pxx_REQ |

+ USB_OTG2_PHY_SW_Pxx_REQ |

+ USB_OTG1_PHY_SW_Pxx_REQ |

+ PCIE_PHY_SW_Pxx_REQ |

+ MIPI_PHY_SW_Pxx_REQ);

+ }

+}

+

+static const struct MemoryRegionOps imx_gpcv2_ops = {

+ .read = imx_gpcv2_read,

+ .write = imx_gpcv2_write,

+ .endianness = DEVICE_NATIVE_ENDIAN,

+ .impl = {

+ /*

+ * Our device would not work correctly if the guest was doing

+ * unaligned access. This might not be a limitation on the real

+ * device but in practice there is no reason for a guest to access

+ * this device unaligned.

+ */

+ .min_access_size = 4,

+ .max_access_size = 4,

+ .unaligned = false,

+ },

+};

+

+static void imx_gpcv2_init(Object *obj)

+{

+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);

+ IMXGPCv2State *s = IMX_GPCV2(obj);

+

+ memory_region_init_io(&s->iomem,

+ obj,

+ &imx_gpcv2_ops,

+ s,

+ TYPE_IMX_GPCV2 ".iomem",

+ sizeof(s->regs));

+ sysbus_init_mmio(sd, &s->iomem);

+}

+

+static const VMStateDescription vmstate_imx_gpcv2 = {

+ .name = TYPE_IMX_GPCV2,

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT32_ARRAY(regs, IMXGPCv2State, GPC_NUM),

+ VMSTATE_END_OF_LIST()

+ },

+};

+

+static void imx_gpcv2_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->reset = imx_gpcv2_reset;

+ dc->vmsd = &vmstate_imx_gpcv2;

+ dc->desc = "i.MX GPCv2 Module";

+}

+

+static const TypeInfo imx_gpcv2_info = {

+ .name = TYPE_IMX_GPCV2,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(IMXGPCv2State),

+ .instance_init = imx_gpcv2_init,

+ .class_init = imx_gpcv2_class_init,

+};

+

+static void imx_gpcv2_register_type(void)

+{

+ type_register_static(&imx_gpcv2_info);

+}

+type_init(imx_gpcv2_register_type)

2.16.1

From: Christoffer Dall <christoffer.dall@linaro.org>

KVM doesn't support emulating a GICv3 in userspace, only GICv2. We

currently attempt this anyway, and as a result a KVM guest doesn't

receive interrupts and the user is left wondering why. Report an error

to the user if this particular combination is requested.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20180201205307.30343-1-christoffer.dall@linaro.org

target/arm/kvm_arm.h | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h

--- a/target/arm/kvm_arm.h

+++ b/target/arm/kvm_arm.h

@@ -XXX,XX +XXX,XX @@ static inline const char *gicv3_class_name(void)

exit(1);

#endif

} else {

+ if (kvm_enabled()) {

+ error_report("Userspace GICv3 is not supported with KVM");

+ exit(1);

+ }

return "arm-gicv3";

}

}

2.16.1

From: Ard Biesheuvel <ard.biesheuvel@linaro.org>

This implements emulation of the new SM3 instructions that have

been added as an optional extension to the ARMv8 Crypto Extensions

in ARM v8.2.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Message-id: 20180207111729.15737-4-ard.biesheuvel@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 1 +

target/arm/helper.h | 4 ++

target/arm/crypto_helper.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++

target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++++++++++++--

4 files changed, 186 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ enum arm_features {

ARM_FEATURE_SVE, /* has Scalable Vector Extension */

ARM_FEATURE_V8_SHA512, /* implements SHA512 part of v8 Crypto Extensions */

ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */

+ ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */

};

static inline int arm_feature(CPUARMState *env, int feature)

diff --git a/target/arm/helper.h b/target/arm/helper.h

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(crypto_sha512h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

DEF_HELPER_FLAGS_2(crypto_sha512su0, TCG_CALL_NO_RWG, void, ptr, ptr)

DEF_HELPER_FLAGS_3(crypto_sha512su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

+DEF_HELPER_FLAGS_5(crypto_sm3tt, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32, i32)

+DEF_HELPER_FLAGS_3(crypto_sm3partw1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

+DEF_HELPER_FLAGS_3(crypto_sm3partw2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr)

+

DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)

DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)

DEF_HELPER_2(dc_zva, void, env, i64)

diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c

--- a/target/arm/crypto_helper.c

+++ b/target/arm/crypto_helper.c

@@ -XXX,XX +XXX,XX @@ void HELPER(crypto_sha512su1)(void *vd, void *vn, void *vm)

rd[0] += s1_512(rn[0]) + rm[0];

rd[1] += s1_512(rn[1]) + rm[1];

}

+

+void HELPER(crypto_sm3partw1)(void *vd, void *vn, void *vm)

+{

+ uint64_t *rd = vd;

+ uint64_t *rn = vn;

+ uint64_t *rm = vm;

+ union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };

+ union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };

+ union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };

+ uint32_t t;

+

+ t = CR_ST_WORD(d, 0) ^ CR_ST_WORD(n, 0) ^ ror32(CR_ST_WORD(m, 1), 17);

+ CR_ST_WORD(d, 0) = t ^ ror32(t, 17) ^ ror32(t, 9);

+

+ t = CR_ST_WORD(d, 1) ^ CR_ST_WORD(n, 1) ^ ror32(CR_ST_WORD(m, 2), 17);

+ CR_ST_WORD(d, 1) = t ^ ror32(t, 17) ^ ror32(t, 9);

+

+ t = CR_ST_WORD(d, 2) ^ CR_ST_WORD(n, 2) ^ ror32(CR_ST_WORD(m, 3), 17);

+ CR_ST_WORD(d, 2) = t ^ ror32(t, 17) ^ ror32(t, 9);

+

+ t = CR_ST_WORD(d, 3) ^ CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(d, 0), 17);

+ CR_ST_WORD(d, 3) = t ^ ror32(t, 17) ^ ror32(t, 9);

+

+ rd[0] = d.l[0];

+ rd[1] = d.l[1];

+}

+

+void HELPER(crypto_sm3partw2)(void *vd, void *vn, void *vm)

+{

+ uint64_t *rd = vd;

+ uint64_t *rn = vn;

+ uint64_t *rm = vm;

+ union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };

+ union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };

+ union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };

+ uint32_t t = CR_ST_WORD(n, 0) ^ ror32(CR_ST_WORD(m, 0), 25);

+

+ CR_ST_WORD(d, 0) ^= t;

+ CR_ST_WORD(d, 1) ^= CR_ST_WORD(n, 1) ^ ror32(CR_ST_WORD(m, 1), 25);

+ CR_ST_WORD(d, 2) ^= CR_ST_WORD(n, 2) ^ ror32(CR_ST_WORD(m, 2), 25);

+ CR_ST_WORD(d, 3) ^= CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(m, 3), 25) ^

+ ror32(t, 17) ^ ror32(t, 2) ^ ror32(t, 26);

+

+ rd[0] = d.l[0];

+ rd[1] = d.l[1];

+}

+

+void HELPER(crypto_sm3tt)(void *vd, void *vn, void *vm, uint32_t imm2,

+ uint32_t opcode)

+{

+ uint64_t *rd = vd;

+ uint64_t *rn = vn;

+ uint64_t *rm = vm;

+ union CRYPTO_STATE d = { .l = { rd[0], rd[1] } };

+ union CRYPTO_STATE n = { .l = { rn[0], rn[1] } };

+ union CRYPTO_STATE m = { .l = { rm[0], rm[1] } };

+ uint32_t t;

+

+ assert(imm2 < 4);

+

+ if (opcode == 0 || opcode == 2) {

+ /* SM3TT1A, SM3TT2A */

+ t = par(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1));

+ } else if (opcode == 1) {

+ /* SM3TT1B */

+ t = maj(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1));

+ } else if (opcode == 3) {

+ /* SM3TT2B */

+ t = cho(CR_ST_WORD(d, 3), CR_ST_WORD(d, 2), CR_ST_WORD(d, 1));

+ } else {

+ g_assert_not_reached();

+ }

+

+ t += CR_ST_WORD(d, 0) + CR_ST_WORD(m, imm2);

+

+ CR_ST_WORD(d, 0) = CR_ST_WORD(d, 1);

+

+ if (opcode < 2) {

+ /* SM3TT1A, SM3TT1B */

+ t += CR_ST_WORD(n, 3) ^ ror32(CR_ST_WORD(d, 3), 20);

+

+ CR_ST_WORD(d, 1) = ror32(CR_ST_WORD(d, 2), 23);

+ } else {

+ /* SM3TT2A, SM3TT2B */

+ t += CR_ST_WORD(n, 3);

+ t ^= rol32(t, 9) ^ rol32(t, 17);

+

+ CR_ST_WORD(d, 1) = ror32(CR_ST_WORD(d, 2), 13);

+ }

+

+ CR_ST_WORD(d, 2) = CR_ST_WORD(d, 3);

+ CR_ST_WORD(d, 3) = t;

+

+ rd[0] = d.l[0];

+ rd[1] = d.l[1];

+}

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)

break;

}

} else {

- unallocated_encoding(s);

- return;

+ switch (opcode) {

+ case 0: /* SM3PARTW1 */

+ feature = ARM_FEATURE_V8_SM3;

+ genfn = gen_helper_crypto_sm3partw1;

+ break;

+ case 1: /* SM3PARTW2 */

+ feature = ARM_FEATURE_V8_SM3;

+ genfn = gen_helper_crypto_sm3partw2;

+ break;

+ default:

+ unallocated_encoding(s);

+ return;

+ }

}

if (!arm_dc_feature(s, feature)) {

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)

case 1: /* BCAX */

feature = ARM_FEATURE_V8_SHA3;

break;

+ case 2: /* SM3SS1 */

+ feature = ARM_FEATURE_V8_SM3;

+ break;

default:

unallocated_encoding(s);

return;

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)

tcg_temp_free_i64(tcg_res[0]);

tcg_temp_free_i64(tcg_res[1]);

} else {

- g_assert_not_reached();

+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero;

+

+ tcg_op1 = tcg_temp_new_i32();

+ tcg_op2 = tcg_temp_new_i32();

+ tcg_op3 = tcg_temp_new_i32();

+ tcg_res = tcg_temp_new_i32();

+ tcg_zero = tcg_const_i32(0);

+

+ read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);

+ read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);

+ read_vec_element_i32(s, tcg_op3, ra, 3, MO_32);

+

+ tcg_gen_rotri_i32(tcg_res, tcg_op1, 20);

+ tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2);

+ tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3);

+ tcg_gen_rotri_i32(tcg_res, tcg_res, 25);

+

+ write_vec_element_i32(s, tcg_zero, rd, 0, MO_32);

+ write_vec_element_i32(s, tcg_zero, rd, 1, MO_32);

+ write_vec_element_i32(s, tcg_zero, rd, 2, MO_32);

+ write_vec_element_i32(s, tcg_res, rd, 3, MO_32);

+

+ tcg_temp_free_i32(tcg_op1);

+ tcg_temp_free_i32(tcg_op2);

+ tcg_temp_free_i32(tcg_op3);

+ tcg_temp_free_i32(tcg_res);

+ tcg_temp_free_i32(tcg_zero);

}

}

@@ -XXX,XX +XXX,XX @@ static void disas_crypto_xar(DisasContext *s, uint32_t insn)

tcg_temp_free_i64(tcg_res[1]);

}

+/* Crypto three-reg imm2

+ * 31 21 20 16 15 14 13 12 11 10 9 5 4 0

+ * +-----------------------+------+-----+------+--------+------+------+

+ * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |

+ * +-----------------------+------+-----+------+--------+------+------+

+ */

+static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)

+{

+ int opcode = extract32(insn, 10, 2);

+ int imm2 = extract32(insn, 12, 2);

+ int rm = extract32(insn, 16, 5);

+ int rn = extract32(insn, 5, 5);

+ int rd = extract32(insn, 0, 5);

+ TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;

+ TCGv_i32 tcg_imm2, tcg_opcode;

+

+ if (!arm_dc_feature(s, ARM_FEATURE_V8_SM3)) {

+ unallocated_encoding(s);

+ return;

+ }

+

+ if (!fp_access_check(s)) {

+ return;

+ }

+

+ tcg_rd_ptr = vec_full_reg_ptr(s, rd);

+ tcg_rn_ptr = vec_full_reg_ptr(s, rn);

+ tcg_rm_ptr = vec_full_reg_ptr(s, rm);

+ tcg_imm2 = tcg_const_i32(imm2);

+ tcg_opcode = tcg_const_i32(opcode);

+

+ gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2,

+ tcg_opcode);

+

+ tcg_temp_free_ptr(tcg_rd_ptr);

+ tcg_temp_free_ptr(tcg_rn_ptr);

+ tcg_temp_free_ptr(tcg_rm_ptr);

+ tcg_temp_free_i32(tcg_imm2);

+ tcg_temp_free_i32(tcg_opcode);

+}

+

/* C3.6 Data processing - SIMD, inc Crypto

*

* As the decode gets a little complex we are using a table based

@@ -XXX,XX +XXX,XX @@ static const AArch64DecodeTable data_proc_simd[] = {

{ 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 },

{ 0xce000000, 0xff808000, disas_crypto_four_reg },

{ 0xce800000, 0xffe00000, disas_crypto_xar },

+ { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },

{ 0x00000000, 0x00000000, NULL }

};

2.16.1

From: Richard Henderson <richard.henderson@linaro.org>

Add both SVE exception state and vector length.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20180123035349.24538-6-richard.henderson@linaro.org