[v6] target-arm: add SHA-3, SM3 and SHA512 instruction support

[Qemu-devel] [PATCH v6 0/5] target-arm: add SHA-3, SM3 and SHA512 instruction support

Ard Biesheuvel posted 5 patches 6 years, 2 months ago

Diff against v3 v4 v5
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20180207111729.15737-1-ard.biesheuvel@linaro.org

Test checkpatch passed

Test docker-build@min-glib passed

Test docker-mingw@fedora passed

Test docker-quick@centos6 passed

Test ppc passed

Test s390x passed

linux-user/elfload.c       |  19 ++
target/arm/cpu.h           |   4 +
target/arm/cpu64.c         |   4 +
target/arm/crypto_helper.c | 277 +++++++++++++++-
target/arm/helper.h        |  12 +
target/arm/translate-a64.c | 340 ++++++++++++++++++++
6 files changed, 655 insertions(+), 1 deletion(-)

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[Qemu-devel] [PATCH v6 0/5] target-arm: add SHA-3, SM3 and SHA512 instruction support

Posted by Ard Biesheuvel 6 years, 2 months ago

Changes since v5:
- fix use of same register for destination and source in SHA-512 code
- use correct free() function in SHA-3 code
- drop helper for sm3ss1 in SM3 code
- include fixed version of SM4 (correct # of iterations)
- enable SM4 in user mode emulator

Changes since v4:
- restructure code changes to make it easier on the reviewer
- add Peter's R-b to #4

Changes since v3:
- don't bother with helpers for the SHA3 instructions: they are simple enough
  to be emitted as TCG ops directly
- rebase onto Richard's pending SVE work

Changes since v2:
- fix thinko in big-endian aware handling of 64-bit quantities: this is not
  needed given that the NEON registers are represented as arrays of uint64_t
  so they always appear in the correct order.
- add support for SM3 instructions (Chinese SHA derivative)

Changes since v1:
- update SHA512 patch to adhere more closely to the existing style, and to
  the way the instruction encodings are classified in the ARM ARM (#1)
- add patch implementing the new SHA3 instructions EOR3/RAX1/XAR/BCAX (#2)
- enable support for these instructions in user mode emulation (#3)

Ard Biesheuvel (5):
  target/arm: implement SHA-512 instructions
  target/arm: implement SHA-3 instructions
  target/arm: implement SM3 instructions
  target/arm: implement SM4 instructions
  target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction
    support

 linux-user/elfload.c       |  19 ++
 target/arm/cpu.h           |   4 +
 target/arm/cpu64.c         |   4 +
 target/arm/crypto_helper.c | 277 +++++++++++++++-
 target/arm/helper.h        |  12 +
 target/arm/translate-a64.c | 340 ++++++++++++++++++++
 6 files changed, 655 insertions(+), 1 deletion(-)

-- 
2.11.0

Re: [Qemu-devel] [PATCH v6 0/5] target-arm: add SHA-3, SM3 and SHA512 instruction support

Posted by Peter Maydell 6 years, 2 months ago

On 7 February 2018 at 11:17, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> Changes since v5:
> - fix use of same register for destination and source in SHA-512 code
> - use correct free() function in SHA-3 code
> - drop helper for sm3ss1 in SM3 code
> - include fixed version of SM4 (correct # of iterations)
> - enable SM4 in user mode emulator

Thanks -- this version passes all my tests and I've put it into
target-arm.next.

-- PMM