[Qemu-devel] [PATCH 3/4] hw/intc/arm_gic: Fix group priority computation for group 1 IRQs

luc.michel@greensocs.com posted 4 patches 8 years ago
[Qemu-devel] [PATCH 3/4] hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
Posted by luc.michel@greensocs.com 8 years ago
From: Luc MICHEL <luc.michel@git.antfield.fr>

When determining the group priority of a group 1 IRQ, if C_CTRL.CBPR is
0, the non-secure BPR value is used. However, this value must be
incremented by one so that it matches the secure world number of
implemented priority bits (NS world has one less priority bit compared
to the Secure world).

Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr>
---
 hw/intc/arm_gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 713de3084f..d0a41a89ae 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -256,7 +256,7 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq)
     if (gic_has_groups(s) &&
         !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&
         GIC_TEST_GROUP(irq, (1 << cpu))) {
-        bpr = s->abpr[cpu];
+        bpr = s->abpr[cpu] - 1;
     } else {
         bpr = s->bpr[cpu];
     }
-- 
2.16.0


Re: [Qemu-devel] [PATCH 3/4] hw/intc/arm_gic: Fix group priority computation for group 1 IRQs
Posted by Peter Maydell 8 years ago
On 19 January 2018 at 14:57,  <luc.michel@greensocs.com> wrote:
> From: Luc MICHEL <luc.michel@git.antfield.fr>
>
> When determining the group priority of a group 1 IRQ, if C_CTRL.CBPR is
> 0, the non-secure BPR value is used. However, this value must be
> incremented by one so that it matches the secure world number of
> implemented priority bits (NS world has one less priority bit compared
> to the Secure world).
>
> Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr>
> ---
>  hw/intc/arm_gic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index 713de3084f..d0a41a89ae 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -256,7 +256,7 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq)
>      if (gic_has_groups(s) &&
>          !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&
>          GIC_TEST_GROUP(irq, (1 << cpu))) {
> -        bpr = s->abpr[cpu];
> +        bpr = s->abpr[cpu] - 1;

I would suggest an "assert(bpr >= 0);" here. (We have a similar
assert for GICv3 in icv_gprio_mask() and icc_gprio_mask() in
arm_gicv3_cpuif.c.)

>      } else {
>          bpr = s->bpr[cpu];
>      }
> --
> 2.16.0

thanks
-- PMM