On Fri, Dec 29, 2017 at 9:49 AM, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> running qtests:
>
> $ make check-qtest-arm
> GTESTER check-qtest-arm
> SDHC rd_4b @0x44 not implemented
> SDHC wr_4b @0x40 <- 0x89abcdef not implemented
> SDHC wr_4b @0x44 <- 0x01234567 not implemented
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Alistair
> ---
> include/hw/sd/sdhci.h | 4 ++--
> hw/sd/sdhci.c | 23 +++++++++++++++++++----
> 2 files changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
> index da943a6562..9436375b1e 100644
> --- a/include/hw/sd/sdhci.h
> +++ b/include/hw/sd/sdhci.h
> @@ -86,9 +86,9 @@ typedef struct SDHCIState {
>
> /* Read-only registers */
> /* 0x40 */
> - uint32_t capareg; /* Capabilities Register */
> + uint64_t capareg; /* Capabilities Register */
> /* 0x48 */
> - uint32_t maxcurr; /* Maximum Current Capabilities Register */
> + uint64_t maxcurr; /* Maximum Current Capabilities Register */
>
> uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
> uint32_t buf_maxsz;
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 604ad525f6..ae84af46da 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -904,10 +904,16 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
> ret = s->acmd12errsts;
> break;
> case SDHC_CAPAB:
> - ret = s->capareg;
> + ret = (uint32_t)s->capareg;
> + break;
> + case SDHC_CAPAB + 4:
> + ret = (uint32_t)(s->capareg >> 32);
> break;
> case SDHC_MAXCURR:
> - ret = s->maxcurr;
> + ret = (uint32_t)s->maxcurr;
> + break;
> + case SDHC_MAXCURR + 4:
> + ret = (uint32_t)(s->maxcurr >> 32);
> break;
> case SDHC_ADMAERR:
> ret = s->admaerr;
> @@ -1129,6 +1135,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
> }
> sdhci_update_irq(s);
> break;
> +
> + case SDHC_CAPAB:
> + case SDHC_CAPAB + 4:
> + case SDHC_MAXCURR:
> + case SDHC_MAXCURR + 4:
> + qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
> + " <- 0x%08x read-only\n", size, offset, value >> shift);
> + break;
> +
> default:
> qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
> "not implemented\n", size, offset, value >> shift);
> @@ -1260,9 +1275,9 @@ const VMStateDescription sdhci_vmstate = {
> /* Capabilities registers provide information on supported features of this
> * specific host controller implementation */
> static Property sdhci_properties[] = {
> - DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
> + DEFINE_PROP_UINT64("capareg", SDHCIState, capareg,
> SDHC_CAPAB_REG_DEFAULT),
> - DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
> + DEFINE_PROP_UINT64("maxcurr", SDHCIState, maxcurr, 0),
> DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
> false),
> DEFINE_PROP_END_OF_LIST(),
> --
> 2.15.1
>
>