This patch set does a few things. First, it switches the AMD CFI flash MMIO
operations from the old MMIO API to the new one. Second, it enables 8-byte
wide flash arrays. Finally, it supports rudimentary interleaving of notional
flash "chips". It is expected that commands will be sent to all "chips"
simultaneously. See the example in the second patch for more details. This
behavior is used by drivers for the PPMC7400 PowerPC evaluation board.

Mike Nawrocki (2):
  Add 8-byte access to AMD CFI devices
  Add support for flash interleaving of AMD chips

 hw/arm/digic_boards.c    |   2 +-
 hw/arm/musicpal.c        |   4 +-
 hw/arm/xilinx_zynq.c     |   2 +-
 hw/block/pflash_cfi02.c  | 210 ++++++++++++++++++++++++++---------------------
 hw/lm32/lm32_boards.c    |   4 +-
 hw/ppc/ppc405_boards.c   |  15 ++--
 hw/sh4/r2d.c             |   2 +-
 include/hw/block/flash.h |   1 +
 8 files changed, 132 insertions(+), 108 deletions(-)

-- 
2.14.2

On 31 October 2017 at 15:44, Mike Nawrocki
<michael.nawrocki@gtri.gatech.edu> wrote:
> This patch set does a few things. First, it switches the AMD CFI flash MMIO
> operations from the old MMIO API to the new one. Second, it enables 8-byte
> wide flash arrays. Finally, it supports rudimentary interleaving of notional
> flash "chips". It is expected that commands will be sent to all "chips"
> simultaneously. See the example in the second patch for more details. This
> behavior is used by drivers for the PPMC7400 PowerPC evaluation board.

I'm confused by the interleaving part. Can you explain how this
differs from the interleaving we already support in pflash_cfi01.c
via setting width, device-width and max-device-width ? (see the comment
in the pflash_cfi01_properties[] array about how those settings
interact). If it is the same thing, we should really implement it
in the same way for both kinds of flash device.

thanks
-- PMM

On 10/31/17, 13:00, "Peter Maydell" <peter.maydell@linaro.org> wrote:

    On 31 October 2017 at 15:44, Mike Nawrocki
    <michael.nawrocki@gtri.gatech.edu> wrote:
    > This patch set does a few things. First, it switches the AMD CFI flash MMIO
    > operations from the old MMIO API to the new one. Second, it enables 8-byte
    > wide flash arrays. Finally, it supports rudimentary interleaving of notional
    > flash "chips". It is expected that commands will be sent to all "chips"
    > simultaneously. See the example in the second patch for more details. This
    > behavior is used by drivers for the PPMC7400 PowerPC evaluation board.
    
    I'm confused by the interleaving part. Can you explain how this
    differs from the interleaving we already support in pflash_cfi01.c
    via setting width, device-width and max-device-width ? (see the comment
    in the pflash_cfi01_properties[] array about how those settings
    interact). If it is the same thing, we should really implement it
    in the same way for both kinds of flash device.
    
    thanks
    -- PMM
    

Looking through pflash_cfi01.c, it looks essentially the same, though my code doesn’t represent max_device_width. The interleaving in pflash_cfi01.c is more robust than what I implemented. Should I revert the changes to the pflash_cfi02_register prototype and mirror the qdev property implementation pflash_cfi01 uses? This would drastically reduce the number of files affected.

Thanks,
Mike