[Qemu-devel] [PULL 0/1] tcg patch queue
[PULL v2.5 00/27] tcg patch queue
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Just one patch, but should make stable 2.10.1 this week.
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v2: Fix target/loongarch printf formats for vaddr
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Include two more reviewed patches.
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This time with actual pull urls. :-/
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r~
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r~
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The following changes since commit 460b6c8e581aa06b86f59eebd9e52edfe7adf417:
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The following changes since commit db7aa99ef894e88fc5eedf02ca2579b8c344b2ec:
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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2017-09-23 12:55:40 +0100)
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Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging (2025-02-16 20:48:06 -0500)
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are available in the git repository at:
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are available in the Git repository at:
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git://github.com/rth7680/qemu.git tags/pull-tcg-20170925
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20250215-2
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for you to fetch changes up to 8b81253332b5a3f3c67b6462f39caef47a00dd29:
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for you to fetch changes up to a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb:
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accel/tcg/cputlb: avoid recursive BQL (fixes #1706296) (2017-09-25 11:23:30 -0700)
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 (2025-02-17 09:52:07 -0800)
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----------------------------------------------------------------
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----------------------------------------------------------------
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BQL bug fix
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tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
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tcg: Cleanups after disallowing 64-on-32
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tcg: Introduce constraint for zero register
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
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tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
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linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
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linux-user: Fix alignment when unmapping excess reservation
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target/sparc: Fix register selection for all F*TOx and FxTO* instructions
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target/sparc: Fix gdbstub incorrectly handling registers f32-f62
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target/sparc: fake UltraSPARC T1 PCR and PIC registers
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alex Bennée (1):
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Andreas Schwab (1):
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accel/tcg/cputlb: avoid recursive BQL (fixes #1706296)
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linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
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accel/tcg/cputlb.c | 4 ++--
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Artyom Tarasenko (1):
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1 file changed, 2 insertions(+), 2 deletions(-)
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target/sparc: fake UltraSPARC T1 PCR and PIC registers
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Fabiano Rosas (1):
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elfload: Fix alignment when unmapping excess reservation
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Mikael Szreder (2):
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target/sparc: Fix register selection for all F*TOx and FxTO* instructions
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target/sparc: Fix gdbstub incorrectly handling registers f32-f62
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Richard Henderson (22):
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tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
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tcg: Remove TCG_OVERSIZED_GUEST
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tcg: Drop support for two address registers in gen_ldst
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tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
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tcg/arm: Drop addrhi from prepare_host_addr
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tcg/i386: Drop addrhi from prepare_host_addr
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tcg/mips: Drop addrhi from prepare_host_addr
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tcg/ppc: Drop addrhi from prepare_host_addr
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tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
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plugins: Fix qemu_plugin_read_memory_vaddr parameters
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accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
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target/loongarch: Use VADDR_PRIx for logging pc_next
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include/exec: Change vaddr to uintptr_t
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include/exec: Use uintptr_t in CPUTLBEntry
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tcg: Introduce the 'z' constraint for a hardware zero register
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tcg/aarch64: Use 'z' constraint
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tcg/loongarch64: Use 'z' constraint
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tcg/mips: Use 'z' constraint
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tcg/riscv: Use 'z' constraint
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tcg/sparc64: Use 'z' constraint
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tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
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tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
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include/exec/tlb-common.h | 10 +-
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include/exec/vaddr.h | 16 +-
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include/qemu/atomic.h | 18 +-
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include/tcg/oversized-guest.h | 23 ---
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include/tcg/tcg-opc.h | 28 +--
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include/tcg/tcg.h | 3 +-
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linux-user/aarch64/target_signal.h | 2 +
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linux-user/arm/target_signal.h | 2 +
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linux-user/generic/signal.h | 1 -
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linux-user/i386/target_signal.h | 2 +
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linux-user/m68k/target_signal.h | 1 +
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linux-user/microblaze/target_signal.h | 2 +
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linux-user/ppc/target_signal.h | 2 +
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linux-user/s390x/target_signal.h | 2 +
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linux-user/sh4/target_signal.h | 2 +
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linux-user/x86_64/target_signal.h | 2 +
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linux-user/xtensa/target_signal.h | 2 +
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tcg/aarch64/tcg-target-con-set.h | 12 +-
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tcg/aarch64/tcg-target.h | 2 +
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tcg/loongarch64/tcg-target-con-set.h | 15 +-
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tcg/loongarch64/tcg-target-con-str.h | 1 -
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tcg/loongarch64/tcg-target-has.h | 2 -
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tcg/loongarch64/tcg-target.h | 2 +
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tcg/mips/tcg-target-con-set.h | 26 +--
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tcg/mips/tcg-target-con-str.h | 1 -
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tcg/mips/tcg-target.h | 2 +
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tcg/riscv/tcg-target-con-set.h | 10 +-
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tcg/riscv/tcg-target-con-str.h | 1 -
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tcg/riscv/tcg-target-has.h | 2 -
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tcg/riscv/tcg-target.h | 2 +
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tcg/sparc64/tcg-target-con-set.h | 12 +-
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tcg/sparc64/tcg-target-con-str.h | 1 -
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tcg/sparc64/tcg-target.h | 3 +-
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tcg/tci/tcg-target.h | 1 -
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accel/tcg/cputlb.c | 32 +---
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accel/tcg/tcg-all.c | 9 +-
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linux-user/elfload.c | 4 +-
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plugins/api.c | 2 +-
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target/arm/ptw.c | 34 ----
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target/loongarch/tcg/translate.c | 2 +-
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target/riscv/cpu_helper.c | 13 +-
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target/sparc/gdbstub.c | 18 +-
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target/sparc/translate.c | 19 +++
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tcg/optimize.c | 21 +--
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tcg/tcg-op-ldst.c | 103 +++--------
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tcg/tcg.c | 97 +++++------
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tcg/tci.c | 119 +++----------
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docs/devel/multi-thread-tcg.rst | 1 -
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docs/devel/tcg-ops.rst | 4 +-
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target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
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target/sparc/insns.decode | 19 ++-
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tcg/aarch64/tcg-target.c.inc | 86 ++++------
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tcg/arm/tcg-target.c.inc | 114 ++++---------
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tcg/i386/tcg-target.c.inc | 190 +++++----------------
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tcg/loongarch64/tcg-target.c.inc | 72 +++-----
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tcg/mips/tcg-target.c.inc | 169 ++++++------------
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tcg/ppc/tcg-target.c.inc | 164 +++++-------------
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tcg/riscv/tcg-target.c.inc | 56 +++---
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tcg/s390x/tcg-target.c.inc | 40 ++---
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tcg/sparc64/tcg-target.c.inc | 45 ++---
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tcg/tci/tcg-target.c.inc | 60 ++-----
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61 files changed, 548 insertions(+), 1160 deletions(-)
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delete mode 100644 include/tcg/oversized-guest.h
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/1] accel/tcg/cputlb: avoid recursive BQL (fixes #1706296)
Deleted patch
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From: Alex Bennée <alex.bennee@linaro.org>
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The mmio path (see exec.c:prepare_mmio_access) already protects itself
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against recursive locking and it makes sense to do the same for
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io_readx/writex. Otherwise any helper running in the BQL context will
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assert when it attempts to write to device memory as in the case of
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the bug report.
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
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CC: Richard Jones <rjones@redhat.com>
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CC: Paolo Bonzini <bonzini@gnu.org>
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CC: qemu-stable@nongnu.org
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Message-Id: <20170921110625.9500-1-alex.bennee@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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accel/tcg/cputlb.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
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index XXXXXXX..XXXXXXX 100644
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--- a/accel/tcg/cputlb.c
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+++ b/accel/tcg/cputlb.c
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@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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cpu->mem_io_vaddr = addr;
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- if (mr->global_locking) {
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+ if (mr->global_locking && !qemu_mutex_iothread_locked()) {
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qemu_mutex_lock_iothread();
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locked = true;
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}
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@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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cpu->mem_io_vaddr = addr;
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cpu->mem_io_pc = retaddr;
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- if (mr->global_locking) {
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+ if (mr->global_locking && !qemu_mutex_iothread_locked()) {
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qemu_mutex_lock_iothread();
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locked = true;
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}
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--
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2.13.5
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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