[Qemu-devel] [PULL 0/1] tcg patch queue
[PULL v2 00/74] tcg patch queue
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Just one patch, but should make stable 2.10.1 this week.
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v2: Drop a few patches, which showed regressions in CI
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for jobs that are not run for forks. :-/
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r~
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r~
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The following changes since commit 460b6c8e581aa06b86f59eebd9e52edfe7adf417:
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The following changes since commit f9d58e0ca53b3f470b84725a7b5e47fcf446a2ea:
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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2017-09-23 12:55:40 +0100)
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Merge tag 'pull-9p-20230516' of https://github.com/cschoenebeck/qemu into staging (2023-05-16 10:21:44 -0700)
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are available in the git repository at:
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are available in the Git repository at:
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git://github.com/rth7680/qemu.git tags/pull-tcg-20170925
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https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230516-2
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for you to fetch changes up to 8b81253332b5a3f3c67b6462f39caef47a00dd29:
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for you to fetch changes up to 44fe8f47fce3bdc8dcf49e3f001519a375ecc88a:
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accel/tcg/cputlb: avoid recursive BQL (fixes #1706296) (2017-09-25 11:23:30 -0700)
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tcg: Split out exec/user/guest-base.h (2023-05-16 16:31:05 -0700)
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----------------------------------------------------------------
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----------------------------------------------------------------
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BQL bug fix
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tcg/i386: Fix tcg_out_addi_ptr for win64
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tcg: Implement atomicity for TCGv_i128
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tcg: First quarter of cleanups for building tcg once
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----------------------------------------------------------------
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----------------------------------------------------------------
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Alex Bennée (1):
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Richard Henderson (74):
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accel/tcg/cputlb: avoid recursive BQL (fixes #1706296)
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tcg/i386: Set P_REXW in tcg_out_addi_ptr
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include/exec/memop: Add MO_ATOM_*
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accel/tcg: Honor atomicity of loads
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accel/tcg: Honor atomicity of stores
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tcg: Unify helper_{be,le}_{ld,st}*
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accel/tcg: Implement helper_{ld,st}*_mmu for user-only
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tcg/tci: Use helper_{ld,st}*_mmu for user-only
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tcg: Add 128-bit guest memory primitives
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meson: Detect atomic128 support with optimization
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tcg/i386: Add have_atomic16
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tcg/aarch64: Detect have_lse, have_lse2 for linux
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tcg/aarch64: Detect have_lse, have_lse2 for darwin
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tcg/i386: Use full load/store helpers in user-only mode
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tcg/aarch64: Use full load/store helpers in user-only mode
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tcg/ppc: Use full load/store helpers in user-only mode
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tcg/loongarch64: Use full load/store helpers in user-only mode
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tcg/riscv: Use full load/store helpers in user-only mode
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tcg/arm: Adjust constraints on qemu_ld/st
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tcg/arm: Use full load/store helpers in user-only mode
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tcg/mips: Use full load/store helpers in user-only mode
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tcg/s390x: Use full load/store helpers in user-only mode
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tcg/sparc64: Allocate %g2 as a third temporary
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tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13
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target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32
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tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32
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tcg/sparc64: Split out tcg_out_movi_s32
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tcg/sparc64: Use standard slow path for softmmu
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accel/tcg: Remove helper_unaligned_{ld,st}
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tcg/loongarch64: Check the host supports unaligned accesses
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tcg/loongarch64: Support softmmu unaligned accesses
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tcg/riscv: Support softmmu unaligned accesses
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tcg: Introduce tcg_target_has_memory_bswap
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tcg: Add INDEX_op_qemu_{ld,st}_i128
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tcg: Introduce tcg_out_movext3
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tcg: Merge tcg_out_helper_load_regs into caller
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tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_helper_{args,ret}
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tcg: Introduce atom_and_align_for_opc
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tcg/i386: Use atom_and_align_for_opc
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tcg/aarch64: Use atom_and_align_for_opc
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tcg/arm: Use atom_and_align_for_opc
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tcg/loongarch64: Use atom_and_align_for_opc
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tcg/mips: Use atom_and_align_for_opc
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tcg/ppc: Use atom_and_align_for_opc
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tcg/riscv: Use atom_and_align_for_opc
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tcg/s390x: Use atom_and_align_for_opc
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tcg/sparc64: Use atom_and_align_for_opc
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tcg: Split out memory ops to tcg-op-ldst.c
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tcg: Widen gen_insn_data to uint64_t
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accel/tcg: Widen tcg-ldst.h addresses to uint64_t
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tcg: Widen helper_{ld,st}_i128 addresses to uint64_t
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tcg: Widen helper_atomic_* addresses to uint64_t
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tcg: Widen tcg_gen_code pc_start argument to uint64_t
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accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback
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accel/tcg: Merge do_gen_mem_cb into caller
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tcg: Reduce copies for plugin_gen_mem_callbacks
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accel/tcg: Widen plugin_gen_empty_mem_callback to i64
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tcg: Add addr_type to TCGContext
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tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
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tcg: Remove TCGv from tcg_gen_atomic_*
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tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
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tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
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tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
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tcg/i386: Conditionalize tcg_out_extu_i32_i64
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tcg/i386: Adjust type of tlb_mask
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tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
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tcg/arm: Remove TARGET_LONG_BITS
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tcg/aarch64: Remove USE_GUEST_BASE
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tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
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tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
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tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
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tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
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tcg: Add page_bits and page_mask to TCGContext
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tcg: Add tlb_dyn_max_bits to TCGContext
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tcg: Split out exec/user/guest-base.h
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accel/tcg/cputlb.c | 4 ++--
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docs/devel/loads-stores.rst | 36 +-
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1 file changed, 2 insertions(+), 2 deletions(-)
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docs/devel/tcg-ops.rst | 11 +-
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meson.build | 52 +-
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accel/tcg/tcg-runtime.h | 49 +-
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include/exec/cpu-all.h | 5 +-
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include/exec/memop.h | 37 ++
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include/exec/plugin-gen.h | 4 +-
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include/exec/user/guest-base.h | 12 +
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include/qemu/cpuid.h | 18 +
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include/tcg/tcg-ldst.h | 72 +--
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include/tcg/tcg-op.h | 273 ++++++---
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include/tcg/tcg-opc.h | 41 +-
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include/tcg/tcg.h | 39 +-
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tcg/aarch64/tcg-target.h | 6 +-
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tcg/arm/tcg-target-con-set.h | 16 +-
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tcg/arm/tcg-target-con-str.h | 5 +-
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tcg/arm/tcg-target.h | 3 +-
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tcg/i386/tcg-target.h | 12 +-
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tcg/loongarch64/tcg-target.h | 3 +-
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tcg/mips/tcg-target.h | 4 +-
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tcg/ppc/tcg-target.h | 3 +-
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tcg/riscv/tcg-target.h | 4 +-
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tcg/s390x/tcg-target.h | 4 +-
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tcg/sparc64/tcg-target-con-set.h | 2 -
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tcg/sparc64/tcg-target-con-str.h | 1 -
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tcg/sparc64/tcg-target.h | 4 +-
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tcg/tcg-internal.h | 2 +
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tcg/tci/tcg-target.h | 4 +-
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accel/tcg/cputlb.c | 839 ++++++++++++++++---------
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accel/tcg/plugin-gen.c | 68 +-
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accel/tcg/translate-all.c | 35 +-
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accel/tcg/user-exec.c | 488 ++++++++++-----
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tcg/optimize.c | 19 +-
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tcg/tcg-op-ldst.c | 1234 +++++++++++++++++++++++++++++++++++++
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tcg/tcg-op.c | 864 --------------------------
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tcg/tcg.c | 631 +++++++++++++++----
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tcg/tci.c | 243 +++-----
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accel/tcg/atomic_common.c.inc | 14 +-
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accel/tcg/ldst_atomicity.c.inc | 1262 ++++++++++++++++++++++++++++++++++++++
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tcg/aarch64/tcg-target.c.inc | 207 +++----
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tcg/arm/tcg-target.c.inc | 246 +++-----
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tcg/i386/tcg-target.c.inc | 240 ++++----
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tcg/loongarch64/tcg-target.c.inc | 123 ++--
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tcg/mips/tcg-target.c.inc | 216 +++----
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tcg/ppc/tcg-target.c.inc | 189 +++---
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tcg/riscv/tcg-target.c.inc | 161 ++---
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tcg/s390x/tcg-target.c.inc | 104 +---
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tcg/sparc64/tcg-target.c.inc | 731 ++++++++--------------
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tcg/tci/tcg-target.c.inc | 58 +-
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tcg/meson.build | 1 +
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50 files changed, 5345 insertions(+), 3350 deletions(-)
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create mode 100644 include/exec/user/guest-base.h
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create mode 100644 tcg/tcg-op-ldst.c
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create mode 100644 accel/tcg/ldst_atomicity.c.inc
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/1] accel/tcg/cputlb: avoid recursive BQL (fixes #1706296)
Deleted patch
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From: Alex Bennée <alex.bennee@linaro.org>
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The mmio path (see exec.c:prepare_mmio_access) already protects itself
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against recursive locking and it makes sense to do the same for
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io_readx/writex. Otherwise any helper running in the BQL context will
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assert when it attempts to write to device memory as in the case of
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the bug report.
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
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CC: Richard Jones <rjones@redhat.com>
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CC: Paolo Bonzini <bonzini@gnu.org>
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CC: qemu-stable@nongnu.org
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Message-Id: <20170921110625.9500-1-alex.bennee@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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---
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accel/tcg/cputlb.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
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index XXXXXXX..XXXXXXX 100644
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--- a/accel/tcg/cputlb.c
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+++ b/accel/tcg/cputlb.c
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@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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cpu->mem_io_vaddr = addr;
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- if (mr->global_locking) {
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+ if (mr->global_locking && !qemu_mutex_iothread_locked()) {
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qemu_mutex_lock_iothread();
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locked = true;
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}
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@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
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cpu->mem_io_vaddr = addr;
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cpu->mem_io_pc = retaddr;
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- if (mr->global_locking) {
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+ if (mr->global_locking && !qemu_mutex_iothread_locked()) {
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qemu_mutex_lock_iothread();
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locked = true;
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}
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--
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2.13.5
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diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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