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[Qemu-devel] [PATCH v4 6/6] target/sparc: optimize various functions using extract op

Philippe Mathieu-Daudé posted 6 patches 8 years, 9 months ago
[Qemu-devel] [PATCH v4 6/6] target/sparc: optimize various functions using extract op
Posted by Philippe Mathieu-Daudé 8 years, 9 months ago 
Patch created mechanically using Coccinelle script via:

    $ spatch --macro-file scripts/cocci-macro-file.h --in-place \
        --sp-file scripts/coccinelle/tcg_gen_extract.cocci --dir target

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/sparc/translate.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index aa6734d54e..67a83b77cc 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -380,29 +380,25 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num,
 static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
 {
     tcg_gen_extu_i32_tl(reg, src);
-    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
-    tcg_gen_andi_tl(reg, reg, 0x1);
+    tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
 }
 
 static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
 {
     tcg_gen_extu_i32_tl(reg, src);
-    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
-    tcg_gen_andi_tl(reg, reg, 0x1);
+    tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
 }
 
 static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
 {
     tcg_gen_extu_i32_tl(reg, src);
-    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
-    tcg_gen_andi_tl(reg, reg, 0x1);
+    tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
 }
 
 static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
 {
     tcg_gen_extu_i32_tl(reg, src);
-    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
-    tcg_gen_andi_tl(reg, reg, 0x1);
+    tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
 }
 
 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -638,8 +634,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
     // env->y = (b2 << 31) | (env->y >> 1);
     tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
     tcg_gen_shli_tl(r_temp, r_temp, 31);
-    tcg_gen_shri_tl(t0, cpu_y, 1);
-    tcg_gen_andi_tl(t0, t0, 0x7fffffff);
+    tcg_gen_extract_tl(t0, cpu_y, 1, 31);
     tcg_gen_or_tl(t0, t0, r_temp);
     tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
 
-- 
2.11.0
Re: [Qemu-devel] [PATCH v4 6/6] target/sparc: optimize various functions using extract op
Posted by Richard Henderson 8 years, 9 months ago 
On 05/12/2017 04:38 PM, Philippe Mathieu-Daudé wrote:
> Patch created mechanically using Coccinelle script via:
> 
>      $ spatch --macro-file scripts/cocci-macro-file.h --in-place \
>          --sp-file scripts/coccinelle/tcg_gen_extract.cocci --dir target
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/sparc/translate.c | 15 +++++----------
>   1 file changed, 5 insertions(+), 10 deletions(-)
> 
> diff --git a/target/sparc/translate.c b/target/sparc/translate.c
> index aa6734d54e..67a83b77cc 100644
> --- a/target/sparc/translate.c
> +++ b/target/sparc/translate.c
> @@ -380,29 +380,25 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num,
>   static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
>   {
>       tcg_gen_extu_i32_tl(reg, src);
> -    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
> -    tcg_gen_andi_tl(reg, reg, 0x1);
> +    tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
>   }
>   
>   static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
>   {
>       tcg_gen_extu_i32_tl(reg, src);
> -    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
> -    tcg_gen_andi_tl(reg, reg, 0x1);
> +    tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
>   }
>   
>   static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
>   {
>       tcg_gen_extu_i32_tl(reg, src);
> -    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
> -    tcg_gen_andi_tl(reg, reg, 0x1);
> +    tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
>   }
>   
>   static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
>   {
>       tcg_gen_extu_i32_tl(reg, src);
> -    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
> -    tcg_gen_andi_tl(reg, reg, 0x1);
> +    tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
>   }
>   

These ones get a

Reviewed-by: Richard Henderson <rth@twiddle.net>

>   static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
> @@ -638,8 +634,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
>       // env->y = (b2 << 31) | (env->y >> 1);
>       tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
>       tcg_gen_shli_tl(r_temp, r_temp, 31);
> -    tcg_gen_shri_tl(t0, cpu_y, 1);
> -    tcg_gen_andi_tl(t0, t0, 0x7fffffff);
> +    tcg_gen_extract_tl(t0, cpu_y, 1, 31);
>       tcg_gen_or_tl(t0, t0, r_temp);
>       tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);

But this should use

   tcg_gen_extract_tl(cpu_y, cpu_y, 1, 31);
   tcg_gen_deposit_tl(cpu_y, cpu_y, cpu_cc_src, 31, 1);


r~
Re: [Qemu-devel] [PATCH v4 6/6] target/sparc: optimize various functions using extract op
Posted by Philippe Mathieu-Daudé 8 years, 6 months ago 
On 05/12/2017 09:08 PM, Richard Henderson wrote:
> On 05/12/2017 04:38 PM, Philippe Mathieu-Daudé wrote:
[...]
>>   static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
>> @@ -638,8 +634,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv 
>> src1, TCGv src2)
>>       // env->y = (b2 << 31) | (env->y >> 1);
>>       tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
>>       tcg_gen_shli_tl(r_temp, r_temp, 31);
>> -    tcg_gen_shri_tl(t0, cpu_y, 1);
>> -    tcg_gen_andi_tl(t0, t0, 0x7fffffff);
>> +    tcg_gen_extract_tl(t0, cpu_y, 1, 31);
>>       tcg_gen_or_tl(t0, t0, r_temp);
>>       tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);

So this 0xffffffff mask is incorrect and should be 0x7fffffff?

> 
> But this should use
> 
>    tcg_gen_extract_tl(cpu_y, cpu_y, 1, 31);
>    tcg_gen_deposit_tl(cpu_y, cpu_y, cpu_cc_src, 31, 1);
> 
> 
> r~
Re: [Qemu-devel] [PATCH v4 6/6] target/sparc: optimize various functions using extract op
Posted by Richard Henderson 8 years, 6 months ago 
On 07/17/2017 05:18 PM, Philippe Mathieu-Daudé wrote:
> On 05/12/2017 09:08 PM, Richard Henderson wrote:
>> On 05/12/2017 04:38 PM, Philippe Mathieu-Daudé wrote:
> [...]
>>>   static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
>>> @@ -638,8 +634,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, 
>>> TCGv src2)
>>>       // env->y = (b2 << 31) | (env->y >> 1);
>>>       tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
>>>       tcg_gen_shli_tl(r_temp, r_temp, 31);
>>> -    tcg_gen_shri_tl(t0, cpu_y, 1);
>>> -    tcg_gen_andi_tl(t0, t0, 0x7fffffff);
>>> +    tcg_gen_extract_tl(t0, cpu_y, 1, 31);
>>>       tcg_gen_or_tl(t0, t0, r_temp);
>>>       tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
> 
> So this 0xffffffff mask is incorrect and should be 0x7fffffff?

No, this has nothing to do with the second andi.


r~

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