Alpha has a weak memory ordering and issues all of the required barriers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 configure          | 1 +
 target/alpha/cpu.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/configure b/configure
index df58e91..6c21975 100755
--- a/configure
+++ b/configure
@@ -5894,6 +5894,7 @@ case "$target_name" in
     TARGET_BASE_ARCH=i386
   ;;
   alpha)
+    mttcg="yes"
   ;;
   arm|armeb)
     TARGET_ARCH=arm
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index b08d160..691ac00 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -28,6 +28,9 @@
 
 #define CPUArchState struct CPUAlphaState
 
+/* Alpha processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO      (0)
+
 #include "exec/cpu-defs.h"
 
 #include "fpu/softfloat.h"
-- 
2.9.3