[Qemu-devel] [PATCH v3 0/4] sd: sdhci: correct transfer mode register usage

P J P posted 4 patches 164 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20170211150701.23391-1-ppandit@redhat.com
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hw/sd/sdhci.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)

[Qemu-devel] [PATCH v3 0/4] sd: sdhci: correct transfer mode register usage

Posted by P J P 164 weeks ago
From: Prasad J Pandit <pjp@fedoraproject.org>

Hello,

In SDHCI protocol, the 'Block Count Enable' bit of the Transfer Mode
register is used to control 's->blkcnt' value. This bit is not relevant
in single block transfers. Also, Transfer Mode register value could be
set such that 's->blkcnt' would not see an update during multi block
transfers. Thus leading to an infinite loop.

This patch set attempts to correct 'Block Count Enable' bit usage.

This series incorporates changes suggested in patch set v2:
  -> https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg01608.html

Thank you.
--
Prasad J Pandit (4):
  sd: sdhci: check transfer mode register in multi block transfer
  sd: sdhci: mask transfer mode register value
  sd: sdhci: conditionally invoke multi block transfer
  sd: sdhci: Remove block count enable check in single block transfers

 hw/sd/sdhci.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

-- 
2.9.3