On Wed, Apr 15, 2026 at 3:22 AM ~lexbaileylowrisc
<lexbaileylowrisc@git.sr.ht> wrote:
>
> Thanks for the review comments again!
>
> this is the third revision of the patch set that [starts to] update
> the OpenTitan uart to align with earlgrey version 1.0.0. I can't really
> give a specific commit hash, but the there is a branch on the opentitan
> repo which represents this version:
> https://github.com/lowRISC/opentitan/tree/earlgrey_1.0.0
We really need something frozen to point at to say that "this is the
version we are targeting"
>
> I can't give a specifc hash because these changes do miss out two
> important parts of the UART device. The clock manager is not yet present
That's fine, as long as the UART works for hash `abcdefg` then we
should point to that
Alistair
> in upstream qemu, only in the lowRISC fork, so for now it is not
> connected here. The other issue is that the alert handler block is
> missing, and thus the alert test feature of the UART will not work. This
> can only be fixed after the alert handler is also upstreamed. that will
> come later.
>
> as before, the details of the version 1 of the UART are found here:
> https://opentitan.org/book/hw/ip/uart/index.html
> (and this URL is still added to the file header in one of these commits,
> as before)
>
> I have now split up that large commit into logical steps, which included
> splitting out that change that removes the timer. You commented on this
> in the last revision. I have put this commit last because it's not
> strictly required yet. It is a change that is included on our own fork,
> and will be needed when we add the rest of the clock handling from our
> fork. For now though, you can take or leave it as you see fit. I'm happy
> for this patch set to merge with or without it.
>
> I think I fixed all the other comments too, sorry if I missed anything.
> Thanks,
> Lex.
>
>
> -----
> Lex Bailey (they/them)
> lowRISC C.I.C. 7 Hills Road, Cambridge, CB2 1GE, UK. Registered in
> England & Wales 09272283 lex.bailey@lowrisc.org
>
> Lex Bailey (10):
> Rename ibex_uart to ot_uart
> ot_uart: move to new reset API
> ot_uart: update register defs, switch to Fifo8 for tx/rx buffers
> ot_uart: replace individual IRQ fields with array, add missing IRQs
> ot_uart: gather similar behaviours togeter in register read and write
> ot_uart: implement RX fifo and loopback
> ot_uart: handle break condition
> ot_uart: update file headers with new authorship and documentation URL
> ot_uart: add tracing
> ot_uart: switch from clock driven transmission to reg R/W driven
> transmission
>
> MAINTAINERS | 1 +
> hw/char/Kconfig | 3 +
> hw/char/ibex_uart.c | 569 --------------------------
> hw/char/meson.build | 2 +-
> hw/char/ot_uart.c | 759 +++++++++++++++++++++++++++++++++++
> hw/char/trace-events | 8 +
> hw/riscv/Kconfig | 1 +
> hw/riscv/opentitan.c | 3 +-
> include/hw/char/ibex_uart.h | 73 ----
> include/hw/char/ot_uart.h | 61 +++
> include/hw/riscv/opentitan.h | 4 +-
> 11 files changed, 838 insertions(+), 646 deletions(-)
> delete mode 100644 hw/char/ibex_uart.c
> create mode 100644 hw/char/ot_uart.c
> delete mode 100644 include/hw/char/ibex_uart.h
> create mode 100644 include/hw/char/ot_uart.h
>
> --
> 2.49.1
>