hw/arm/max78000: Fix num-irq to match hardware specification

[PATCH qemu] hw/arm/max78000: Fix num-irq to match hardware specification

Posted by ~emckean 1 month, 2 weeks ago

From: Ethan McKean <emckean@protonmail.com>

The MAX78000 user guide Section 5.2 and Table 5-1 specify 119 interrupt
entries. The previous value of 120 was based on a misreading of the
table which spans three pages, with entries 0-104 on pages 102-103 and
the remaining entries 105-118 on page 104.

Signed-off-by: Ethan McKean <emckean@protonmail.com>
---
 hw/arm/max78000_soc.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c
index 7f1856f5ba..1e2f66428d 100644
--- a/hw/arm/max78000_soc.c
+++ b/hw/arm/max78000_soc.c
@@ -88,13 +88,7 @@ static void max78000_soc_realize(DeviceState *dev_soc, Error **errp)
 
     armv7m = DEVICE(&s->armv7m);
 
-    /*
-     * The MAX78000 user guide's Interrupt Vector Table section
-     * suggests that there are 120 IRQs in the text, while only listing
-     * 104 in table 5-1. Implement the more generous of the two.
-     * This has not been tested in hardware.
-     */
-    qdev_prop_set_uint32(armv7m, "num-irq", 120);
+    qdev_prop_set_uint32(armv7m, "num-irq", 119);
     qdev_prop_set_uint8(armv7m, "num-prio-bits", 3);
     qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
     qdev_prop_set_bit(armv7m, "enable-bitband", true);
-- 
2.49.1

Re: [PATCH qemu] hw/arm/max78000: Fix num-irq to match hardware specification

Posted by Peter Maydell 3 weeks, 4 days ago

On Thu, 25 Dec 2025 at 04:14, ~emckean <emckean@git.sr.ht> wrote:
>
> From: Ethan McKean <emckean@protonmail.com>
>
> The MAX78000 user guide Section 5.2 and Table 5-1 specify 119 interrupt
> entries. The previous value of 120 was based on a misreading of the
> table which spans three pages, with entries 0-104 on pages 102-103 and
> the remaining entries 105-118 on page 104.
>
> Signed-off-by: Ethan McKean <emckean@protonmail.com>
> ---
>  hw/arm/max78000_soc.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c
> index 7f1856f5ba..1e2f66428d 100644
> --- a/hw/arm/max78000_soc.c
> +++ b/hw/arm/max78000_soc.c
> @@ -88,13 +88,7 @@ static void max78000_soc_realize(DeviceState *dev_soc, Error **errp)
>
>      armv7m = DEVICE(&s->armv7m);
>
> -    /*
> -     * The MAX78000 user guide's Interrupt Vector Table section
> -     * suggests that there are 120 IRQs in the text, while only listing
> -     * 104 in table 5-1. Implement the more generous of the two.
> -     * This has not been tested in hardware.
> -     */
> -    qdev_prop_set_uint32(armv7m, "num-irq", 120);
> +    qdev_prop_set_uint32(armv7m, "num-irq", 119);

The num-irq property of the armv7m QEMU device is the number
of *external* interrupts (see the comments in the props_nvic[]
definition in hw/intc/armv7m_nvic.c). Table 5-1 includes in
its count the 16 internal interrupts (from 0, unused, through
to 15, systick). So to get from the last listed external interrupt
number in table 5-1 (which is # 119) to the total number of external
interrupts we must subtract 15. That gets us 119 - 15 == 104,
which is what our comment says for the table 5-1 figure.

But the datasheet also says this in section 5.2:

"Including the 15 system exceptions for the Arm
Cortex-M4 with FPU, the total number of entries is 134."

That's where we get the "more generous" number from. If you
strictly believe the 134 figure and that they weren't off
by one by not accounting for the unused zero internal exception
then that would be 134 - 15 == 119, but I am very reluctant to
believe in a non-multiple-of-8 number of external interrupts
unless somebody goes and finds the real hardware and tests
by writing to the NVIC_ISERn register bank to find where the
RAZ/WI bits start. If anybody did do that it would not
massively surprise me if it turned out that the actual number
of external interrupts is 104 and the datasheet text was wrong.

Getting the number slightly high in QEMU is pretty harmless.

The original discussion about what we should set num-irq to
in the review of the patchseries is in this mail thread:
https://lore.kernel.org/qemu-devel/CAFEAcA96fap_EJiFtX6a_PFmWeP1OPZGABueAyE_=JQwFi-spA@mail.gmail.com/

thanks
-- PMM

Re: [PATCH qemu] hw/arm/max78000: Fix num-irq to match hardware specification

Posted by e 3 weeks, 1 day ago

I appreciate the detailed reply and breakdown. Apologies for the lack of due diligence on the previous discussion. I do not have the hardware with me currently but will confirm the real number of external interrupts in a few months when I do again.

- Ethan

On Tuesday, January 13th, 2026 at 1:19 AM, Peter Maydell <peter.maydell@linaro.org> wrote:

> 
> 
> On Thu, 25 Dec 2025 at 04:14, ~emckean emckean@git.sr.ht wrote:
> 
> > From: Ethan McKean emckean@protonmail.com
> > 
> > The MAX78000 user guide Section 5.2 and Table 5-1 specify 119 interrupt
> > entries. The previous value of 120 was based on a misreading of the
> > table which spans three pages, with entries 0-104 on pages 102-103 and
> > the remaining entries 105-118 on page 104.
> > 
> > Signed-off-by: Ethan McKean emckean@protonmail.com
> > ---
> > hw/arm/max78000_soc.c | 8 +-------
> > 1 file changed, 1 insertion(+), 7 deletions(-)
> > 
> > diff --git a/hw/arm/max78000_soc.c b/hw/arm/max78000_soc.c
> > index 7f1856f5ba..1e2f66428d 100644
> > --- a/hw/arm/max78000_soc.c
> > +++ b/hw/arm/max78000_soc.c
> > @@ -88,13 +88,7 @@ static void max78000_soc_realize(DeviceState *dev_soc, Error **errp)
> > 
> > armv7m = DEVICE(&s->armv7m);
> > 
> > - /*
> > - * The MAX78000 user guide's Interrupt Vector Table section
> > - * suggests that there are 120 IRQs in the text, while only listing
> > - * 104 in table 5-1. Implement the more generous of the two.
> > - * This has not been tested in hardware.
> > - */
> > - qdev_prop_set_uint32(armv7m, "num-irq", 120);
> > + qdev_prop_set_uint32(armv7m, "num-irq", 119);
> 
> 
> The num-irq property of the armv7m QEMU device is the number
> of external interrupts (see the comments in the props_nvic[]
> definition in hw/intc/armv7m_nvic.c). Table 5-1 includes in
> its count the 16 internal interrupts (from 0, unused, through
> to 15, systick). So to get from the last listed external interrupt
> number in table 5-1 (which is # 119) to the total number of external
> interrupts we must subtract 15. That gets us 119 - 15 == 104,
> which is what our comment says for the table 5-1 figure.
> 
> But the datasheet also says this in section 5.2:
> 
> "Including the 15 system exceptions for the Arm
> Cortex-M4 with FPU, the total number of entries is 134."
> 
> That's where we get the "more generous" number from. If you
> strictly believe the 134 figure and that they weren't off
> by one by not accounting for the unused zero internal exception
> then that would be 134 - 15 == 119, but I am very reluctant to
> believe in a non-multiple-of-8 number of external interrupts
> unless somebody goes and finds the real hardware and tests
> by writing to the NVIC_ISERn register bank to find where the
> RAZ/WI bits start. If anybody did do that it would not
> massively surprise me if it turned out that the actual number
> of external interrupts is 104 and the datasheet text was wrong.
> 
> Getting the number slightly high in QEMU is pretty harmless.
> 
> The original discussion about what we should set num-irq to
> in the review of the patchseries is in this mail thread:
> https://lore.kernel.org/qemu-devel/CAFEAcA96fap_EJiFtX6a_PFmWeP1OPZGABueAyE_=JQwFi-spA@mail.gmail.com/
> 
> thanks
> -- PMM