[v11] target/riscv: Add Zilsd and Zclsd extension support

[PATCH qemu v11 0/1] target/riscv: Add Zilsd and Zclsd extension support

~liuxu posted 1 patch 2 weeks, 4 days ago

Diff against v3 v4 v5 v6 v7 v8 v9 v10
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/176154834968.21563.217396575391240410-0@git.sr.ht

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c                        |   4 +
target/riscv/cpu_cfg_fields.h.inc         |   2 +
target/riscv/insn16.decode                |   8 ++
target/riscv/insn32.decode                |  12 ++-
target/riscv/insn_trans/trans_zilsd.c.inc | 105 ++++++++++++++++++++++
target/riscv/tcg/tcg-cpu.c                |  33 +++++++
target/riscv/translate.c                  |   1 +
7 files changed, 163 insertions(+), 2 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

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[PATCH qemu v11 0/1] target/riscv: Add Zilsd and Zclsd extension support

Posted by ~liuxu 2 weeks, 4 days ago

This version has added a SPDX-License-Identifier.

lxx (1):
  target/riscv: Add Zilsd and Zclsd extension support

 target/riscv/cpu.c                        |   4 +
 target/riscv/cpu_cfg_fields.h.inc         |   2 +
 target/riscv/insn16.decode                |   8 ++
 target/riscv/insn32.decode                |  12 ++-
 target/riscv/insn_trans/trans_zilsd.c.inc | 105 ++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c                |  33 +++++++
 target/riscv/translate.c                  |   1 +
 7 files changed, 163 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

-- 
2.49.1

Re: [PATCH qemu v11 0/1] target/riscv: Add Zilsd and Zclsd extension support

Posted by Alistair Francis 2 days, 13 hours ago

On Mon, Oct 27, 2025 at 4:59 PM ~liuxu <liuxu@git.sr.ht> wrote:
>
> This version has added a SPDX-License-Identifier.
>
> lxx (1):
>   target/riscv: Add Zilsd and Zclsd extension support

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c                        |   4 +
>  target/riscv/cpu_cfg_fields.h.inc         |   2 +
>  target/riscv/insn16.decode                |   8 ++
>  target/riscv/insn32.decode                |  12 ++-
>  target/riscv/insn_trans/trans_zilsd.c.inc | 105 ++++++++++++++++++++++
>  target/riscv/tcg/tcg-cpu.c                |  33 +++++++
>  target/riscv/translate.c                  |   1 +
>  7 files changed, 163 insertions(+), 2 deletions(-)
>  create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc
>
> --
> 2.49.1