[PATCH qemu v10 0/1] target/riscv: Add Zilsd and Zclsd extension support

~liuxu posted 1 patch 2 months, 3 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/175611702979.27776.8893001401121570723-0@git.sr.ht
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
There is a newer version of this series
target/riscv/cpu.c                        |   4 +
target/riscv/cpu_cfg_fields.h.inc         |   2 +
target/riscv/insn16.decode                |   8 ++
target/riscv/insn32.decode                |  12 ++-
target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
target/riscv/tcg/tcg-cpu.c                |  33 +++++++
target/riscv/translate.c                  |   1 +
7 files changed, 170 insertions(+), 2 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc
[PATCH qemu v10 0/1] target/riscv: Add Zilsd and Zclsd extension support
Posted by ~liuxu 2 months, 3 weeks ago
This version has completely fixed the conflict between Zclsd and C&F
under linux-user. The specific reason is that Zilsd will imply Zclsd, so
it also needs to be disabled for the "max" CPU. The local test was also
successful.

lxx (1):
  target/riscv: Add Zilsd and Zclsd extension support

 target/riscv/cpu.c                        |   4 +
 target/riscv/cpu_cfg_fields.h.inc         |   2 +
 target/riscv/insn16.decode                |   8 ++
 target/riscv/insn32.decode                |  12 ++-
 target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c                |  33 +++++++
 target/riscv/translate.c                  |   1 +
 7 files changed, 170 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

-- 
2.49.1