[v9] target/riscv: Add Zilsd and Zclsd extension support

[PATCH qemu v9 0/1] target/riscv: Add Zilsd and Zclsd extension support

~liuxu posted 1 patch 5 months ago

Diff against v3 v4 v5 v6 v7 v8 v10 v11
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/175014178352.19565.9471325854234944512-0@git.sr.ht

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.c                        |   4 +
target/riscv/cpu_cfg_fields.h.inc         |   2 +
target/riscv/insn16.decode                |   8 ++
target/riscv/insn32.decode                |  12 ++-
target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
target/riscv/tcg/tcg-cpu.c                |  32 +++++++
target/riscv/translate.c                  |   1 +
7 files changed, 169 insertions(+), 2 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

Expand all Fold all

[PATCH qemu v9 0/1] target/riscv: Add Zilsd and Zclsd extension support

Posted by ~liuxu 5 months ago

Thanks for Alistair's correction on the V8 version.

Now Zclsd has been disabled for the "max" CPU as C and F are already
enabled.

lxx (1):
  target/riscv: Add Zilsd and Zclsd extension support

 target/riscv/cpu.c                        |   4 +
 target/riscv/cpu_cfg_fields.h.inc         |   2 +
 target/riscv/insn16.decode                |   8 ++
 target/riscv/insn32.decode                |  12 ++-
 target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c                |  32 +++++++
 target/riscv/translate.c                  |   1 +
 7 files changed, 169 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

-- 
2.45.3

Re: [PATCH qemu v9 0/1] target/riscv: Add Zilsd and Zclsd extension support

Posted by Alistair Francis 4 months, 2 weeks ago

On Tue, Jun 17, 2025 at 4:29 PM ~liuxu <liuxu@git.sr.ht> wrote:
>
> Thanks for Alistair's correction on the V8 version.
>
> Now Zclsd has been disabled for the "max" CPU as C and F are already
> enabled.

This is still broken with userspace mode:

```
qemu-riscv64: Zclsd cannot be supported together with C and F extension
```

Alistair


>
> lxx (1):
>   target/riscv: Add Zilsd and Zclsd extension support
>
>  target/riscv/cpu.c                        |   4 +
>  target/riscv/cpu_cfg_fields.h.inc         |   2 +
>  target/riscv/insn16.decode                |   8 ++
>  target/riscv/insn32.decode                |  12 ++-
>  target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
>  target/riscv/tcg/tcg-cpu.c                |  32 +++++++
>  target/riscv/translate.c                  |   1 +
>  7 files changed, 169 insertions(+), 2 deletions(-)
>  create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc
>
> --
> 2.45.3

Re: [PATCH qemu v9 0/1] target/riscv: Add Zilsd and Zclsd extension support

Posted by liuxu 4 months ago

>On Tue, Jun 17, 2025 at 4:29 PM ~liuxu <liuxu@git.sr.ht> wrote:
>>
>> Thanks for Alistair's correction on the V8 version.
>>
>> Now Zclsd has been disabled for the "max" CPU as C and F are already
>> enabled.
>
>This is still broken with userspace mode:
>
>```
>qemu-riscv64: Zclsd cannot be supported together with C and F extension
>```
>
>Alistair

Could you please tell me the specific reproduction method? 
I have re-reviewed the code and tried the tests that come with qemu,
but I still haven't figured out why the above error occurre.

>> lxx (1):
>>   target/riscv: Add Zilsd and Zclsd extension support
>>
>>  target/riscv/cpu.c                        |   4 +
>>  target/riscv/cpu_cfg_fields.h.inc         |   2 +
>>  target/riscv/insn16.decode                |   8 ++
>>  target/riscv/insn32.decode                |  12 ++-
>>  target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
>>  target/riscv/tcg/tcg-cpu.c                |  32 +++++++
>>  target/riscv/translate.c                  |   1 +
>>  7 files changed, 169 insertions(+), 2 deletions(-)
>>  create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc
>>
>> --
>> 2.45.3

Re: [PATCH qemu v9 0/1] target/riscv: Add Zilsd and Zclsd extension support

Posted by Alistair Francis 4 months, 2 weeks ago

On Tue, Jun 17, 2025 at 4:29 PM ~liuxu <liuxu@git.sr.ht> wrote:
>
> Thanks for Alistair's correction on the V8 version.
>
> Now Zclsd has been disabled for the "max" CPU as C and F are already
> enabled.
>
> lxx (1):
>   target/riscv: Add Zilsd and Zclsd extension support

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c                        |   4 +
>  target/riscv/cpu_cfg_fields.h.inc         |   2 +
>  target/riscv/insn16.decode                |   8 ++
>  target/riscv/insn32.decode                |  12 ++-
>  target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
>  target/riscv/tcg/tcg-cpu.c                |  32 +++++++
>  target/riscv/translate.c                  |   1 +
>  7 files changed, 169 insertions(+), 2 deletions(-)
>  create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc
>
> --
> 2.45.3