[v8] target/riscv: Add Zilsd and Zclsd extension support

[PATCH qemu v8 0/1] target/riscv: Add Zilsd and Zclsd extension support

~liuxu posted 1 patch 5 months ago

Diff against v3 v4 v5 v6 v7 v9 v10 v11
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/174971620915.19456.15836954551382475540-0@git.sr.ht

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.c                        |   4 +
target/riscv/cpu_cfg_fields.h.inc         |   2 +
target/riscv/insn16.decode                |   8 ++
target/riscv/insn32.decode                |  12 ++-
target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
target/riscv/tcg/tcg-cpu.c                |  30 ++++++
target/riscv/translate.c                  |   1 +
7 files changed, 167 insertions(+), 2 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

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[PATCH qemu v8 0/1] target/riscv: Add Zilsd and Zclsd extension support

Posted by ~liuxu 5 months ago

Thanks for Alistair Francis's reply, and now this version has changed as
follows:
1. Rebase to https://github.com/alistair23/qemu/tree/riscv-to-
apply.next.
2. The Review-by information has been added.

lxx (1):
  target/riscv: Add Zilsd and Zclsd extension support

 target/riscv/cpu.c                        |   4 +
 target/riscv/cpu_cfg_fields.h.inc         |   2 +
 target/riscv/insn16.decode                |   8 ++
 target/riscv/insn32.decode                |  12 ++-
 target/riscv/insn_trans/trans_zilsd.c.inc | 112 ++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c                |  30 ++++++
 target/riscv/translate.c                  |   1 +
 7 files changed, 167 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

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2.45.3