[v2] target/riscv: Add Zilsd and Zcmlsd extension support

[PATCH qemu v2 0/1] target/riscv: Add Zilsd and Zcmlsd extension support

~liuxu posted 1 patch 3 months, 1 week ago

Diff against v1 v1
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/172075515999.22382.15550760745449625636-0@git.sr.ht

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c                         |  4 +
target/riscv/cpu_cfg.h                     |  2 +
target/riscv/insn16.decode                 |  8 ++
target/riscv/insn32.decode                 | 12 ++-
target/riscv/insn_trans/trans_zcmlsd.c.inc | 91 +++++++++++++++++++++
target/riscv/insn_trans/trans_zilsd.c.inc  | 94 ++++++++++++++++++++++
target/riscv/tcg/tcg-cpu.c                 | 13 +++
target/riscv/translate.c                   |  2 +
8 files changed, 224 insertions(+), 2 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_zcmlsd.c.inc
create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

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[PATCH qemu v2 0/1] target/riscv: Add Zilsd and Zcmlsd extension support

Posted by ~liuxu 3 months, 1 week ago

In this version of the patch:
1. Adjusted the code formatting issue
2. Optimize the processing of all instructions

lxx (1):
  target/riscv: Add Zilsd and Zcmlsd extension support

 target/riscv/cpu.c                         |  4 +
 target/riscv/cpu_cfg.h                     |  2 +
 target/riscv/insn16.decode                 |  8 ++
 target/riscv/insn32.decode                 | 12 ++-
 target/riscv/insn_trans/trans_zcmlsd.c.inc | 91 +++++++++++++++++++++
 target/riscv/insn_trans/trans_zilsd.c.inc  | 94 ++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c                 | 13 +++
 target/riscv/translate.c                   |  2 +
 8 files changed, 224 insertions(+), 2 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_zcmlsd.c.inc
 create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc

-- 
2.43.4