This patch adds a new STM32L4x5 EXTI device and is part
of a series implementing the STM32L4x5 with a few peripherals.

The patch is split up in 3 commits :
- implementing the EXTI device
- adding tests (that fail in this commit)
- connecting the EXTI device to the SoC (the tests pass in this commit)

Thank you Alistair for the review and very helpful answers !

Sincerely,
Ines Varhol

Changes from v3 to non-RFC v1:
- separating the patch in 3 commits
- justifying in the commit message why we implement a new
model instead of changing the existing stm32f4xx_exti
- changed irq_raise to irq_pulse in register SWIERx write (in
stm32l4x5_exti_write)
to be consistent with the irq_pulse in stm32l4x5_exti_set_irq (and also
both these interrupts
are edge-triggered)
- changed the license to GPL

Changes from v2 to v3:
- adding more tests writing/reading in exti registers
- adding tests checking that interrupt work by reading NVIC registers
- correcting exti_write in SWIER (so it sets an irq only when a bit goes
from '0' to '1')
- correcting exti_set_irq (so it never writes in PR when the relevant
bit in IMR is '0')

Changes from v1 to v2:
- use arrays to deduplicate code and logic
- move internal constant EXTI_NUM_GPIO_EVENT_IN_LINES from the header
to the .c file
- Improve copyright headers
- replace static const with #define
- use the DEFINE_TYPES macro
- fill the impl and valid field of the exti's MemoryRegionOps
- fix invalid test caused by a last minute change

Based-on: <170100975340.4879.5844108484092111139-0@git.sr.ht>
([PATCH qemu 0/2] hw/arm: Add minimal support for the B-L475E-IOT01A
board)

Inès Varhol (3):
  hw/arm: Implement STM32L4x5 EXTI
  hw/arm: Add STM32L4x5 EXTI QTest testcase
  hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC

 hw/arm/Kconfig                    |   1 +
 hw/arm/stm32l4x5_soc.c            |  65 +++-
 hw/misc/Kconfig                   |   3 +
 hw/misc/meson.build               |   1 +
 hw/misc/stm32l4x5_exti.c          | 299 ++++++++++++++++++
 hw/misc/trace-events              |   5 +
 include/hw/arm/stm32l4x5_soc.h    |   3 +
 include/hw/misc/stm32l4x5_exti.h  |  61 ++++
 tests/qtest/meson.build           |   5 +
 tests/qtest/stm32l4x5_exti-test.c | 485 ++++++++++++++++++++++++++++++
 10 files changed, 926 insertions(+), 2 deletions(-)
 create mode 100644 hw/misc/stm32l4x5_exti.c
 create mode 100644 include/hw/misc/stm32l4x5_exti.h
 create mode 100644 tests/qtest/stm32l4x5_exti-test.c

-- 
2.38.5

Hi Inès,

On 7/12/23 22:30, ~inesvarhol wrote:
> This patch adds a new STM32L4x5 EXTI device and is part
> of a series implementing the STM32L4x5 with a few peripherals.
> 
> The patch is split up in 3 commits :
> - implementing the EXTI device
> - adding tests (that fail in this commit)
> - connecting the EXTI device to the SoC (the tests pass in this commit)
> 
> Thank you Alistair for the review and very helpful answers !
> 
> Sincerely,
> Ines Varhol
> 
> Changes from v3 to non-RFC v1:
> - separating the patch in 3 commits
> - justifying in the commit message why we implement a new
> model instead of changing the existing stm32f4xx_exti
> - changed irq_raise to irq_pulse in register SWIERx write (in
> stm32l4x5_exti_write)
> to be consistent with the irq_pulse in stm32l4x5_exti_set_irq (and also
> both these interrupts
> are edge-triggered)
> - changed the license to GPL
> 
> Changes from v2 to v3:
> - adding more tests writing/reading in exti registers
> - adding tests checking that interrupt work by reading NVIC registers
> - correcting exti_write in SWIER (so it sets an irq only when a bit goes
> from '0' to '1')
> - correcting exti_set_irq (so it never writes in PR when the relevant
> bit in IMR is '0')
> 
> Changes from v1 to v2:
> - use arrays to deduplicate code and logic
> - move internal constant EXTI_NUM_GPIO_EVENT_IN_LINES from the header
> to the .c file
> - Improve copyright headers
> - replace static const with #define
> - use the DEFINE_TYPES macro
> - fill the impl and valid field of the exti's MemoryRegionOps
> - fix invalid test caused by a last minute change

FYI I have your series tagged for review, but I have been busy and
won't have time to look at it the next 2 weeks :/

> Based-on: <170100975340.4879.5844108484092111139-0@git.sr.ht>
> ([PATCH qemu 0/2] hw/arm: Add minimal support for the B-L475E-IOT01A
> board)
> 
> Inès Varhol (3):
>    hw/arm: Implement STM32L4x5 EXTI
>    hw/arm: Add STM32L4x5 EXTI QTest testcase
>    hw/arm: Connect STM32L4x5 EXTI to STM32L4x5 SoC