From: eopXD <eop.chen@sifive.com>
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++++
target/riscv/vector_helper.c | 30 +++++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 86374f22c0..a27433b324 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3211,6 +3211,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = \
+ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -3315,6 +3317,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ data = \
+ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
cpu_env, s->cfg_ptr->vlen / 8, \
@@ -3352,6 +3356,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_gvec_3_ptr * const fns[4] = {
gen_helper_viota_m_b, gen_helper_viota_m_h,
gen_helper_viota_m_w, gen_helper_viota_m_d,
@@ -3381,6 +3386,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, VTA, s->vta);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vid_v_b, gen_helper_vid_v_h,
gen_helper_vid_v_w, gen_helper_vid_v_d,
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a319cda969..dcb6d3538c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4719,6 +4719,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vl = env->vl; \
+ uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
+ uint32_t vta_all_1s = vext_vta_all_1s(desc); \
uint32_t i; \
int a, b; \
\
@@ -4728,6 +4730,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
env->vstart = 0; \
+ /* mask destination register are always tail- \
+ * agnostic \
+ */ \
+ /* set tail elements to 1s */ \
+ if (vta_all_1s) { \
+ for (; i < total_elems; i++) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
+ } \
}
#define DO_NAND(N, M) (!(N & M))
@@ -4795,6 +4806,8 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
+ uint32_t total_elems = env_archcpu(env)->cfg.vlen;
+ uint32_t vta_all_1s = vext_vta_all_1s(desc);
int i;
bool first_mask_bit = false;
@@ -4823,6 +4836,13 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
}
}
env->vstart = 0;
+ /* mask destination register are always tail-agnostic */
+ /* set tail elements to 1s */
+ if (vta_all_1s) {
+ for (; i < total_elems; i++) {
+ vext_set_elem_mask(vd, i, 1);
+ }
+ }
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
@@ -4850,6 +4870,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
+ uint32_t vta = vext_vta(desc); \
uint32_t sum = 0; \
int i; \
\
@@ -4863,6 +4886,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
} \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1)
@@ -4876,6 +4901,9 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
+ uint32_t esz = sizeof(ETYPE); \
+ uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
+ uint32_t vta = vext_vta(desc); \
int i; \
\
for (i = env->vstart; i < vl; i++) { \
@@ -4885,6 +4913,8 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
*((ETYPE *)vd + H(i)) = i; \
} \
env->vstart = 0; \
+ /* set tail elements to 1s */ \
+ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
GEN_VEXT_VID_V(vid_v_b, uint8_t, H1)
--
2.34.2On Tue, May 3, 2022 at 9:44 AM ~eopxd <eopxd@git.sr.ht> wrote:
>
> From: eopXD <eop.chen@sifive.com>
>
> The tail elements in the destination mask register are updated under
> a tail-agnostic policy.
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 6 +++++
> target/riscv/vector_helper.c | 30 +++++++++++++++++++++++++
> 2 files changed, 36 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 86374f22c0..a27433b324 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3211,6 +3211,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
> tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> + data = \
> + FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), cpu_env, \
> @@ -3315,6 +3317,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> \
> data = FIELD_DP32(data, VDATA, VM, a->vm); \
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> + data = \
> + FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
> tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
> vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
> cpu_env, s->cfg_ptr->vlen / 8, \
> @@ -3352,6 +3356,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, VTA, s->vta);
> static gen_helper_gvec_3_ptr * const fns[4] = {
> gen_helper_viota_m_b, gen_helper_viota_m_h,
> gen_helper_viota_m_w, gen_helper_viota_m_d,
> @@ -3381,6 +3386,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
>
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, VTA, s->vta);
> static gen_helper_gvec_2_ptr * const fns[4] = {
> gen_helper_vid_v_b, gen_helper_vid_v_h,
> gen_helper_vid_v_w, gen_helper_vid_v_d,
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index a319cda969..dcb6d3538c 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4719,6 +4719,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
> uint32_t desc) \
> { \
> uint32_t vl = env->vl; \
> + uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> + uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> uint32_t i; \
> int a, b; \
> \
> @@ -4728,6 +4730,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
> vext_set_elem_mask(vd, i, OP(b, a)); \
> } \
> env->vstart = 0; \
> + /* mask destination register are always tail- \
> + * agnostic \
> + */ \
> + /* set tail elements to 1s */ \
> + if (vta_all_1s) { \
> + for (; i < total_elems; i++) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> + } \
> }
>
> #define DO_NAND(N, M) (!(N & M))
> @@ -4795,6 +4806,8 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
> {
> uint32_t vm = vext_vm(desc);
> uint32_t vl = env->vl;
> + uint32_t total_elems = env_archcpu(env)->cfg.vlen;
> + uint32_t vta_all_1s = vext_vta_all_1s(desc);
> int i;
> bool first_mask_bit = false;
>
> @@ -4823,6 +4836,13 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
> }
> }
> env->vstart = 0;
> + /* mask destination register are always tail-agnostic */
> + /* set tail elements to 1s */
> + if (vta_all_1s) {
> + for (; i < total_elems; i++) {
> + vext_set_elem_mask(vd, i, 1);
> + }
> + }
> }
>
> void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
> @@ -4850,6 +4870,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
> { \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> + uint32_t vta = vext_vta(desc); \
> uint32_t sum = 0; \
> int i; \
> \
> @@ -4863,6 +4886,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
> } \
> } \
> env->vstart = 0; \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
> }
>
> GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1)
> @@ -4876,6 +4901,9 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
> { \
> uint32_t vm = vext_vm(desc); \
> uint32_t vl = env->vl; \
> + uint32_t esz = sizeof(ETYPE); \
> + uint32_t total_elems = vext_get_total_elems(env, desc, esz); \
> + uint32_t vta = vext_vta(desc); \
> int i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> @@ -4885,6 +4913,8 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
> *((ETYPE *)vd + H(i)) = i; \
> } \
> env->vstart = 0; \
> + /* set tail elements to 1s */ \
> + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
> }
>
> GEN_VEXT_VID_V(vid_v_b, uint8_t, H1)
> --
> 2.34.2
>
>
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