target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 + target/riscv/cpu_helper.c | 2 + target/riscv/insn_trans/trans_rvv.c.inc | 164 +++ target/riscv/internals.h | 5 +- target/riscv/translate.c | 2 + target/riscv/vector_helper.c | 1562 ++++++++++++++--------- 7 files changed, 1121 insertions(+), 617 deletions(-)
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to enable the behavior, it is default as
disabled.
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s makes things simple and allow QEMU to express this.
We may explore other possibility of agnostic behavior by adding
other options in the future. Please understand that this patch-set
is limited.
v2 updates:
- Addressed comments from Weiwei Li
- Added commit tail agnostic on load / store instructions (which
I forgot to include into the patch-set)
v3 updates:
- Missed the very 1st commit, adding it back
v4 updates:
- Renamed vlmax to total_elems
- Deal with tail element when vl_eq_vlmax == true
v5 updates:
- Let `vext_get_total_elems` take `desc` and `esz`
- Utilize `simd_maxsz(desc)` to get `vlenb`
- Fix alignments to code
v6 updates:
- Fix `vext_get_total_elems`
v7 updates:
- Reuse `max_elems` for vector load / store helper functions. The
translation sets desc's `lmul` to `min(1, lmul)`, making
`vext_max_elems`
equivalent to `vext_get_total_elems`.
eopXD (14):
target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
target/riscv: rvv: Rename ambiguous esz
target/riscv: rvv: Early exit when vstart >= vl
target/riscv: rvv: Add tail agnostic for vv instructions
target/riscv: rvv: Add tail agnostic for vector load / store
instructions
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
target/riscv: rvv: Add tail agnostic for vector integer shift
instructions
target/riscv: rvv: Add tail agnostic for vector integer comparison
instructions
target/riscv: rvv: Add tail agnostic for vector integer merge and move
instructions
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic
instructions
target/riscv: rvv: Add tail agnostic for vector floating-point
instructions
target/riscv: rvv: Add tail agnostic for vector reduction instructions
target/riscv: rvv: Add tail agnostic for vector mask instructions
target/riscv: rvv: Add tail agnostic for vector permutation
instructions
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 2 +
target/riscv/cpu_helper.c | 2 +
target/riscv/insn_trans/trans_rvv.c.inc | 164 +++
target/riscv/internals.h | 5 +-
target/riscv/translate.c | 2 +
target/riscv/vector_helper.c | 1562 ++++++++++++++---------
7 files changed, 1121 insertions(+), 617 deletions(-)
--
2.34.1
在 2022/3/30 下午6:24, ~eopxd 写道: > According to v-spec, tail agnostic behavior can be either kept as > undisturbed or set elements' bits to all 1s. To distinguish the > difference of tail policies, QEMU should be able to simulate the tail > agnostic behavior as "set tail elements' bits to all 1s". An option > 'rvv_ta_all_1s' is added to enable the behavior, it is default as > disabled. > > There are multiple possibility for agnostic elements according to > v-spec. The main intent of this patch-set tries to add option that > can distinguish between tail policies. Setting agnostic elements to > all 1s makes things simple and allow QEMU to express this. > > We may explore other possibility of agnostic behavior by adding > other options in the future. Please understand that this patch-set > is limited. > > v2 updates: > - Addressed comments from Weiwei Li > - Added commit tail agnostic on load / store instructions (which > I forgot to include into the patch-set) > > v3 updates: > - Missed the very 1st commit, adding it back > > v4 updates: > - Renamed vlmax to total_elems > - Deal with tail element when vl_eq_vlmax == true > > v5 updates: > - Let `vext_get_total_elems` take `desc` and `esz` > - Utilize `simd_maxsz(desc)` to get `vlenb` > - Fix alignments to code > > v6 updates: > - Fix `vext_get_total_elems` > > v7 updates: > - Reuse `max_elems` for vector load / store helper functions. The > translation sets desc's `lmul` to `min(1, lmul)`, making > `vext_max_elems` > equivalent to `vext_get_total_elems`. > > eopXD (14): > target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed > target/riscv: rvv: Rename ambiguous esz > target/riscv: rvv: Early exit when vstart >= vl > target/riscv: rvv: Add tail agnostic for vv instructions > target/riscv: rvv: Add tail agnostic for vector load / store > instructions > target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions > target/riscv: rvv: Add tail agnostic for vector integer shift > instructions > target/riscv: rvv: Add tail agnostic for vector integer comparison > instructions > target/riscv: rvv: Add tail agnostic for vector integer merge and move > instructions > target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic > instructions > target/riscv: rvv: Add tail agnostic for vector floating-point > instructions > target/riscv: rvv: Add tail agnostic for vector reduction instructions > target/riscv: rvv: Add tail agnostic for vector mask instructions > target/riscv: rvv: Add tail agnostic for vector permutation > instructions > > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 2 + > target/riscv/cpu_helper.c | 2 + > target/riscv/insn_trans/trans_rvv.c.inc | 164 +++ > target/riscv/internals.h | 5 +- > target/riscv/translate.c | 2 + > target/riscv/vector_helper.c | 1562 ++++++++++++++--------- > 7 files changed, 1121 insertions(+), 617 deletions(-) > The patchset looks good to me. Regards, Weiwei Li
On Wed, Mar 30, 2022 at 10:52 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > > 在 2022/3/30 下午6:24, ~eopxd 写道: > > According to v-spec, tail agnostic behavior can be either kept as > > undisturbed or set elements' bits to all 1s. To distinguish the > > difference of tail policies, QEMU should be able to simulate the tail > > agnostic behavior as "set tail elements' bits to all 1s". An option > > 'rvv_ta_all_1s' is added to enable the behavior, it is default as > > disabled. > > > > There are multiple possibility for agnostic elements according to > > v-spec. The main intent of this patch-set tries to add option that > > can distinguish between tail policies. Setting agnostic elements to > > all 1s makes things simple and allow QEMU to express this. > > > > We may explore other possibility of agnostic behavior by adding > > other options in the future. Please understand that this patch-set > > is limited. > > > > v2 updates: > > - Addressed comments from Weiwei Li > > - Added commit tail agnostic on load / store instructions (which > > I forgot to include into the patch-set) > > > > v3 updates: > > - Missed the very 1st commit, adding it back > > > > v4 updates: > > - Renamed vlmax to total_elems > > - Deal with tail element when vl_eq_vlmax == true > > > > v5 updates: > > - Let `vext_get_total_elems` take `desc` and `esz` > > - Utilize `simd_maxsz(desc)` to get `vlenb` > > - Fix alignments to code > > > > v6 updates: > > - Fix `vext_get_total_elems` > > > > v7 updates: > > - Reuse `max_elems` for vector load / store helper functions. The > > translation sets desc's `lmul` to `min(1, lmul)`, making > > `vext_max_elems` > > equivalent to `vext_get_total_elems`. > > > > eopXD (14): > > target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed > > target/riscv: rvv: Rename ambiguous esz > > target/riscv: rvv: Early exit when vstart >= vl > > target/riscv: rvv: Add tail agnostic for vv instructions > > target/riscv: rvv: Add tail agnostic for vector load / store > > instructions > > target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions > > target/riscv: rvv: Add tail agnostic for vector integer shift > > instructions > > target/riscv: rvv: Add tail agnostic for vector integer comparison > > instructions > > target/riscv: rvv: Add tail agnostic for vector integer merge and move > > instructions > > target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic > > instructions > > target/riscv: rvv: Add tail agnostic for vector floating-point > > instructions > > target/riscv: rvv: Add tail agnostic for vector reduction instructions > > target/riscv: rvv: Add tail agnostic for vector mask instructions > > target/riscv: rvv: Add tail agnostic for vector permutation > > instructions > > > > target/riscv/cpu.c | 1 + > > target/riscv/cpu.h | 2 + > > target/riscv/cpu_helper.c | 2 + > > target/riscv/insn_trans/trans_rvv.c.inc | 164 +++ > > target/riscv/internals.h | 5 +- > > target/riscv/translate.c | 2 + > > target/riscv/vector_helper.c | 1562 ++++++++++++++--------- > > 7 files changed, 1121 insertions(+), 617 deletions(-) > > > The patchset looks good to me. Do you want to add a reviewed-by or acked-by tag? Alistair > > Regards, > > Weiwei Li > >
在 2022/3/31 上午8:11, Alistair Francis 写道: > On Wed, Mar 30, 2022 at 10:52 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> >> 在 2022/3/30 下午6:24, ~eopxd 写道: >>> According to v-spec, tail agnostic behavior can be either kept as >>> undisturbed or set elements' bits to all 1s. To distinguish the >>> difference of tail policies, QEMU should be able to simulate the tail >>> agnostic behavior as "set tail elements' bits to all 1s". An option >>> 'rvv_ta_all_1s' is added to enable the behavior, it is default as >>> disabled. >>> >>> There are multiple possibility for agnostic elements according to >>> v-spec. The main intent of this patch-set tries to add option that >>> can distinguish between tail policies. Setting agnostic elements to >>> all 1s makes things simple and allow QEMU to express this. >>> >>> We may explore other possibility of agnostic behavior by adding >>> other options in the future. Please understand that this patch-set >>> is limited. >>> >>> v2 updates: >>> - Addressed comments from Weiwei Li >>> - Added commit tail agnostic on load / store instructions (which >>> I forgot to include into the patch-set) >>> >>> v3 updates: >>> - Missed the very 1st commit, adding it back >>> >>> v4 updates: >>> - Renamed vlmax to total_elems >>> - Deal with tail element when vl_eq_vlmax == true >>> >>> v5 updates: >>> - Let `vext_get_total_elems` take `desc` and `esz` >>> - Utilize `simd_maxsz(desc)` to get `vlenb` >>> - Fix alignments to code >>> >>> v6 updates: >>> - Fix `vext_get_total_elems` >>> >>> v7 updates: >>> - Reuse `max_elems` for vector load / store helper functions. The >>> translation sets desc's `lmul` to `min(1, lmul)`, making >>> `vext_max_elems` >>> equivalent to `vext_get_total_elems`. >>> >>> eopXD (14): >>> target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed >>> target/riscv: rvv: Rename ambiguous esz >>> target/riscv: rvv: Early exit when vstart >= vl >>> target/riscv: rvv: Add tail agnostic for vv instructions >>> target/riscv: rvv: Add tail agnostic for vector load / store >>> instructions >>> target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions >>> target/riscv: rvv: Add tail agnostic for vector integer shift >>> instructions >>> target/riscv: rvv: Add tail agnostic for vector integer comparison >>> instructions >>> target/riscv: rvv: Add tail agnostic for vector integer merge and move >>> instructions >>> target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic >>> instructions >>> target/riscv: rvv: Add tail agnostic for vector floating-point >>> instructions >>> target/riscv: rvv: Add tail agnostic for vector reduction instructions >>> target/riscv: rvv: Add tail agnostic for vector mask instructions >>> target/riscv: rvv: Add tail agnostic for vector permutation >>> instructions >>> >>> target/riscv/cpu.c | 1 + >>> target/riscv/cpu.h | 2 + >>> target/riscv/cpu_helper.c | 2 + >>> target/riscv/insn_trans/trans_rvv.c.inc | 164 +++ >>> target/riscv/internals.h | 5 +- >>> target/riscv/translate.c | 2 + >>> target/riscv/vector_helper.c | 1562 ++++++++++++++--------- >>> 7 files changed, 1121 insertions(+), 617 deletions(-) >>> >> The patchset looks good to me. > Do you want to add a reviewed-by or acked-by tag? > > Alistair Is there any other prerequirement to add these tags? If not, It's OK for me to add reviewed-by on this patchset. Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Regards, Weiwei Li >> Regards, >> >> Weiwei Li >> >>
On Thu, Mar 31, 2022 at 11:24 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > > 在 2022/3/31 上午8:11, Alistair Francis 写道: > > On Wed, Mar 30, 2022 at 10:52 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > >> > >> 在 2022/3/30 下午6:24, ~eopxd 写道: > >>> According to v-spec, tail agnostic behavior can be either kept as > >>> undisturbed or set elements' bits to all 1s. To distinguish the > >>> difference of tail policies, QEMU should be able to simulate the tail > >>> agnostic behavior as "set tail elements' bits to all 1s". An option > >>> 'rvv_ta_all_1s' is added to enable the behavior, it is default as > >>> disabled. > >>> > >>> There are multiple possibility for agnostic elements according to > >>> v-spec. The main intent of this patch-set tries to add option that > >>> can distinguish between tail policies. Setting agnostic elements to > >>> all 1s makes things simple and allow QEMU to express this. > >>> > >>> We may explore other possibility of agnostic behavior by adding > >>> other options in the future. Please understand that this patch-set > >>> is limited. > >>> > >>> v2 updates: > >>> - Addressed comments from Weiwei Li > >>> - Added commit tail agnostic on load / store instructions (which > >>> I forgot to include into the patch-set) > >>> > >>> v3 updates: > >>> - Missed the very 1st commit, adding it back > >>> > >>> v4 updates: > >>> - Renamed vlmax to total_elems > >>> - Deal with tail element when vl_eq_vlmax == true > >>> > >>> v5 updates: > >>> - Let `vext_get_total_elems` take `desc` and `esz` > >>> - Utilize `simd_maxsz(desc)` to get `vlenb` > >>> - Fix alignments to code > >>> > >>> v6 updates: > >>> - Fix `vext_get_total_elems` > >>> > >>> v7 updates: > >>> - Reuse `max_elems` for vector load / store helper functions. The > >>> translation sets desc's `lmul` to `min(1, lmul)`, making > >>> `vext_max_elems` > >>> equivalent to `vext_get_total_elems`. > >>> > >>> eopXD (14): > >>> target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed > >>> target/riscv: rvv: Rename ambiguous esz > >>> target/riscv: rvv: Early exit when vstart >= vl > >>> target/riscv: rvv: Add tail agnostic for vv instructions > >>> target/riscv: rvv: Add tail agnostic for vector load / store > >>> instructions > >>> target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions > >>> target/riscv: rvv: Add tail agnostic for vector integer shift > >>> instructions > >>> target/riscv: rvv: Add tail agnostic for vector integer comparison > >>> instructions > >>> target/riscv: rvv: Add tail agnostic for vector integer merge and move > >>> instructions > >>> target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic > >>> instructions > >>> target/riscv: rvv: Add tail agnostic for vector floating-point > >>> instructions > >>> target/riscv: rvv: Add tail agnostic for vector reduction instructions > >>> target/riscv: rvv: Add tail agnostic for vector mask instructions > >>> target/riscv: rvv: Add tail agnostic for vector permutation > >>> instructions > >>> > >>> target/riscv/cpu.c | 1 + > >>> target/riscv/cpu.h | 2 + > >>> target/riscv/cpu_helper.c | 2 + > >>> target/riscv/insn_trans/trans_rvv.c.inc | 164 +++ > >>> target/riscv/internals.h | 5 +- > >>> target/riscv/translate.c | 2 + > >>> target/riscv/vector_helper.c | 1562 ++++++++++++++--------- > >>> 7 files changed, 1121 insertions(+), 617 deletions(-) > >>> > >> The patchset looks good to me. > > Do you want to add a reviewed-by or acked-by tag? > > > > Alistair > > Is there any other prerequirement to add these tags? If not, It's OK > for me to add reviewed-by on this patchset. There is no single rule, it's a personal decision. Generally if you have read through the code, understand it and think it works (matches QEMU style and architecture, bug free, matches hardware spec, etc) then you review it. > > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Thanks! Alistair > > Regards, > > Weiwei Li > > >> Regards, > >> > >> Weiwei Li > >> > >> >
Gentle ping, it is not picked to `riscv-to-apply.next` yet. Thank you. Yueh-Ting (eop) Chen > Alistair Francis <alistair23@gmail.com> 於 2022年3月31日 上午11:18 寫道： > > On Thu, Mar 31, 2022 at 11:24 AM Weiwei Li <liweiwei@iscas.ac.cn <mailto:liweiwei@iscas.ac.cn>> wrote: >> >> >> 在 2022/3/31 上午8:11, Alistair Francis 写道: >>> On Wed, Mar 30, 2022 at 10:52 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >>>> >>>> 在 2022/3/30 下午6:24, ~eopxd 写道: >>>>> According to v-spec, tail agnostic behavior can be either kept as >>>>> undisturbed or set elements' bits to all 1s. To distinguish the >>>>> difference of tail policies, QEMU should be able to simulate the tail >>>>> agnostic behavior as "set tail elements' bits to all 1s". An option >>>>> 'rvv_ta_all_1s' is added to enable the behavior, it is default as >>>>> disabled. >>>>> >>>>> There are multiple possibility for agnostic elements according to >>>>> v-spec. The main intent of this patch-set tries to add option that >>>>> can distinguish between tail policies. Setting agnostic elements to >>>>> all 1s makes things simple and allow QEMU to express this. >>>>> >>>>> We may explore other possibility of agnostic behavior by adding >>>>> other options in the future. Please understand that this patch-set >>>>> is limited. >>>>> >>>>> v2 updates: >>>>> - Addressed comments from Weiwei Li >>>>> - Added commit tail agnostic on load / store instructions (which >>>>> I forgot to include into the patch-set) >>>>> >>>>> v3 updates: >>>>> - Missed the very 1st commit, adding it back >>>>> >>>>> v4 updates: >>>>> - Renamed vlmax to total_elems >>>>> - Deal with tail element when vl_eq_vlmax == true >>>>> >>>>> v5 updates: >>>>> - Let `vext_get_total_elems` take `desc` and `esz` >>>>> - Utilize `simd_maxsz(desc)` to get `vlenb` >>>>> - Fix alignments to code >>>>> >>>>> v6 updates: >>>>> - Fix `vext_get_total_elems` >>>>> >>>>> v7 updates: >>>>> - Reuse `max_elems` for vector load / store helper functions. The >>>>> translation sets desc's `lmul` to `min(1, lmul)`, making >>>>> `vext_max_elems` >>>>> equivalent to `vext_get_total_elems`. >>>>> >>>>> eopXD (14): >>>>> target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed >>>>> target/riscv: rvv: Rename ambiguous esz >>>>> target/riscv: rvv: Early exit when vstart >= vl >>>>> target/riscv: rvv: Add tail agnostic for vv instructions >>>>> target/riscv: rvv: Add tail agnostic for vector load / store >>>>> instructions >>>>> target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions >>>>> target/riscv: rvv: Add tail agnostic for vector integer shift >>>>> instructions >>>>> target/riscv: rvv: Add tail agnostic for vector integer comparison >>>>> instructions >>>>> target/riscv: rvv: Add tail agnostic for vector integer merge and move >>>>> instructions >>>>> target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic >>>>> instructions >>>>> target/riscv: rvv: Add tail agnostic for vector floating-point >>>>> instructions >>>>> target/riscv: rvv: Add tail agnostic for vector reduction instructions >>>>> target/riscv: rvv: Add tail agnostic for vector mask instructions >>>>> target/riscv: rvv: Add tail agnostic for vector permutation >>>>> instructions >>>>> >>>>> target/riscv/cpu.c | 1 + >>>>> target/riscv/cpu.h | 2 + >>>>> target/riscv/cpu_helper.c | 2 + >>>>> target/riscv/insn_trans/trans_rvv.c.inc | 164 +++ >>>>> target/riscv/internals.h | 5 +- >>>>> target/riscv/translate.c | 2 + >>>>> target/riscv/vector_helper.c | 1562 ++++++++++++++--------- >>>>> 7 files changed, 1121 insertions(+), 617 deletions(-) >>>>> >>>> The patchset looks good to me. >>> Do you want to add a reviewed-by or acked-by tag? >>> >>> Alistair >> >> Is there any other prerequirement to add these tags? If not, It's OK >> for me to add reviewed-by on this patchset. > > There is no single rule, it's a personal decision. Generally if you > have read through the code, understand it and think it works (matches > QEMU style and architecture, bug free, matches hardware spec, etc) > then you review it. > >> >> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn <mailto:liweiwei@iscas.ac.cn>> > > Thanks! > > Alistair > >> >> Regards, >> >> Weiwei Li >> >>>> Regards, >>>> >>>> Weiwei Li
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