在 2022/3/19 下午8:50, ~eopxd 写道:
> According to v-spec, tail agnostic behavior can be either kept as
> undisturbed or set elements' bits to all 1s. To distinguish the
> difference of tail policies, qemu should be able to simulate the tail
> agnostic behavior as "set tail elements' bits to all 1s". An option
> 'rvv_ta_all_1s' is added to enable the behavior, it is default as
> disabled.
Another question: when rvv_ta_all_1s for vta is enabled, How about vma?
Is it necessary to set the inactive elements to all 1s?
Regards,
Weiwei Li
>
> eopXD (13):
> target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
> target/riscv: rvv: Rename ambiguous esz
> target/riscv: rvv: Early exit when vstart >= vl
> target/riscv: rvv: Add tail agnostic for vv instructions
> target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
> target/riscv: rvv: Add tail agnostic for vector integer shift
> instructions
> target/riscv: rvv: Add tail agnostic for vector integer comparison
> instructions
> target/riscv: rvv: Add tail agnostic for vector integer merge and move
> instructions
> target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic
> instructions
> target/riscv: rvv: Add tail agnostic for vector floating-point
> instructions
> target/riscv: rvv: Add tail agnostic for vector reduction instructions
> target/riscv: rvv: Add tail agnostic for vector mask instructions
> target/riscv: rvv: Add tail agnostic for vector permutation
> instructions
>
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 2 +
> target/riscv/cpu_helper.c | 2 +
> target/riscv/insn_trans/trans_rvv.c.inc | 58 +
> target/riscv/internals.h | 5 +-
> target/riscv/translate.c | 2 +
> target/riscv/vector_helper.c | 1508 ++++++++++++++---------
> 7 files changed, 961 insertions(+), 617 deletions(-)
>