From: Philippe Mathieu-Daudé <f4bug@amsat.org>
When the block is disabled, only the ECSPI_CONREG register can
be modified. Setting the EN bit enabled the device, clearing it
"disables the block and resets the internal logic with the
exception of the ECSPI_CONREG" register.
Ignore all other registers write except ECSPI_CONREG when the
block is disabled.
Ref: i.MX 6DQ Applications Processor Reference Manual (IMX6DQRM),
chapter 21.7.3: Control Register (ECSPIx_CONREG)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210115153049.3353008-6-f4bug@amsat.org>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Changes in v8:
- keep the controller disable logic in the ECSPI_CONREG case
in imx_spi_write()
Changes in v7:
- remove the RFC tag
Changes in v6:
- new patch: [RFC] rework imx_spi_write() to handle block disabled
hw/ssi/imx_spi.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
index 277b936..23f9f9d 100644
--- a/hw/ssi/imx_spi.c
+++ b/hw/ssi/imx_spi.c
@@ -327,6 +327,14 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
(uint32_t)value);
+ if (!imx_spi_is_enabled(s)) {
+ /* Block is disabled */
+ if (index != ECSPI_CONREG) {
+ /* Ignore access */
+ return;
+ }
+ }
+
change_mask = s->regs[index] ^ value;
switch (index) {
@@ -335,10 +343,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
TYPE_IMX_SPI, __func__);
break;
case ECSPI_TXDATA:
- if (!imx_spi_is_enabled(s)) {
- /* Ignore writes if device is disabled */
- break;
- } else if (fifo32_is_full(&s->tx_fifo)) {
+ if (fifo32_is_full(&s->tx_fifo)) {
/* Ignore writes if queue is full */
break;
}
--
2.7.4