hw/i386/intel_iommu.c | 7 ++++++- hw/i386/intel_iommu_internal.h | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-)
In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced
in VTD_IQA_REG. Sfotware could set this bit to tell VT-d the QI descriptor
from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should
be 5 when descriptor size is 256 bits.
This patch adds the DW bit check when deciding the shift used to update
VTD_IQH_REG.
Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
---
hw/i386/intel_iommu.c | 7 ++++++-
hw/i386/intel_iommu_internal.h | 3 ++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index df7ad25..8703a2d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2549,6 +2549,11 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
/* Try to fetch and process more Invalidation Descriptors */
static void vtd_fetch_inv_desc(IntelIOMMUState *s)
{
+ int qi_shift;
+
+ /* Refer to 10.4.23 of VT-d spec 3.0 */
+ qi_shift = s->iq_dw ? VTD_IQH_QH_SHIFT_5 : VTD_IQH_QH_SHIFT_4;
+
trace_vtd_inv_qi_fetch();
if (s->iq_tail >= s->iq_size) {
@@ -2567,7 +2572,7 @@ static void vtd_fetch_inv_desc(IntelIOMMUState *s)
}
/* Must update the IQH_REG in time */
vtd_set_quad_raw(s, DMAR_IQH_REG,
- (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
+ (((uint64_t)(s->iq_head)) << qi_shift) &
VTD_IQH_QH_MASK);
}
}
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 862033e..3d5487f 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -230,7 +230,8 @@
#define VTD_IQA_DW_MASK 0x800
/* IQH_REG */
-#define VTD_IQH_QH_SHIFT 4
+#define VTD_IQH_QH_SHIFT_4 4
+#define VTD_IQH_QH_SHIFT_5 5
#define VTD_IQH_QH_MASK 0x7fff0ULL
/* ICS_REG */
--
2.7.4
On Sat, Jul 04, 2020 at 01:07:15AM -0700, Liu Yi L wrote: > In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced > in VTD_IQA_REG. Sfotware could set this bit to tell VT-d the QI descriptor > from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should > be 5 when descriptor size is 256 bits. > > This patch adds the DW bit check when deciding the shift used to update > VTD_IQH_REG. > > Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> -- Peter Xu
> From: Peter Xu <peterx@redhat.com> > Sent: Tuesday, July 7, 2020 4:58 AM > > On Sat, Jul 04, 2020 at 01:07:15AM -0700, Liu Yi L wrote: > > In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was > > introduced in VTD_IQA_REG. Sfotware could set this bit to tell VT-d > > the QI descriptor from software would be 256 bits. Accordingly, the > > VTD_IQH_QH_SHIFT should be 5 when descriptor size is 256 bits. > > > > This patch adds the DW bit check when deciding the shift used to > > update VTD_IQH_REG. > > > > Signed-off-by: Liu Yi L <yi.l.liu@intel.com> > > Reviewed-by: Peter Xu <peterx@redhat.com> thanks. Regards, Yi Liu
On 2020/7/4 下午4:07, Liu Yi L wrote: > In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced > in VTD_IQA_REG. Sfotware could set this bit to tell VT-d the QI descriptor Typo. > from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should > be 5 when descriptor size is 256 bits. > > This patch adds the DW bit check when deciding the shift used to update > VTD_IQH_REG. > > Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Acked-by: Jason Wang <jasowang@redhat.com> > --- > hw/i386/intel_iommu.c | 7 ++++++- > hw/i386/intel_iommu_internal.h | 3 ++- > 2 files changed, 8 insertions(+), 2 deletions(-) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index df7ad25..8703a2d 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -2549,6 +2549,11 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) > /* Try to fetch and process more Invalidation Descriptors */ > static void vtd_fetch_inv_desc(IntelIOMMUState *s) > { > + int qi_shift; > + > + /* Refer to 10.4.23 of VT-d spec 3.0 */ > + qi_shift = s->iq_dw ? VTD_IQH_QH_SHIFT_5 : VTD_IQH_QH_SHIFT_4; > + > trace_vtd_inv_qi_fetch(); > > if (s->iq_tail >= s->iq_size) { > @@ -2567,7 +2572,7 @@ static void vtd_fetch_inv_desc(IntelIOMMUState *s) > } > /* Must update the IQH_REG in time */ > vtd_set_quad_raw(s, DMAR_IQH_REG, > - (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) & > + (((uint64_t)(s->iq_head)) << qi_shift) & > VTD_IQH_QH_MASK); > } > } > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index 862033e..3d5487f 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -230,7 +230,8 @@ > #define VTD_IQA_DW_MASK 0x800 > > /* IQH_REG */ > -#define VTD_IQH_QH_SHIFT 4 > +#define VTD_IQH_QH_SHIFT_4 4 > +#define VTD_IQH_QH_SHIFT_5 5 > #define VTD_IQH_QH_MASK 0x7fff0ULL > > /* ICS_REG */
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