On Mon, May 04, 2020 at 07:36:01PM +0530, Sai Pavan Boddu wrote:
> Set irq's specific to a queue, present implementation is setting q1 irq
> based on q0 status.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
> hw/net/cadence_gem.c | 25 +++----------------------
> 1 file changed, 3 insertions(+), 22 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 6cb2f64..a930bf1 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -554,29 +554,10 @@ static void gem_update_int_status(CadenceGEMState *s)
> {
> int i;
>
> - if (!s->regs[GEM_ISR]) {
> - /* ISR isn't set, clear all the interrupts */
> - for (i = 0; i < s->num_priority_queues; ++i) {
> - qemu_set_irq(s->irq[i], 0);
> - }
> - return;
> - }
> + qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]);
>
> - /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
> - * check it again.
> - */
> - if (s->num_priority_queues == 1) {
> - /* No priority queues, just trigger the interrupt */
> - DB_PRINT("asserting int.\n");
> - qemu_set_irq(s->irq[0], 1);
> - return;
> - }
> -
> - for (i = 0; i < s->num_priority_queues; ++i) {
> - if (s->regs[GEM_INT_Q1_STATUS + i]) {
> - DB_PRINT("asserting int. (q=%d)\n", i);
> - qemu_set_irq(s->irq[i], 1);
> - }
> + for (i = 1; i < s->num_priority_queues; ++i) {
> + qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]);
> }
> }
>
> --
> 2.7.4
>