The following changes since commit e0175b71638cf4398903c0d25f93fe62e0606389:

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200228' into staging (2020-02-28 16:39:27 +0000)

for you to fetch changes up to 41aa2e3f9b27fd259a13711545d933a20f1d2f16:

l2tpv3: fix RFC number typo in qemu-options.hx (2020-03-02 15:30:08 +0800)

Bin Meng (1):

hw: net: cadence_gem: Fix build errors in DB_PRINT()

Finn Thain (14):

dp8393x: Mask EOL bit from descriptor addresses

dp8393x: Always use 32-bit accesses

dp8393x: Clean up endianness hacks

dp8393x: Have dp8393x_receive() return the packet size

dp8393x: Update LLFA and CRDA registers from rx descriptor

dp8393x: Clear RRRA command register bit only when appropriate

dp8393x: Implement packet size limit and RBAE interrupt

dp8393x: Don't clobber packet checksum

dp8393x: Use long-word-aligned RRA pointers in 32-bit mode

dp8393x: Pad frames to word or long word boundary

dp8393x: Clear descriptor in_use field to release packet

dp8393x: Always update RRA pointers and sequence numbers

dp8393x: Don't reset Silicon Revision register

dp8393x: Don't stop reception upon RBE interrupt assertion

Lukas Straub (4):

block/replication.c: Ignore requests after failover

tests/test-replication.c: Add test for for secondary node continuing replication

net/filter.c: Add Options to insert filters anywhere in the filter list

colo: Update Documentation for continuous replication

Stefan Hajnoczi (1):

l2tpv3: fix RFC number typo in qemu-options.hx

Yuri Benditovich (3):

e1000e: Avoid hw_error if legacy mode used

NetRxPkt: Introduce support for additional hash types

NetRxPkt: fix hash calculation of IPV6 TCP

block/replication.c | 35 ++++++-

docs/COLO-FT.txt | 224 +++++++++++++++++++++++++++++++++------------

docs/block-replication.txt | 28 ++++--

hw/net/cadence_gem.c | 11 ++-

hw/net/dp8393x.c | 200 ++++++++++++++++++++++++++--------------

hw/net/e1000e_core.c | 15 +--

hw/net/net_rx_pkt.c | 44 ++++++++-

hw/net/net_rx_pkt.h | 6 +-

hw/net/trace-events | 4 +

include/net/filter.h | 2 +

net/filter.c | 92 ++++++++++++++++++-

qemu-options.hx | 35 +++++--

tests/test-replication.c | 52 +++++++++++

13 files changed, 591 insertions(+), 157 deletions(-)

From: Finn Thain <fthain@telegraphics.com.au>

The DP83932 and DP83934 have 32 data lines. The datasheet says,

Data Bus: These bidirectional lines are used to transfer data on the

system bus. When the SONIC is a bus master, 16-bit data is transferred

on D15-D0 and 32-bit data is transferred on D31-D0. When the SONIC is

accessed as a slave, register data is driven onto lines D15-D0.

D31-D16 are held TRI-STATE if SONIC is in 16-bit mode. If SONIC is in

32-bit mode, they are driven, but invalid.

Always use 32-bit accesses both as bus master and bus slave.

Force the MSW to zero in bus master mode.

This gets the Linux 'jazzsonic' driver working, and avoids the need for

prior hacks to make the NetBSD 'sn' driver work.

Signed-off-by: Finn Thain <fthain@telegraphics.com.au>

Tested-by: Laurent Vivier <laurent@vivier.eu>

hw/net/dp8393x.c | 47 +++++++++++++++++++++++++++++------------------

1 file changed, 29 insertions(+), 18 deletions(-)

diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c

--- a/hw/net/dp8393x.c

+++ b/hw/net/dp8393x.c

@@ -XXX,XX +XXX,XX @@ static void dp8393x_put(dp8393xState *s, int width, int offset,

uint16_t val)

{

if (s->big_endian) {

- s->data[offset * width + width - 1] = cpu_to_be16(val);

+ if (width == 2) {

+ s->data[offset * 2] = 0;

+ s->data[offset * 2 + 1] = cpu_to_be16(val);

+ } else {

+ s->data[offset] = cpu_to_be16(val);

+ }

} else {

- s->data[offset * width] = cpu_to_le16(val);

+ if (width == 2) {

+ s->data[offset * 2] = cpu_to_le16(val);

+ s->data[offset * 2 + 1] = 0;

+ } else {

+ s->data[offset] = cpu_to_le16(val);

+ }

}

}

@@ -XXX,XX +XXX,XX @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)

DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);

- return val;

+ return s->big_endian ? val << 16 : val;

}

static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,

@@ -XXX,XX +XXX,XX @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,

{

dp8393xState *s = opaque;

int reg = addr >> s->it_shift;

+ uint32_t val = s->big_endian ? data >> 16 : data;

- DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]);

+ DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]);

switch (reg) {

/* Command register */

case SONIC_CR:

- dp8393x_do_command(s, data);

+ dp8393x_do_command(s, val);

break;

/* Prevent write to read-only registers */

case SONIC_CAP2:

@@ -XXX,XX +XXX,XX @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,

/* Accept write to some registers only when in reset mode */

case SONIC_DCR:

if (s->regs[SONIC_CR] & SONIC_CR_RST) {

- s->regs[reg] = data & 0xbfff;

+ s->regs[reg] = val & 0xbfff;

} else {

DPRINTF("writing to DCR invalid\n");

}

break;

case SONIC_DCR2:

if (s->regs[SONIC_CR] & SONIC_CR_RST) {

- s->regs[reg] = data & 0xf017;

+ s->regs[reg] = val & 0xf017;

} else {

DPRINTF("writing to DCR2 invalid\n");

}

break;

/* 12 lower bytes are Read Only */

case SONIC_TCR:

- s->regs[reg] = data & 0xf000;

+ s->regs[reg] = val & 0xf000;

break;

/* 9 lower bytes are Read Only */

case SONIC_RCR:

- s->regs[reg] = data & 0xffe0;

+ s->regs[reg] = val & 0xffe0;

break;

/* Ignore most significant bit */

case SONIC_IMR:

- s->regs[reg] = data & 0x7fff;

+ s->regs[reg] = val & 0x7fff;

dp8393x_update_irq(s);

break;

/* Clear bits by writing 1 to them */

case SONIC_ISR:

- data &= s->regs[reg];

- s->regs[reg] &= ~data;

- if (data & SONIC_ISR_RBE) {

+ val &= s->regs[reg];

+ s->regs[reg] &= ~val;

+ if (val & SONIC_ISR_RBE) {

dp8393x_do_read_rra(s);

}

dp8393x_update_irq(s);

@@ -XXX,XX +XXX,XX @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,

case SONIC_REA:

case SONIC_RRP:

case SONIC_RWP:

- s->regs[reg] = data & 0xfffe;

+ s->regs[reg] = val & 0xfffe;

break;

/* Invert written value for some registers */

case SONIC_CRCT:

case SONIC_FAET:

case SONIC_MPT:

- s->regs[reg] = data ^ 0xffff;

+ s->regs[reg] = val ^ 0xffff;

break;

/* All other registers have no special contrainst */

default:

- s->regs[reg] = data;

+ s->regs[reg] = val;

}

if (reg == SONIC_WT0 || reg == SONIC_WT1) {

@@ -XXX,XX +XXX,XX @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,

static const MemoryRegionOps dp8393x_ops = {

.read = dp8393x_read,

.write = dp8393x_write,

- .impl.min_access_size = 2,

- .impl.max_access_size = 2,

+ .impl.min_access_size = 4,

+ .impl.max_access_size = 4,

.endianness = DEVICE_NATIVE_ENDIAN,

};

2.5.0

From: Finn Thain <fthain@telegraphics.com.au>

Section 3.4.7 of the datasheet explains that,

The RBE bit in the Interrupt Status register is set when the

SONIC finishes using the second to last receive buffer and reads

the last RRA descriptor. Actually, the SONIC is not truly out of

resources, but gives the system an early warning of an impending

out of resources condition.

RBE does not mean actual receive buffer exhaustion, and reception should

not be stopped. This is important because Linux will not check and clear

the RBE interrupt until it receives another packet. But that won't

happen if can_receive returns false. This bug causes the SONIC to become

deaf (until reset).

Fix this with a new flag to indicate actual receive buffer exhaustion.

Signed-off-by: Finn Thain <fthain@telegraphics.com.au>

Tested-by: Laurent Vivier <laurent@vivier.eu>

hw/net/dp8393x.c | 35 ++++++++++++++++++++++-------------

1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c

--- a/hw/net/dp8393x.c

+++ b/hw/net/dp8393x.c

@@ -XXX,XX +XXX,XX @@ typedef struct dp8393xState {

/* Hardware */

uint8_t it_shift;

bool big_endian;

+ bool last_rba_is_full;

qemu_irq irq;

#ifdef DEBUG_SONIC

int irq_level;

@@ -XXX,XX +XXX,XX @@ static void dp8393x_do_read_rra(dp8393xState *s)

s->regs[SONIC_RRP] = s->regs[SONIC_RSA];

}

- /* Check resource exhaustion */

+ /* Warn the host if CRBA now has the last available resource */

if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])

{

s->regs[SONIC_ISR] |= SONIC_ISR_RBE;

dp8393x_update_irq(s);

}

+ /* Allow packet reception */

+ s->last_rba_is_full = false;

static void dp8393x_do_software_reset(dp8393xState *s)

@@ -XXX,XX +XXX,XX @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,

dp8393x_do_read_rra(s);

}

dp8393x_update_irq(s);

- if (dp8393x_can_receive(s->nic->ncs)) {

- qemu_flush_queued_packets(qemu_get_queue(s->nic));

- }

break;

/* The guest is required to store aligned pointers here */

case SONIC_RSA:

@@ -XXX,XX +XXX,XX @@ static int dp8393x_can_receive(NetClientState *nc)

if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))

return 0;

- if (s->regs[SONIC_ISR] & SONIC_ISR_RBE)

- return 0;

return 1;

}

@@ -XXX,XX +XXX,XX @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,

s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |

SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);

+ if (s->last_rba_is_full) {

+ return pkt_size;

rx_len = pkt_size + sizeof(checksum);

if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {

width = 2;

@@ -XXX,XX +XXX,XX @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,

DPRINTF("oversize packet, pkt_size is %d\n", pkt_size);

s->regs[SONIC_ISR] |= SONIC_ISR_RBAE;

dp8393x_update_irq(s);

- dp8393x_do_read_rra(s);

- return pkt_size;

+ s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;

+ goto done;

}

packet_type = dp8393x_receive_filter(s, buf, pkt_size);

@@ -XXX,XX +XXX,XX @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,

s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;

}

+ dp8393x_update_irq(s);

s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) |

((s->regs[SONIC_RSC] + 1) & 0x00ff);

+done:

if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {

- /* Read next RRA */

- dp8393x_do_read_rra(s);

+ if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {

+ /* Stop packet reception */

+ s->last_rba_is_full = true;

+ } else {

+ /* Read next resource */

+ dp8393x_do_read_rra(s);

+ }

}

- /* Done */

- dp8393x_update_irq(s);

-

return pkt_size;

2.5.0

From: Stefan Hajnoczi <stefanha@redhat.com>

The L2TPv3 RFC number is 3931:

https://tools.ietf.org/html/rfc3931

Reported-by: Henrik Johansson <henrikjohansson@rocketmail.com>

Reviewed-by: Stefan Weil <sw@weilnetz.de>

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

qemu-options.hx | 4 ++--

1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu-options.hx b/qemu-options.hx

index XXXXXXX..XXXXXXX 100644

--- a/qemu-options.hx

+++ b/qemu-options.hx

@@ -XXX,XX +XXX,XX @@ DEF("netdev", HAS_ARG, QEMU_OPTION_netdev,

" Linux kernel 3.3+ as well as most routers can talk\n"

" L2TPv3. This transport allows connecting a VM to a VM,\n"

" VM to a router and even VM to Host. It is a nearly-universal\n"

- " standard (RFC3391). Note - this implementation uses static\n"

+ " standard (RFC3931). Note - this implementation uses static\n"

" pre-configured tunnels (same as the Linux kernel).\n"

" use 'src=' to specify source address\n"

" use 'dst=' to specify destination address\n"

@@ -XXX,XX +XXX,XX @@ Example (send packets from host's 1.2.3.4):

@end example

@item -netdev l2tpv3,id=@var{id},src=@var{srcaddr},dst=@var{dstaddr}[,srcport=@var{srcport}][,dstport=@var{dstport}],txsession=@var{txsession}[,rxsession=@var{rxsession}][,ipv6][,udp][,cookie64][,counter][,pincounter][,txcookie=@var{txcookie}][,rxcookie=@var{rxcookie}][,offset=@var{offset}]

-Configure a L2TPv3 pseudowire host network backend. L2TPv3 (RFC3391) is a

+Configure a L2TPv3 pseudowire host network backend. L2TPv3 (RFC3931) is a

popular protocol to transport Ethernet (and other Layer 2) data frames between

two systems. It is present in routers, firewalls and the Linux kernel

(from version 3.3 onwards).