[PATCH 0/3] Add CPU model for intel processor Cooper Lake

Cathy Zhang posted 3 patches 5 weeks ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/1570863638-22272-1-git-send-email-cathy.zhang@intel.com
Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Eduardo Habkost <ehabkost@redhat.com>, Richard Henderson <rth@twiddle.net>
target/i386/cpu.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h |  2 ++
2 files changed, 61 insertions(+)

[PATCH 0/3] Add CPU model for intel processor Cooper Lake

Posted by Cathy Zhang 5 weeks ago
This patchset is to add CPU model for intel processor Cooper Lake. It 
will inherit features from the existing CPU model Cascadelake-Server, 
meanwhile, add the platform associated new instruction and feature
for speculative execution which the host supports. There are associated
feature bit and macro defined here as needed. 

Cathy Zhang (3):
  i386: Add MSR feature bit for MDS-NO
  i386: Add macro for stibp
  i386: Add new CPU model Cooperlake

 target/i386/cpu.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 target/i386/cpu.h |  2 ++
 2 files changed, 61 insertions(+)

-- 
1.8.3.1


Re: [PATCH 0/3] Add CPU model for intel processor Cooper Lake

Posted by no-reply@patchew.org 5 weeks ago
Patchew URL: https://patchew.org/QEMU/1570863638-22272-1-git-send-email-cathy.zhang@intel.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH 0/3] Add CPU model for intel processor Cooper Lake
Type: series
Message-id: 1570863638-22272-1-git-send-email-cathy.zhang@intel.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Switched to a new branch 'test'
c16a74f i386: Add new CPU model Cooperlake
c70bdd0 i386: Add macro for stibp
073abd3 i386: Add MSR feature bit for MDS-NO

=== OUTPUT BEGIN ===
1/3 Checking commit 073abd367191 (i386: Add MSR feature bit for MDS-NO)
2/3 Checking commit c70bdd0665f0 (i386: Add macro for stibp)
WARNING: line over 80 characters
#23: FILE: target/i386/cpu.h:720:
+#define CPUID_7_0_EDX_STIBP     (1U << 27) /* Single Thread Indirect Branch Predictors */

total: 0 errors, 1 warnings, 7 lines checked

Patch 2/3 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/3 Checking commit c16a74f138e1 (i386: Add new CPU model Cooperlake)
ERROR: trailing whitespace
#52: FILE: target/i386/cpu.c:2644:
+            CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | $

ERROR: trailing whitespace
#61: FILE: target/i386/cpu.c:2653:
+            CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, $

WARNING: Block comments use a leading /* on a separate line
#67: FILE: target/i386/cpu.c:2659:
+        /* Missing: XSAVES (not supported by some Linux versions,

WARNING: Block comments should align the * on each line
#68: FILE: target/i386/cpu.c:2660:
+        /* Missing: XSAVES (not supported by some Linux versions,
+                * including v4.1 to v4.12).

total: 2 errors, 2 warnings, 65 lines checked

Patch 3/3 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/1570863638-22272-1-git-send-email-cathy.zhang@intel.com/testing.checkpatch/?type=message.
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