Introduce cpu core complex id(ccx_id) in x86CPU topology.
Each CCX can have upto 4 cores and share same L3 cache.
This information is required to build the topology in
new apyc mode.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/core/machine-hmp-cmds.c | 3 +++
hw/core/machine.c | 13 +++++++++++++
hw/i386/pc.c | 10 ++++++++++
include/hw/i386/topology.h | 1 +
qapi/machine.json | 4 +++-
target/i386/cpu.c | 2 ++
target/i386/cpu.h | 1 +
7 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
index 1f66bda346..6c534779af 100644
--- a/hw/core/machine-hmp-cmds.c
+++ b/hw/core/machine-hmp-cmds.c
@@ -89,6 +89,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
if (c->has_die_id) {
monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
}
+ if (c->has_ccx_id) {
+ monitor_printf(mon, " ccx-id: \"%" PRIu64 "\"\n", c->ccx_id);
+ }
if (c->has_core_id) {
monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
}
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 4034b7e903..9a8586cf30 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -694,6 +694,11 @@ void machine_set_cpu_numa_node(MachineState *machine,
return;
}
+ if (props->has_ccx_id && !slot->props.has_ccx_id) {
+ error_setg(errp, "ccx-id is not supported");
+ return;
+ }
+
/* skip slots with explicit mismatch */
if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
continue;
@@ -707,6 +712,10 @@ void machine_set_cpu_numa_node(MachineState *machine,
continue;
}
+ if (props->has_ccx_id && props->ccx_id != slot->props.ccx_id) {
+ continue;
+ }
+
if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
continue;
}
@@ -1041,6 +1050,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
if (cpu->props.has_die_id) {
g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
}
+
+ if (cpu->props.has_ccx_id) {
+ g_string_append_printf(s, "ccx-id: %"PRId64, cpu->props.ccx_id);
+ }
if (cpu->props.has_core_id) {
if (s->len) {
g_string_append_printf(s, ", ");
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 9e1c3f9f57..f71389ad9f 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -2444,6 +2444,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
topo_ids.pkg_id = cpu->socket_id;
topo_ids.die_id = cpu->die_id;
+ topo_ids.ccx_id = cpu->ccx_id;
topo_ids.core_id = cpu->core_id;
topo_ids.smt_id = cpu->thread_id;
cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids);
@@ -2489,6 +2490,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
}
cpu->die_id = topo_ids.die_id;
+ if (cpu->ccx_id != -1 && cpu->ccx_id != topo_ids.ccx_id) {
+ error_setg(errp, "property ccx-id: %u doesn't match set apic-id:"
+ " 0x%x (ccx-id: %u)", cpu->ccx_id, cpu->apic_id, topo_ids.ccx_id);
+ return;
+ }
+ cpu->ccx_id = topo_ids.ccx_id;
+
if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
error_setg(errp, "property core-id: %u doesn't match set apic-id:"
" 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id);
@@ -2896,6 +2904,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
ms->possible_cpus->cpus[i].props.has_die_id = true;
ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;
+ ms->possible_cpus->cpus[i].props.has_ccx_id = true;
+ ms->possible_cpus->cpus[i].props.ccx_id = topo_ids.ccx_id;
ms->possible_cpus->cpus[i].props.has_core_id = true;
ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;
ms->possible_cpus->cpus[i].props.has_thread_id = true;
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index fb10863a66..5a61d53f05 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -170,6 +170,7 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
(apicid >> apicid_die_offset(nr_cores, nr_threads)) &
~(0xFFFFFFFFUL << apicid_die_width(nr_dies));
topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads);
+ topo_ids->ccx_id = 0;
}
/* Make APIC ID for the CPU 'cpu_index'
diff --git a/qapi/machine.json b/qapi/machine.json
index 6db8a7e2ec..bb7627e698 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -597,9 +597,10 @@
# @node-id: NUMA node ID the CPU belongs to
# @socket-id: socket number within node/board the CPU belongs to
# @die-id: die number within node/board the CPU belongs to (Since 4.1)
+# @ccx-id: core complex number within node/board the CPU belongs to (Since 4.1)
# @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to
#
-# Note: currently there are 5 properties that could be present
+# Note: currently there are 6 properties that could be present
# but management should be prepared to pass through other
# properties with device_add command to allow for future
# interface extension. This also requires the filed names to be kept in
@@ -611,6 +612,7 @@
'data': { '*node-id': 'int',
'*socket-id': 'int',
'*die-id': 'int',
+ '*ccx-id': 'int',
'*core-id': 'int',
'*thread-id': 'int'
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6d7f9b6b8b..ca02bc21ec 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5811,12 +5811,14 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
+ DEFINE_PROP_INT32("ccx-id", X86CPU, ccx_id, 0),
DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
#else
DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
+ DEFINE_PROP_INT32("ccx-id", X86CPU, ccx_id, -1),
DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
#endif
DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 8b3dc5533e..db940cdb2a 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1508,6 +1508,7 @@ struct X86CPU {
int32_t node_id; /* NUMA node this CPU belongs to */
int32_t socket_id;
int32_t die_id;
+ int32_t ccx_id;
int32_t core_id;
int32_t thread_id;
On 9/6/19 2:12 PM, Moger, Babu wrote: > Introduce cpu core complex id(ccx_id) in x86CPU topology. > Each CCX can have upto 4 cores and share same L3 cache. > This information is required to build the topology in > new apyc mode. > > Signed-off-by: Babu Moger <babu.moger@amd.com> > --- > +++ b/qapi/machine.json > @@ -597,9 +597,10 @@ > # @node-id: NUMA node ID the CPU belongs to > # @socket-id: socket number within node/board the CPU belongs to > # @die-id: die number within node/board the CPU belongs to (Since 4.1) > +# @ccx-id: core complex number within node/board the CPU belongs to (Since 4.1) 4.2 now > # @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to Pre-existing, but let's fix that missing newline while you're here. -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org
On 9/6/19 2:20 PM, Eric Blake wrote: > On 9/6/19 2:12 PM, Moger, Babu wrote: >> Introduce cpu core complex id(ccx_id) in x86CPU topology. >> Each CCX can have upto 4 cores and share same L3 cache. >> This information is required to build the topology in >> new apyc mode. >> >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> --- > >> +++ b/qapi/machine.json >> @@ -597,9 +597,10 @@ >> # @node-id: NUMA node ID the CPU belongs to >> # @socket-id: socket number within node/board the CPU belongs to >> # @die-id: die number within node/board the CPU belongs to (Since 4.1) >> +# @ccx-id: core complex number within node/board the CPU belongs to (Since 4.1) > > 4.2 now ok. Will fix. > >> # @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to > > Pre-existing, but let's fix that missing newline while you're here. Sure. will take care. thanks
On Fri, Sep 06, 2019 at 07:12:18PM +0000, Moger, Babu wrote:
> Introduce cpu core complex id(ccx_id) in x86CPU topology.
> Each CCX can have upto 4 cores and share same L3 cache.
> This information is required to build the topology in
> new apyc mode.
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> hw/core/machine-hmp-cmds.c | 3 +++
> hw/core/machine.c | 13 +++++++++++++
> hw/i386/pc.c | 10 ++++++++++
> include/hw/i386/topology.h | 1 +
> qapi/machine.json | 4 +++-
> target/i386/cpu.c | 2 ++
> target/i386/cpu.h | 1 +
> 7 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
> index 1f66bda346..6c534779af 100644
> --- a/hw/core/machine-hmp-cmds.c
> +++ b/hw/core/machine-hmp-cmds.c
> @@ -89,6 +89,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
> if (c->has_die_id) {
> monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
> }
> + if (c->has_ccx_id) {
> + monitor_printf(mon, " ccx-id: \"%" PRIu64 "\"\n", c->ccx_id);
> + }
> if (c->has_core_id) {
> monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
> }
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index 4034b7e903..9a8586cf30 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -694,6 +694,11 @@ void machine_set_cpu_numa_node(MachineState *machine,
> return;
> }
>
> + if (props->has_ccx_id && !slot->props.has_ccx_id) {
> + error_setg(errp, "ccx-id is not supported");
> + return;
> + }
> +
> /* skip slots with explicit mismatch */
> if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
> continue;
> @@ -707,6 +712,10 @@ void machine_set_cpu_numa_node(MachineState *machine,
> continue;
> }
>
> + if (props->has_ccx_id && props->ccx_id != slot->props.ccx_id) {
> + continue;
> + }
> +
> if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
> continue;
> }
> @@ -1041,6 +1050,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
> if (cpu->props.has_die_id) {
> g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
> }
> +
> + if (cpu->props.has_ccx_id) {
> + g_string_append_printf(s, "ccx-id: %"PRId64, cpu->props.ccx_id);
> + }
> if (cpu->props.has_core_id) {
> if (s->len) {
> g_string_append_printf(s, ", ");
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 9e1c3f9f57..f71389ad9f 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -2444,6 +2444,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
>
> topo_ids.pkg_id = cpu->socket_id;
> topo_ids.die_id = cpu->die_id;
> + topo_ids.ccx_id = cpu->ccx_id;
> topo_ids.core_id = cpu->core_id;
> topo_ids.smt_id = cpu->thread_id;
> cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids);
> @@ -2489,6 +2490,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
> }
> cpu->die_id = topo_ids.die_id;
>
> + if (cpu->ccx_id != -1 && cpu->ccx_id != topo_ids.ccx_id) {
> + error_setg(errp, "property ccx-id: %u doesn't match set apic-id:"
> + " 0x%x (ccx-id: %u)", cpu->ccx_id, cpu->apic_id, topo_ids.ccx_id);
> + return;
> + }
> + cpu->ccx_id = topo_ids.ccx_id;
> +
> if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
> error_setg(errp, "property core-id: %u doesn't match set apic-id:"
> " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id);
> @@ -2896,6 +2904,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
> ms->possible_cpus->cpus[i].props.has_die_id = true;
> ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;
> + ms->possible_cpus->cpus[i].props.has_ccx_id = true;
> + ms->possible_cpus->cpus[i].props.ccx_id = topo_ids.ccx_id;
> ms->possible_cpus->cpus[i].props.has_core_id = true;
> ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;
> ms->possible_cpus->cpus[i].props.has_thread_id = true;
> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
> index fb10863a66..5a61d53f05 100644
> --- a/include/hw/i386/topology.h
> +++ b/include/hw/i386/topology.h
> @@ -170,6 +170,7 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
> (apicid >> apicid_die_offset(nr_cores, nr_threads)) &
> ~(0xFFFFFFFFUL << apicid_die_width(nr_dies));
> topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads);
> + topo_ids->ccx_id = 0;
> }
>
> /* Make APIC ID for the CPU 'cpu_index'
> diff --git a/qapi/machine.json b/qapi/machine.json
> index 6db8a7e2ec..bb7627e698 100644
> --- a/qapi/machine.json
> +++ b/qapi/machine.json
> @@ -597,9 +597,10 @@
> # @node-id: NUMA node ID the CPU belongs to
> # @socket-id: socket number within node/board the CPU belongs to
> # @die-id: die number within node/board the CPU belongs to (Since 4.1)
> +# @ccx-id: core complex number within node/board the CPU belongs to (Since 4.1)
Can we come up with a non-AMD specific name?
E.g. would "last level cache" be correct for AMD?
Better ideas?
> # @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to
> #
> -# Note: currently there are 5 properties that could be present
> +# Note: currently there are 6 properties that could be present
> # but management should be prepared to pass through other
> # properties with device_add command to allow for future
> # interface extension. This also requires the filed names to be kept in
> @@ -611,6 +612,7 @@
> 'data': { '*node-id': 'int',
> '*socket-id': 'int',
> '*die-id': 'int',
> + '*ccx-id': 'int',
> '*core-id': 'int',
> '*thread-id': 'int'
> }
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 6d7f9b6b8b..ca02bc21ec 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -5811,12 +5811,14 @@ static Property x86_cpu_properties[] = {
> DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
> DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
> DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
> + DEFINE_PROP_INT32("ccx-id", X86CPU, ccx_id, 0),
> DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
> #else
> DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
> DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
> DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
> DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
> + DEFINE_PROP_INT32("ccx-id", X86CPU, ccx_id, -1),
> DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
> #endif
> DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 8b3dc5533e..db940cdb2a 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1508,6 +1508,7 @@ struct X86CPU {
> int32_t node_id; /* NUMA node this CPU belongs to */
> int32_t socket_id;
> int32_t die_id;
> + int32_t ccx_id;
> int32_t core_id;
> int32_t thread_id;
>
>
On 9/22/19 7:48 AM, Michael S. Tsirkin wrote:
> On Fri, Sep 06, 2019 at 07:12:18PM +0000, Moger, Babu wrote:
>> Introduce cpu core complex id(ccx_id) in x86CPU topology.
>> Each CCX can have upto 4 cores and share same L3 cache.
>> This information is required to build the topology in
>> new apyc mode.
>>
>> Signed-off-by: Babu Moger <babu.moger@amd.com>
>> ---
>> hw/core/machine-hmp-cmds.c | 3 +++
>> hw/core/machine.c | 13 +++++++++++++
>> hw/i386/pc.c | 10 ++++++++++
>> include/hw/i386/topology.h | 1 +
>> qapi/machine.json | 4 +++-
>> target/i386/cpu.c | 2 ++
>> target/i386/cpu.h | 1 +
>> 7 files changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c
>> index 1f66bda346..6c534779af 100644
>> --- a/hw/core/machine-hmp-cmds.c
>> +++ b/hw/core/machine-hmp-cmds.c
>> @@ -89,6 +89,9 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict)
>> if (c->has_die_id) {
>> monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id);
>> }
>> + if (c->has_ccx_id) {
>> + monitor_printf(mon, " ccx-id: \"%" PRIu64 "\"\n", c->ccx_id);
>> + }
>> if (c->has_core_id) {
>> monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_id);
>> }
>> diff --git a/hw/core/machine.c b/hw/core/machine.c
>> index 4034b7e903..9a8586cf30 100644
>> --- a/hw/core/machine.c
>> +++ b/hw/core/machine.c
>> @@ -694,6 +694,11 @@ void machine_set_cpu_numa_node(MachineState *machine,
>> return;
>> }
>>
>> + if (props->has_ccx_id && !slot->props.has_ccx_id) {
>> + error_setg(errp, "ccx-id is not supported");
>> + return;
>> + }
>> +
>> /* skip slots with explicit mismatch */
>> if (props->has_thread_id && props->thread_id != slot->props.thread_id) {
>> continue;
>> @@ -707,6 +712,10 @@ void machine_set_cpu_numa_node(MachineState *machine,
>> continue;
>> }
>>
>> + if (props->has_ccx_id && props->ccx_id != slot->props.ccx_id) {
>> + continue;
>> + }
>> +
>> if (props->has_socket_id && props->socket_id != slot->props.socket_id) {
>> continue;
>> }
>> @@ -1041,6 +1050,10 @@ static char *cpu_slot_to_string(const CPUArchId *cpu)
>> if (cpu->props.has_die_id) {
>> g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id);
>> }
>> +
>> + if (cpu->props.has_ccx_id) {
>> + g_string_append_printf(s, "ccx-id: %"PRId64, cpu->props.ccx_id);
>> + }
>> if (cpu->props.has_core_id) {
>> if (s->len) {
>> g_string_append_printf(s, ", ");
>> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
>> index 9e1c3f9f57..f71389ad9f 100644
>> --- a/hw/i386/pc.c
>> +++ b/hw/i386/pc.c
>> @@ -2444,6 +2444,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
>>
>> topo_ids.pkg_id = cpu->socket_id;
>> topo_ids.die_id = cpu->die_id;
>> + topo_ids.ccx_id = cpu->ccx_id;
>> topo_ids.core_id = cpu->core_id;
>> topo_ids.smt_id = cpu->thread_id;
>> cpu->apic_id = apicid_from_topo_ids(&topo_info, &topo_ids);
>> @@ -2489,6 +2490,13 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_dev,
>> }
>> cpu->die_id = topo_ids.die_id;
>>
>> + if (cpu->ccx_id != -1 && cpu->ccx_id != topo_ids.ccx_id) {
>> + error_setg(errp, "property ccx-id: %u doesn't match set apic-id:"
>> + " 0x%x (ccx-id: %u)", cpu->ccx_id, cpu->apic_id, topo_ids.ccx_id);
>> + return;
>> + }
>> + cpu->ccx_id = topo_ids.ccx_id;
>> +
>> if (cpu->core_id != -1 && cpu->core_id != topo_ids.core_id) {
>> error_setg(errp, "property core-id: %u doesn't match set apic-id:"
>> " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.core_id);
>> @@ -2896,6 +2904,8 @@ static const CPUArchIdList *pc_possible_cpu_arch_ids(MachineState *ms)
>> ms->possible_cpus->cpus[i].props.socket_id = topo_ids.pkg_id;
>> ms->possible_cpus->cpus[i].props.has_die_id = true;
>> ms->possible_cpus->cpus[i].props.die_id = topo_ids.die_id;
>> + ms->possible_cpus->cpus[i].props.has_ccx_id = true;
>> + ms->possible_cpus->cpus[i].props.ccx_id = topo_ids.ccx_id;
>> ms->possible_cpus->cpus[i].props.has_core_id = true;
>> ms->possible_cpus->cpus[i].props.core_id = topo_ids.core_id;
>> ms->possible_cpus->cpus[i].props.has_thread_id = true;
>> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
>> index fb10863a66..5a61d53f05 100644
>> --- a/include/hw/i386/topology.h
>> +++ b/include/hw/i386/topology.h
>> @@ -170,6 +170,7 @@ static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
>> (apicid >> apicid_die_offset(nr_cores, nr_threads)) &
>> ~(0xFFFFFFFFUL << apicid_die_width(nr_dies));
>> topo_ids->pkg_id = apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_threads);
>> + topo_ids->ccx_id = 0;
>> }
>>
>> /* Make APIC ID for the CPU 'cpu_index'
>> diff --git a/qapi/machine.json b/qapi/machine.json
>> index 6db8a7e2ec..bb7627e698 100644
>> --- a/qapi/machine.json
>> +++ b/qapi/machine.json
>> @@ -597,9 +597,10 @@
>> # @node-id: NUMA node ID the CPU belongs to
>> # @socket-id: socket number within node/board the CPU belongs to
>> # @die-id: die number within node/board the CPU belongs to (Since 4.1)
>> +# @ccx-id: core complex number within node/board the CPU belongs to (Since 4.1)
>
> Can we come up with a non-AMD specific name?
> E.g. would "last level cache" be correct for AMD?
> Better ideas?
Yes. Last level cache (or llc_id) should work. Will change it next
revision. Thanks
>
>> # @core-id: core number within die the CPU belongs to# @thread-id: thread number within core the CPU belongs to
>> #
>> -# Note: currently there are 5 properties that could be present
>> +# Note: currently there are 6 properties that could be present
>> # but management should be prepared to pass through other
>> # properties with device_add command to allow for future
>> # interface extension. This also requires the filed names to be kept in
>> @@ -611,6 +612,7 @@
>> 'data': { '*node-id': 'int',
>> '*socket-id': 'int',
>> '*die-id': 'int',
>> + '*ccx-id': 'int',
>> '*core-id': 'int',
>> '*thread-id': 'int'
>> }
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 6d7f9b6b8b..ca02bc21ec 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -5811,12 +5811,14 @@ static Property x86_cpu_properties[] = {
>> DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
>> DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
>> DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
>> + DEFINE_PROP_INT32("ccx-id", X86CPU, ccx_id, 0),
>> DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
>> #else
>> DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
>> DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
>> DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
>> DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
>> + DEFINE_PROP_INT32("ccx-id", X86CPU, ccx_id, -1),
>> DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
>> #endif
>> DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>> index 8b3dc5533e..db940cdb2a 100644
>> --- a/target/i386/cpu.h
>> +++ b/target/i386/cpu.h
>> @@ -1508,6 +1508,7 @@ struct X86CPU {
>> int32_t node_id; /* NUMA node this CPU belongs to */
>> int32_t socket_id;
>> int32_t die_id;
>> + int32_t ccx_id;
>> int32_t core_id;
>> int32_t thread_id;
>>
>>
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