From: Aleksandar Markovic <amarkovic@wavecomp.com>

The following changes since commit 1b142da5f82a8fcdc7783a418592de654d5c6052:

  target/mips: Clean up handling of CP0 register 0 (2019-08-29 11:50:18 +0200)

are available in the git repository at:

  https://github.com/AMarkovic/qemu tags/mips-queue-aug-29-2019

for you to fetch changes up to abd4393d769d9fe2333b2e83e00f911a78475943:

  target/mips: Fix emulation of ST.W in system mode (2019-08-29 12:11:14 +0200)

----------------------------------------------------------------

MIPS queue for August 29th, 2019

Highlights:

  - cleanup of handling of configuration register CP0
  - fix for ST.W emulation (in system mode only)

----------------------------------------------------------------

Aleksandar Markovic (31):
  target/mips: Clean up handling of CP0 register 0
  target/mips: Clean up handling of CP0 register 1
  target/mips: Clean up handling of CP0 register 2
  target/mips: Clean up handling of CP0 register 3
  target/mips: Clean up handling of CP0 register 4
  target/mips: Clean up handling of CP0 register 5
  target/mips: Clean up handling of CP0 register 6
  target/mips: Clean up handling of CP0 register 7
  target/mips: Clean up handling of CP0 register 8
  target/mips: Clean up handling of CP0 register 9
  target/mips: Clean up handling of CP0 register 10
  target/mips: Clean up handling of CP0 register 11
  target/mips: Clean up handling of CP0 register 12
  target/mips: Clean up handling of CP0 register 13
  target/mips: Clean up handling of CP0 register 14
  target/mips: Clean up handling of CP0 register 15
  target/mips: Clean up handling of CP0 register 16
  target/mips: Clean up handling of CP0 register 17
  target/mips: Clean up handling of CP0 register 18
  target/mips: Clean up handling of CP0 register 19
  target/mips: Clean up handling of CP0 register 20
  target/mips: Clean up handling of CP0 register 23
  target/mips: Clean up handling of CP0 register 24
  target/mips: Clean up handling of CP0 register 25
  target/mips: Clean up handling of CP0 register 26
  target/mips: Clean up handling of CP0 register 27
  target/mips: Clean up handling of CP0 register 28
  target/mips: Clean up handling of CP0 register 29
  target/mips: Clean up handling of CP0 register 30
  target/mips: Clean up handling of CP0 register 31
  target/mips: Fix emulation of ST.W in system mode

 target/mips/cpu.h       |  113 ++++-
 target/mips/op_helper.c |   16 +-
 target/mips/translate.c | 1142 ++++++++++++++++++++++++-----------------------
 3 files changed, 685 insertions(+), 586 deletions(-)

-- 
2.7.4

On Thu, 29 Aug 2019 at 11:25, Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
>
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> The following changes since commit 1b142da5f82a8fcdc7783a418592de654d5c6052:
>
>   target/mips: Clean up handling of CP0 register 0 (2019-08-29 11:50:18 +0200)
>
> are available in the git repository at:
>
>   https://github.com/AMarkovic/qemu tags/mips-queue-aug-29-2019
>
> for you to fetch changes up to abd4393d769d9fe2333b2e83e00f911a78475943:
>
>   target/mips: Fix emulation of ST.W in system mode (2019-08-29 12:11:14 +0200)
>
> ----------------------------------------------------------------
>
> MIPS queue for August 29th, 2019
>
> Highlights:
>
>   - cleanup of handling of configuration register CP0
>   - fix for ST.W emulation (in system mode only)
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.

-- PMM