As of today, the QEMU 'sifive_u' machine is a special target that does
not boot the upstream OpenSBI/U-Boot firmware images built for the real
SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
"qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced
in the OpenSBI doc as its payload, but that does not boot at all due
to various issues in current QEMU 'sifive_u' machine codes.

This series aims to improve the emulation fidelity of sifive_u machine,
so that the upstream OpenSBI, U-Boot and kernel images built for the
SiFive HiFive Unleashed board can be used out of the box without any
special hack.

The major changes include:
- Heterogeneous harts creation supported, so that we can create a CPU
  that exactly mirrors the real hardware: 1 E51 + 4 U54.
- Implemented a PRCI model for FU540
- Implemented an OTP model for FU540, primarily used for storing serial
  number of the board
- Fixed GEM support that was seriously broken on sifive_u
- Synced device tree with upstream Linux kernel on sifive_u
- Adding initramfs loading support on sifive_u

OpenSBI v0.4 image built for sifive/fu540 is included as the default
bios image for 'sifive_u' machine.

The series is tested against OpenSBI v0.4 image for sifive/fu540
paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig,
and Linux kernel v5.3-rc3 image with the following patch:

macb: Update compatibility string for SiFive FU540-C000
https://patchwork.kernel.org/patch/11050003/

OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well.
Boot Linux 64-bit defconfig image, verified that system console on
the serial 0 and ping host work pretty well.

An OpenSBI patch was sent to drop the special "qemu/sifive_u" platform
support in OpenSBI. It will be applied after this QEMU series is merged.
http://lists.infradead.org/pipermail/opensbi/2019-August/000335.html

Changes in v3:
- changed to use macros for management and compute cpu count
- use management cpu count + 1 for the min_cpus
- update IRQ numbers of both UARTs to match hardware as well

Changes in v2:
- fixed the "interrupts-extended" property size
- update the file header to indicate at least 2 harts are created
- use create_unimplemented_device() to create the GEM management
  block instead of sifive_mmio_emulate()
- add "phy-handle" property to the ethernet node
- keep the PLIC compatible string unchanged as OpenSBI uses that
  for DT fix up
- drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place"
- new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"

Bin Meng (28):
  riscv: hw: Remove superfluous "linux,phandle" property
  riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
  riscv: Add a sifive_cpu.h to include both E and U cpu type defines
  riscv: hart: Extract hart realize to a separate routine
  riscv: hart: Support heterogeneous harts population
  riscv: sifive_u: Update hart configuration to reflect the real FU540
    SoC
  riscv: sifive_u: Set the minimum number of cpus to 2
  riscv: sifive_u: Update PLIC hart topology configuration string
  riscv: sifive_u: Update UART base addresses and IRQs
  riscv: sifive_u: Remove the unnecessary include of prci header
  riscv: sifive: Rename sifive_prci.{c,h} to sifive_e_prci.{c,h}
  riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
  riscv: sifive_e: prci: Update the PRCI register block size
  riscv: sifive: Implement PRCI model for FU540
  riscv: sifive_u: Generate hfclk and rtcclk nodes
  riscv: sifive_u: Add PRCI block to the SoC
  riscv: sifive_u: Change UART node name in device tree
  riscv: hw: Implement a model for SiFive FU540 OTP
  riscv: sifive_u: Instantiate OTP memory with a serial number
  riscv: roms: Update default bios for sifive_u machine
  riscv: sifive_u: Update UART and ethernet node clock properties
  riscv: sifive_u: Generate an aliases node in the device tree
  riscv: sifive_u: Fix broken GEM support
  riscv: sifive_u: Support loading initramfs
  riscv: hw: Remove not needed PLIC properties in device tree
  riscv: sifive_e: Drop sifive_mmio_emulate()
  riscv: virt: Change create_fdt() to return void
  riscv: sifive_u: Update model and compatible strings in device tree

 hw/riscv/Makefile.objs                             |   4 +-
 hw/riscv/riscv_hart.c                              |  75 ++++++--
 hw/riscv/sifive_e.c                                |  27 ++-
 hw/riscv/{sifive_prci.c => sifive_e_prci.c}        |  16 +-
 hw/riscv/sifive_u.c                                | 185 ++++++++++++++------
 hw/riscv/sifive_u_otp.c                            | 194 +++++++++++++++++++++
 hw/riscv/sifive_u_prci.c                           | 163 +++++++++++++++++
 hw/riscv/virt.c                                    |  40 ++---
 include/hw/riscv/sifive_cpu.h                      |  31 ++++
 include/hw/riscv/sifive_e.h                        |   7 +-
 .../hw/riscv/{sifive_prci.h => sifive_e_prci.h}    |  16 +-
 include/hw/riscv/sifive_u.h                        |  22 +--
 include/hw/riscv/sifive_u_otp.h                    |  90 ++++++++++
 include/hw/riscv/sifive_u_prci.h                   | 100 +++++++++++
 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin       | Bin 40968 -> 45064 bytes
 roms/Makefile                                      |   4 +-
 16 files changed, 830 insertions(+), 144 deletions(-)
 rename hw/riscv/{sifive_prci.c => sifive_e_prci.c} (88%)
 create mode 100644 hw/riscv/sifive_u_otp.c
 create mode 100644 hw/riscv/sifive_u_prci.c
 create mode 100644 include/hw/riscv/sifive_cpu.h
 rename include/hw/riscv/{sifive_prci.h => sifive_e_prci.h} (80%)
 create mode 100644 include/hw/riscv/sifive_u_otp.h
 create mode 100644 include/hw/riscv/sifive_u_prci.h

-- 
2.7.4

On Sun, Aug 11, 2019 at 4:07 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> As of today, the QEMU 'sifive_u' machine is a special target that does
> not boot the upstream OpenSBI/U-Boot firmware images built for the real
> SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
> "qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced
> in the OpenSBI doc as its payload, but that does not boot at all due
> to various issues in current QEMU 'sifive_u' machine codes.
>
> This series aims to improve the emulation fidelity of sifive_u machine,
> so that the upstream OpenSBI, U-Boot and kernel images built for the
> SiFive HiFive Unleashed board can be used out of the box without any
> special hack.
>
> The major changes include:
> - Heterogeneous harts creation supported, so that we can create a CPU
>   that exactly mirrors the real hardware: 1 E51 + 4 U54.
> - Implemented a PRCI model for FU540
> - Implemented an OTP model for FU540, primarily used for storing serial
>   number of the board
> - Fixed GEM support that was seriously broken on sifive_u
> - Synced device tree with upstream Linux kernel on sifive_u
> - Adding initramfs loading support on sifive_u
>
> OpenSBI v0.4 image built for sifive/fu540 is included as the default
> bios image for 'sifive_u' machine.
>
> The series is tested against OpenSBI v0.4 image for sifive/fu540
> paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig,
> and Linux kernel v5.3-rc3 image with the following patch:
>
> macb: Update compatibility string for SiFive FU540-C000
> https://patchwork.kernel.org/patch/11050003/
>
> OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well.
> Boot Linux 64-bit defconfig image, verified that system console on
> the serial 0 and ping host work pretty well.
>
> An OpenSBI patch was sent to drop the special "qemu/sifive_u" platform
> support in OpenSBI. It will be applied after this QEMU series is merged.
> http://lists.infradead.org/pipermail/opensbi/2019-August/000335.html
>
> Changes in v3:
> - changed to use macros for management and compute cpu count
> - use management cpu count + 1 for the min_cpus
> - update IRQ numbers of both UARTs to match hardware as well
>
> Changes in v2:
> - fixed the "interrupts-extended" property size
> - update the file header to indicate at least 2 harts are created
> - use create_unimplemented_device() to create the GEM management
>   block instead of sifive_mmio_emulate()
> - add "phy-handle" property to the ethernet node
> - keep the PLIC compatible string unchanged as OpenSBI uses that
>   for DT fix up
> - drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place"
> - new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"
>
> Bin Meng (28):
>   riscv: hw: Remove superfluous "linux,phandle" property
>   riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
>   riscv: Add a sifive_cpu.h to include both E and U cpu type defines
>   riscv: hart: Extract hart realize to a separate routine
>   riscv: hart: Support heterogeneous harts population
>   riscv: sifive_u: Update hart configuration to reflect the real FU540
>     SoC
>   riscv: sifive_u: Set the minimum number of cpus to 2
>   riscv: sifive_u: Update PLIC hart topology configuration string
>   riscv: sifive_u: Update UART base addresses and IRQs
>   riscv: sifive_u: Remove the unnecessary include of prci header
>   riscv: sifive: Rename sifive_prci.{c,h} to sifive_e_prci.{c,h}
>   riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
>   riscv: sifive_e: prci: Update the PRCI register block size
>   riscv: sifive: Implement PRCI model for FU540
>   riscv: sifive_u: Generate hfclk and rtcclk nodes
>   riscv: sifive_u: Add PRCI block to the SoC
>   riscv: sifive_u: Change UART node name in device tree
>   riscv: hw: Implement a model for SiFive FU540 OTP
>   riscv: sifive_u: Instantiate OTP memory with a serial number
>   riscv: roms: Update default bios for sifive_u machine
>   riscv: sifive_u: Update UART and ethernet node clock properties
>   riscv: sifive_u: Generate an aliases node in the device tree
>   riscv: sifive_u: Fix broken GEM support
>   riscv: sifive_u: Support loading initramfs
>   riscv: hw: Remove not needed PLIC properties in device tree
>   riscv: sifive_e: Drop sifive_mmio_emulate()
>   riscv: virt: Change create_fdt() to return void
>   riscv: sifive_u: Update model and compatible strings in device tree
>

I have no idea on why patch [20/28] and [26/28] failed to arrive on
the mailing list. The "git send-email" logs said OK when these two
patches were sent. In v2, these 2 patches are missing on patchwork,
and unfortunately this is the same situation for v3.

Attached these 2 patches.

Regards,
Bin
From e8bb57b3423b096f1efc851e0361232fde205f09 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Sat, 3 Aug 2019 13:48:24 +0800
Subject: [PATCH v3 20/28] riscv: roms: Update default bios for sifive_u
 machine

With the support of heterogeneous harts and PRCI model, it's now
possible to use the opensbi image built for the real hardware.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---
This patch should be applied after http://patchwork.ozlabs.org/patch/1141443/

Changes in v3: None
Changes in v2: None

 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin 40968 -> 45064 bytes
 roms/Makefile                                |   4 ++--
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
index 5d7a1ef6818994bac4a36818ad36043b592ce309..f29b3bed6fa8b57a735436d9c684740aa0a6bb16 100755
GIT binary patch
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diff --git a/roms/Makefile b/roms/Makefile
index 775c963..6cf07d3 100644
--- a/roms/Makefile
+++ b/roms/Makefile
@@ -182,8 +182,8 @@ opensbi64-virt:
 opensbi64-sifive_u:
 	$(MAKE) -C opensbi \
 		CROSS_COMPILE=$(riscv64_cross_prefix) \
-		PLATFORM="qemu/sifive_u"
-	cp opensbi/build/platform/qemu/sifive_u/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
+		PLATFORM="sifive/fu540"
+	cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
 
 clean:
 	rm -rf seabios/.config seabios/out seabios/builds
-- 
2.7.4

From b611512239ea23629d89bbcdf12fe8ee6a0459c1 Mon Sep 17 00:00:00 2001
From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 7 Aug 2019 14:56:09 +0800
Subject: [PATCH v3 26/28] riscv: sifive_e: Drop sifive_mmio_emulate()

Use create_unimplemented_device() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v3: None
Changes in v2:
- drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common place"
- new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"

 hw/riscv/sifive_e.c | 23 ++++++++---------------
 1 file changed, 8 insertions(+), 15 deletions(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 2d67670..040d59f 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -37,6 +37,7 @@
 #include "hw/loader.h"
 #include "hw/sysbus.h"
 #include "hw/char/serial.h"
+#include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
@@ -74,14 +75,6 @@ static const struct MemmapEntry {
     [SIFIVE_E_DTIM] =     { 0x80000000,     0x4000 }
 };
 
-static void sifive_mmio_emulate(MemoryRegion *parent, const char *name,
-                             uintptr_t offset, uintptr_t length)
-{
-    MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
-    memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal);
-    memory_region_add_subregion(parent, offset, mock_mmio);
-}
-
 static void riscv_sifive_e_init(MachineState *machine)
 {
     const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -172,7 +165,7 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
     sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
         memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
-    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
+    create_unimplemented_device("riscv.sifive.e.aon",
         memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
     sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
 
@@ -199,19 +192,19 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
 
     sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
-    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
+    create_unimplemented_device("riscv.sifive.e.qspi0",
         memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
-    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
+    create_unimplemented_device("riscv.sifive.e.pwm0",
         memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
     sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
-    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
+    create_unimplemented_device("riscv.sifive.e.qspi1",
         memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
-    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
+    create_unimplemented_device("riscv.sifive.e.pwm1",
         memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
-    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
+    create_unimplemented_device("riscv.sifive.e.qspi2",
         memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
-    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
+    create_unimplemented_device("riscv.sifive.e.pwm2",
         memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
 
     /* Flash memory */
-- 
2.7.4