[v1] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine

[Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string

Posted by Bin Meng 6 years, 6 months ago

With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.

Suggested-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 hw/riscv/sifive_u.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 206eccc..b235f29 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -372,10 +372,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
     plic_hart_config = g_malloc0(plic_hart_config_len);
     for (i = 0; i < ms->smp.cpus; i++) {
         if (i != 0) {
-            strncat(plic_hart_config, ",", plic_hart_config_len);
+            strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
+                    plic_hart_config_len);
+        } else {
+            strncat(plic_hart_config, "M", plic_hart_config_len);
         }
-        strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
-                plic_hart_config_len);
         plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
     }
 
-- 
2.7.4

Re: [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string

Posted by Alistair Francis 6 years, 6 months ago

On Mon, Aug 5, 2019 at 9:03 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> With heterogeneous harts config, the PLIC hart topology configuration
> string are "M,MS,.." because of the monitor hart #0.
>
> Suggested-by: Fabien Chouteau <chouteau@adacore.com>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/sifive_u.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 206eccc..b235f29 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -372,10 +372,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
>      plic_hart_config = g_malloc0(plic_hart_config_len);
>      for (i = 0; i < ms->smp.cpus; i++) {
>          if (i != 0) {
> -            strncat(plic_hart_config, ",", plic_hart_config_len);
> +            strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
> +                    plic_hart_config_len);
> +        } else {
> +            strncat(plic_hart_config, "M", plic_hart_config_len);
>          }
> -        strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
> -                plic_hart_config_len);
>          plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
>      }
>
> --
> 2.7.4
>
>