[v1] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine

[Qemu-devel] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2

Posted by Bin Meng 6 years, 6 months ago

It is not useful if we only have one management CPU.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 hw/riscv/sifive_u.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 08d406f..206eccc 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -428,6 +428,8 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
      * management CPU.
      */
     mc->max_cpus = 5;
+    /* It is not useful if we only have one management CPU */
+    mc->min_cpus = 2;
 }
 
 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
-- 
2.7.4

Re: [Qemu-devel] [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2

Posted by Jonathan Behrens 6 years, 6 months ago

I'm not familiar with QEMU conventions on this, but would it make sense to
require having exactly 5 CPUs to match the real board?

Jonathan


On Mon, Aug 5, 2019 at 12:05 PM Bin Meng <bmeng.cn@gmail.com> wrote:

> It is not useful if we only have one management CPU.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  hw/riscv/sifive_u.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 08d406f..206eccc 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -428,6 +428,8 @@ static void riscv_sifive_u_machine_init(MachineClass
> *mc)
>       * management CPU.
>       */
>      mc->max_cpus = 5;
> +    /* It is not useful if we only have one management CPU */
> +    mc->min_cpus = 2;
>  }
>
>  DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
> --
> 2.7.4
>
>
>

Re: [Qemu-devel] [Qemu-riscv] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2

Posted by Alistair Francis 6 years, 6 months ago

On Mon, Aug 5, 2019 at 9:42 AM Jonathan Behrens <fintelia@gmail.com> wrote:
>
> I'm not familiar with QEMU conventions on this, but would it make sense to
> require having exactly 5 CPUs to match the real board?

SMP can sometimes cause failures, so I think it makes some sense to
keep the default low.

Alistair

>
> Jonathan
>
>
> On Mon, Aug 5, 2019 at 12:05 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> > It is not useful if we only have one management CPU.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> >  hw/riscv/sifive_u.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> > index 08d406f..206eccc 100644
> > --- a/hw/riscv/sifive_u.c
> > +++ b/hw/riscv/sifive_u.c
> > @@ -428,6 +428,8 @@ static void riscv_sifive_u_machine_init(MachineClass
> > *mc)
> >       * management CPU.
> >       */
> >      mc->max_cpus = 5;
> > +    /* It is not useful if we only have one management CPU */
> > +    mc->min_cpus = 2;
> >  }
> >
> >  DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
> > --
> > 2.7.4
> >
> >
> >