[Qemu-devel] [PATCH RFC] i386: Add new Hygon 'Dhyana' and 'Dhyana-IBPB' CPU models

Pu Wen posted 1 patch 1 week ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/1555072669-20441-1-git-send-email-puwen@hygon.cn
hw/i386/pc.c      |  6 ++++
target/i386/cpu.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h |  2 ++
3 files changed, 106 insertions(+)

[Qemu-devel] [PATCH RFC] i386: Add new Hygon 'Dhyana' and 'Dhyana-IBPB' CPU models

Posted by Pu Wen 1 week ago
Add two new base CPU models called 'Dhyana' and 'Dhyana-IBPB' to model
processors from Hygon Dhyana (family 18h), which derived from AMD EPYC
(family 17h). 'Dhyana-IBPB' is a copy of the 'Dhyana' CPU model with
just CPUID_8000_0008_EBX_IBPB added.

The following features bits have been removed compare to AMD EPYC:
aes, pclmulqdq, sha_ni

The Hygon Dhyana support to KVM in Linux is already accepted upstream[1].
So add Hygon Dhyana support to Qemu is necessary to create Hygon's own
CPU models.

Reference:
[1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87

Signed-off-by: Pu Wen <puwen@hygon.cn>
---
 hw/i386/pc.c      |  6 ++++
 target/i386/cpu.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 target/i386/cpu.h |  2 ++
 3 files changed, 106 insertions(+)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index f2c15bf..7e59f50 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -128,6 +128,10 @@ GlobalProperty pc_compat_3_1[] = {
     { "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
     { "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
     { "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
+    { "Dhyana" "-" TYPE_X86_CPU, "npt", "off" },
+    { "Dhyana" "-" TYPE_X86_CPU, "nrip-save", "off" },
+    { "Dhyana-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
+    { "Dhyana-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
     { "Skylake-Client" "-" TYPE_X86_CPU,      "mpx", "on" },
     { "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
     { "Skylake-Server" "-" TYPE_X86_CPU,      "mpx", "on" },
@@ -152,6 +156,8 @@ GlobalProperty pc_compat_2_12[] = {
     { TYPE_X86_CPU, "topoext", "off" },
     { "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
     { "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
+    { "Dhyana-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
+    { "Dhyana-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
 };
 const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
 
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d6bb57d..9a46401 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2934,6 +2934,104 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .model_id = "AMD EPYC Processor (with IBPB)",
         .cache_info = &epyc_cache_info,
     },
+    {
+        .name = "Dhyana",
+        .level = 0xd,
+        .vendor = CPUID_VENDOR_HYGON,
+        .family = 24,
+        .model = 0,
+        .stepping = 1,
+        .features[FEAT_1_EDX] =
+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
+            CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
+            CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
+            CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
+            CPUID_VME | CPUID_FP87,
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+            CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
+            CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+            CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
+            CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
+            CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
+            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+            CPUID_EXT3_TOPOEXT,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
+            CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
+            CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
+        /*
+         * Missing: XSAVES (not supported by some Linux versions,
+         * including v4.1 to v4.12).
+         * KVM doesn't yet expose any XSAVES state save component.
+         */
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+            CPUID_XSAVE_XGETBV1,
+        .features[FEAT_6_EAX] =
+            CPUID_6_EAX_ARAT,
+        .features[FEAT_SVM] =
+            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
+        .xlevel = 0x8000001E,
+        .model_id = "Hygon Dhyana Processor",
+        .cache_info = &epyc_cache_info,
+    },
+    {
+        .name = "Dhyana-IBPB",
+        .level = 0xd,
+        .vendor = CPUID_VENDOR_HYGON,
+        .family = 24,
+        .model = 0,
+        .stepping = 1,
+        .features[FEAT_1_EDX] =
+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
+            CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
+            CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
+            CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
+            CPUID_VME | CPUID_FP87,
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+            CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
+            CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+            CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
+            CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
+            CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
+            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+            CPUID_EXT3_TOPOEXT,
+        .features[FEAT_8000_0008_EBX] =
+            CPUID_8000_0008_EBX_IBPB,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
+            CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
+            CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
+        /*
+         * Missing: XSAVES (not supported by some Linux versions,
+         * including v4.1 to v4.12).
+         * KVM doesn't yet expose any XSAVES state save component.
+         */
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+            CPUID_XSAVE_XGETBV1,
+        .features[FEAT_6_EAX] =
+            CPUID_6_EAX_ARAT,
+        .features[FEAT_SVM] =
+            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
+        .xlevel = 0x8000001E,
+        .model_id = "Hygon Dhyana Processor (with IBPB)",
+        .cache_info = &epyc_cache_info,
+    },
 };
 
 typedef struct PropValue {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 83fb522..553dbe7 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -726,6 +726,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
 
 #define CPUID_VENDOR_VIA   "CentaurHauls"
 
+#define CPUID_VENDOR_HYGON    "HygonGenuine"
+
 #define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
 #define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
 
-- 
2.7.4


Re: [Qemu-devel] [PATCH RFC] i386: Add new Hygon 'Dhyana' and 'Dhyana-IBPB' CPU models

Posted by Daniel P. Berrangé 1 week ago
On Fri, Apr 12, 2019 at 08:37:49PM +0800, Pu Wen wrote:
> Add two new base CPU models called 'Dhyana' and 'Dhyana-IBPB' to model
> processors from Hygon Dhyana (family 18h), which derived from AMD EPYC
> (family 17h). 'Dhyana-IBPB' is a copy of the 'Dhyana' CPU model with
> just CPUID_8000_0008_EBX_IBPB added.

Do we really need to support both CPU variants ?

The IBPB feature is the Spectre fix which dates from January 2018.
Having both made (limited) sense for EPYC as EPYC CPUs existed
already, so there would be a mix of EPYC CPUs with and without the
microcode that adds IBPB.

The Google results I see suggest that Dhyana CPUs started to become
available in July 2018, so surely they would come with microcode
that has the IBPB right from day 1 ?

Am I missing anything that means there will be a compelling need
to support Dhyana /without/ IBPB ?

If not, then we only need 1 CPU model and that would include IBPB.

Regards,
Daniel
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Re: [Qemu-devel] [PATCH RFC] i386: Add new Hygon 'Dhyana' and 'Dhyana-IBPB' CPU models

Posted by Pu Wen 1 week ago
On 2019/4/12 21:25, Daniel P. Berrangé wrote:
> On Fri, Apr 12, 2019 at 08:37:49PM +0800, Pu Wen wrote:
>> Add two new base CPU models called 'Dhyana' and 'Dhyana-IBPB' to model
>> processors from Hygon Dhyana (family 18h), which derived from AMD EPYC
>> (family 17h). 'Dhyana-IBPB' is a copy of the 'Dhyana' CPU model with
>> just CPUID_8000_0008_EBX_IBPB added.
...
> The Google results I see suggest that Dhyana CPUs started to become
> available in July 2018, so surely they would come with microcode
> that has the IBPB right from day 1 ?

Yes, you are right. Dhyana CPUs already have the IBPB feature.

> Am I missing anything that means there will be a compelling need
> to support Dhyana /without/ IBPB ?
> 
> If not, then we only need 1 CPU model and that would include IBPB.

Okay, will only keep one CPU model which include IBPB by using the name 
'Dhyana'.

Thx.

-- 
Regards,
Pu Wen

Re: [Qemu-devel] [PATCH RFC] i386: Add new Hygon 'Dhyana' and 'Dhyana-IBPB' CPU models

Posted by Paolo Bonzini 1 week ago
On 12/04/19 15:24, Daniel P. Berrangé wrote:
>> Add two new base CPU models called 'Dhyana' and 'Dhyana-IBPB' to model
>> processors from Hygon Dhyana (family 18h), which derived from AMD EPYC
>> (family 17h). 'Dhyana-IBPB' is a copy of the 'Dhyana' CPU model with
>> just CPUID_8000_0008_EBX_IBPB added.
> 
> Do we really need to support both CPU variants ?

Also, I think the compatibility properties are not needed for Dhyana chips.

Paolo

Re: [Qemu-devel] [PATCH RFC] i386: Add new Hygon 'Dhyana' and 'Dhyana-IBPB' CPU models

Posted by Pu Wen 1 week ago
On 2019/4/12 22:45, Paolo Bonzini wrote:
> On 12/04/19 15:24, Daniel P. Berrangé wrote:
>>> Add two new base CPU models called 'Dhyana' and 'Dhyana-IBPB' to model
>>> processors from Hygon Dhyana (family 18h), which derived from AMD EPYC
>>> (family 17h). 'Dhyana-IBPB' is a copy of the 'Dhyana' CPU model with
>>> just CPUID_8000_0008_EBX_IBPB added.
>>
>> Do we really need to support both CPU variants ?
> 
> Also, I think the compatibility properties are not needed for Dhyana chips.
 
Will only keep one CPU model with IBPB feature by using the name 'Dhyana'.

Thx.

-- 
Regards,
Pu Wen