From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>

Add emulation of MMI instruction PEXEW. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
 target/mips/translate.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 01efcde..f55a0db 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24721,6 +24721,67 @@ static void gen_mmi_pexeh(DisasContext *ctx)
     }
 }
 
+/*
+ *  PEXEW rd, rt
+ *
+ *  Parallel Exchange Even Word
+ *
+ *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ *  +-----------+---------+---------+---------+---------+-----------+
+ *  |    MMI    |0 0 0 0 0|   rt    |   rd    |  PEXEW  |    MMI2   |
+ *  +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pexew(DisasContext *ctx)
+{
+    uint32_t pd, rt, rd;
+    uint32_t opcode;
+
+    opcode = ctx->opcode;
+
+    pd = extract32(opcode, 21, 5);
+    rt = extract32(opcode, 16, 5);
+    rd = extract32(opcode, 11, 5);
+
+    if (unlikely(pd != 0)) {
+        generate_exception_end(ctx, EXCP_RI);
+    } else if (rd == 0) {
+        /* nop */
+    } else if (rt == 0) {
+        tcg_gen_movi_i64(cpu_gpr[rd], 0);
+        tcg_gen_movi_i64(cpu_mmr[rd], 0);
+    } else {
+        TCGv_i64 t0 = tcg_temp_new();
+        TCGv_i64 t1 = tcg_temp_new();
+        TCGv_i64 t2 = tcg_temp_new();
+        uint64_t mask0 = (1ULL << 32) - 1;
+        uint64_t mask1 = mask0 << 32;
+
+        tcg_gen_movi_i64(t1, 0);
+        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+        tcg_gen_or_i64(t1, t0, t1);
+        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
+        tcg_gen_shri_i64(t0, t0, 64);
+        tcg_gen_or_i64(t1, t0, t1);
+        tcg_gen_mov_i64(t2, t1);
+
+        tcg_gen_mov_i64(cpu_gpr[rd], t2);
+
+        tcg_gen_movi_i64(t1, 0);
+        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask0);
+        tcg_gen_shli_i64(t0, t0, 64);
+        tcg_gen_or_i64(t1, t0, t1);
+        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+        tcg_gen_or_i64(t1, t0, t1);
+
+        tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+        tcg_temp_free(t0);
+        tcg_temp_free(t1);
+        tcg_temp_free(t2);
+    }
+}
+
 #endif
 
 
@@ -27744,7 +27805,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_2_PREVH:     /* TODO: MMI_OPC_2_PREVH */
     case MMI_OPC_2_PMULTH:    /* TODO: MMI_OPC_2_PMULTH */
     case MMI_OPC_2_PDIVBW:    /* TODO: MMI_OPC_2_PDIVBW */
-    case MMI_OPC_2_PEXEW:     /* TODO: MMI_OPC_2_PEXEW */
     case MMI_OPC_2_PROT3W:    /* TODO: MMI_OPC_2_PROT3W */
         generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
         break;
@@ -27754,6 +27814,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_2_PEXEH:
         gen_mmi_pexeh(ctx);
         break;
+    case MMI_OPC_2_PEXEW:
+        gen_mmi_pexew(ctx);
+        break;
     default:
         MIPS_INVAL("TX79 MMI class MMI2");
         generate_exception_end(ctx, EXCP_RI);
-- 
2.7.4

On 3/4/19 7:13 AM, Mateja Marjanovic wrote:
> +    } else {
> +        TCGv_i64 t0 = tcg_temp_new();
> +        TCGv_i64 t1 = tcg_temp_new();
> +        TCGv_i64 t2 = tcg_temp_new();
> +        uint64_t mask0 = (1ULL << 32) - 1;
> +        uint64_t mask1 = mask0 << 32;
> +
> +        tcg_gen_movi_i64(t1, 0);
> +        tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> +        tcg_gen_or_i64(t1, t0, t1);
> +        tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
> +        tcg_gen_shri_i64(t0, t0, 64);

This line should abort, since the shift count is out of range.
Are you testing with --enable-debug-tcg?

> +        tcg_gen_or_i64(t1, t0, t1);
> +        tcg_gen_mov_i64(t2, t1);

But again, this whole thing is two deposit operations:

    tcg_gen_mov_i64(t0, cpu_gpr[rt]);
    tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_mmr[rt], 0, 32);
    tcg_gen_deposit_i64(cpu_mmr[rd], cpu_mmr[rt], t0, 0, 32);


r~