From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>

Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
 target/mips/translate.c | 42 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 117a29c..124f766 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24454,6 +24454,44 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
     }
 }
 
+/*
+ *  PCPYUD rd, rs, rt
+ *
+ *    Parallel Copy Upper Doubleword
+ *
+ *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ *  +-----------+---------+---------+---------+---------+-----------+
+ *  |    MMI    |   rs    |   rt    |   rd    | PCPYUD  |    MMI3   |
+ *  +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyud(DisasContext *ctx)
+{
+    uint32_t rs, rt, rd;
+    uint32_t opcode;
+
+    opcode = ctx->opcode;
+
+    rs = extract32(opcode, 21, 5);
+    rt = extract32(opcode, 16, 5);
+    rd = extract32(opcode, 11, 5);
+
+    if (rd == 0) {
+        /* nop */
+    } else if ((rt == 0) && (rs == 0)) {
+        tcg_gen_movi_i64(cpu_gpr[rt], 0);
+        tcg_gen_movi_i64(cpu_mmr[rt], 0);
+    } else if (rt == 0) {
+        tcg_gen_movi_i64(cpu_mmr[rd], 0);
+        tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+    } else if (rs == 0) {
+        tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+        tcg_gen_movi_i64(cpu_gpr[rd], 0);
+    } else {
+        tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+        tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+    }
+}
+
 #endif
 
 
@@ -27504,7 +27542,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_3_PINTEH:     /* TODO: MMI_OPC_3_PINTEH */
     case MMI_OPC_3_PMULTUW:    /* TODO: MMI_OPC_3_PMULTUW */
     case MMI_OPC_3_PDIVUW:     /* TODO: MMI_OPC_3_PDIVUW */
-    case MMI_OPC_3_PCPYUD:     /* TODO: MMI_OPC_3_PCPYUD */
     case MMI_OPC_3_POR:        /* TODO: MMI_OPC_3_POR */
     case MMI_OPC_3_PNOR:       /* TODO: MMI_OPC_3_PNOR */
     case MMI_OPC_3_PEXCH:      /* TODO: MMI_OPC_3_PEXCH */
@@ -27514,6 +27551,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_3_PCPYH:
         gen_mmi_pcpyh(ctx);
         break;
+    case MMI_OPC_3_PCPYUD:
+        gen_mmi_pcpyud(ctx);
+        break;
     default:
         MIPS_INVAL("TX79 MMI class MMI3");
         generate_exception_end(ctx, EXCP_RI);
-- 
2.7.4

On 2/25/19 8:10 AM, Mateja Marjanovic wrote:
> +    if (rd == 0) {
> +        /* nop */
> +    } else if ((rt == 0) && (rs == 0)) {
> +        tcg_gen_movi_i64(cpu_gpr[rt], 0);
> +        tcg_gen_movi_i64(cpu_mmr[rt], 0);
> +    } else if (rt == 0) {
> +        tcg_gen_movi_i64(cpu_mmr[rd], 0);
> +        tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
> +    } else if (rs == 0) {
> +        tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
> +        tcg_gen_movi_i64(cpu_gpr[rd], 0);
> +    } else {
> +        tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
> +        tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
> +    }

Same as patch 2.  You may have to invent gen_load_mmr.


r~