[Qemu-devel] [PATCH 6/8] target/mips: Add field and R/W access to ITU control register ICR0

Aleksandar Markovic posted 8 patches 7 years, 1 month ago
Maintainers: Aleksandar Markovic <amarkovic@wavecomp.com>, Stefan Markovic <smarkovic@wavecomp.com>, Aurelien Jarno <aurelien@aurel32.net>, Aleksandar Rikalo <arikalo@wavecomp.com>
[Qemu-devel] [PATCH 6/8] target/mips: Add field and R/W access to ITU control register ICR0
Posted by Aleksandar Markovic 7 years, 1 month ago
From: Yongbok Kim <yongbok.kim@mips.com>

Add field and R/W access to ITU control register ICR0.

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 hw/misc/mips_itu.c         | 22 +++++++++++++++++++++-
 include/hw/misc/mips_itu.h |  4 ++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index 43bbec4..4801958 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -55,9 +55,17 @@ typedef enum ITCView {
     ITCVIEW_EF_SYNC = 2,
     ITCVIEW_EF_TRY  = 3,
     ITCVIEW_PV_SYNC = 4,
-    ITCVIEW_PV_TRY  = 5
+    ITCVIEW_PV_TRY  = 5,
+    ITCVIEW_PV_ICR0 = 15,
 } ITCView;
 
+#define ITC_ICR0_CELL_NUM        16
+#define ITC_ICR0_BLK_GRAIN       8
+#define ITC_ICR0_BLK_GRAIN_MASK  0x7
+#define ITC_ICR0_ERR_AXI         2
+#define ITC_ICR0_ERR_PARITY      1
+#define ITC_ICR0_ERR_EXEC        0
+
 MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
 {
     return &itu->tag_io;
@@ -382,6 +390,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
     case ITCVIEW_PV_TRY:
         ret = view_pv_try_read(cell);
         break;
+    case ITCVIEW_PV_ICR0:
+        ret = s->icr0;
+        break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "itc_storage_read: Bad ITC View %d\n", (int)view);
@@ -417,6 +428,15 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
     case ITCVIEW_PV_TRY:
         view_pv_try_write(cell);
         break;
+    case ITCVIEW_PV_ICR0:
+        if (data & 0x7) {
+            /* clear ERROR bits */
+            s->icr0 &= ~(data & 0x7);
+        }
+        /* set BLK_GRAIN */
+        s->icr0 &= ~0x700;
+        s->icr0 |= data & 0x700;
+        break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "itc_storage_write: Bad ITC View %d\n", (int)view);
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 030eb4a..45a0c51 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -66,6 +66,10 @@ typedef struct MIPSITUState {
     /* ITC Configuration Tags */
     uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
     MemoryRegion tag_io;
+
+    /* ITU Control Register */
+    uint64_t icr0;
+
 } MIPSITUState;
 
 /* Get ITC Configuration Tag memory region. */
-- 
2.7.4


Re: [Qemu-devel] [PATCH 6/8] target/mips: Add field and R/W access to ITU control register ICR0
Posted by Stefan Markovic 7 years ago
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Add field and R/W access to ITU control register ICR0.
>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
>   hw/misc/mips_itu.c         | 22 +++++++++++++++++++++-
>   include/hw/misc/mips_itu.h |  4 ++++
>   2 files changed, 25 insertions(+), 1 deletion(-)


Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>


> diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
> index 43bbec4..4801958 100644
> --- a/hw/misc/mips_itu.c
> +++ b/hw/misc/mips_itu.c
> @@ -55,9 +55,17 @@ typedef enum ITCView {
>       ITCVIEW_EF_SYNC = 2,
>       ITCVIEW_EF_TRY  = 3,
>       ITCVIEW_PV_SYNC = 4,
> -    ITCVIEW_PV_TRY  = 5
> +    ITCVIEW_PV_TRY  = 5,
> +    ITCVIEW_PV_ICR0 = 15,
>   } ITCView;
>   
> +#define ITC_ICR0_CELL_NUM        16
> +#define ITC_ICR0_BLK_GRAIN       8
> +#define ITC_ICR0_BLK_GRAIN_MASK  0x7
> +#define ITC_ICR0_ERR_AXI         2
> +#define ITC_ICR0_ERR_PARITY      1
> +#define ITC_ICR0_ERR_EXEC        0
> +
>   MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
>   {
>       return &itu->tag_io;
> @@ -382,6 +390,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
>       case ITCVIEW_PV_TRY:
>           ret = view_pv_try_read(cell);
>           break;
> +    case ITCVIEW_PV_ICR0:
> +        ret = s->icr0;
> +        break;
>       default:
>           qemu_log_mask(LOG_GUEST_ERROR,
>                         "itc_storage_read: Bad ITC View %d\n", (int)view);
> @@ -417,6 +428,15 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
>       case ITCVIEW_PV_TRY:
>           view_pv_try_write(cell);
>           break;
> +    case ITCVIEW_PV_ICR0:
> +        if (data & 0x7) {
> +            /* clear ERROR bits */
> +            s->icr0 &= ~(data & 0x7);
> +        }
> +        /* set BLK_GRAIN */
> +        s->icr0 &= ~0x700;
> +        s->icr0 |= data & 0x700;
> +        break;
>       default:
>           qemu_log_mask(LOG_GUEST_ERROR,
>                         "itc_storage_write: Bad ITC View %d\n", (int)view);
> diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
> index 030eb4a..45a0c51 100644
> --- a/include/hw/misc/mips_itu.h
> +++ b/include/hw/misc/mips_itu.h
> @@ -66,6 +66,10 @@ typedef struct MIPSITUState {
>       /* ITC Configuration Tags */
>       uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
>       MemoryRegion tag_io;
> +
> +    /* ITU Control Register */
> +    uint64_t icr0;
> +
>   } MIPSITUState;
>   
>   /* Get ITC Configuration Tag memory region. */