MIPS queue for November 2018 (for QEMU 3.1-rc2)

[Qemu-devel] [PULL 06/11] target/mips: Guard check_insn with INSN_R5900 check

Posted by Aleksandar Markovic 6 years, 11 months ago

From: Fredrik Noring <noring@nocrew.org>

Explicitely mark handling of PREF instruction for R5900 as
treating the same as NOP.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
 target/mips/translate.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c79da3c..714f2e6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28357,9 +28357,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case OPC_PREF:
         check_insn_opc_removed(ctx, ISA_MIPS32R6);
-        check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
-                   INSN_R5900);
-        /* Treat as NOP. */
+        if (ctx->insn_flags & INSN_R5900) {
+            /* Treat as NOP. */
+        } else {
+            check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+            /* Treat as NOP. */
+        }
         break;
 
     /* Floating point (COP1). */
-- 
2.7.4