[v8] target/mips: Add limited support for Ingenic's MXU ASE

[Qemu-devel] [PATCH v8 07/20] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2'

Posted by Aleksandar Markovic 7 years ago

From: Craig Janeczek <jancraig@amazon.com>

Add bit encoding for MXU accumulate add/subtract 2-bit pattern
'aptn2'.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7130729..7116697 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23981,6 +23981,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
 #define MXU_APTN1_A    0
 #define MXU_APTN1_S    1
 
+/* MXU accumulate add/subtract 2-bit pattern 'aptn2' */
+#define MXU_APTN2_AA    0
+#define MXU_APTN2_AS    1
+#define MXU_APTN2_SA    2
+#define MXU_APTN2_SS    3
+
 
 /*
  *
-- 
2.7.4