From: Aleksandar Markovic <amarkovic@wavecomp.com>

Provide the placeholder and add the invocation logic for MXU
decoding engine.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index fefe9ac..128cabe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23844,6 +23844,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
+static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
+{
+    MIPS_INVAL("decode_opc_mxu");
+    generate_exception_end(ctx, EXCP_RI);
+}
+
 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
 {
     int rs, rt, rd;
@@ -26087,6 +26093,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     case OPC_SPECIAL2:
         if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
             decode_tx79_mmi(env, ctx);
+        } else if (ctx->insn_flags & ASE_MXU) {
+            decode_opc_mxu(env, ctx);
         } else {
             decode_opc_special2_legacy(env, ctx);
         }
-- 
2.7.4

On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Provide the placeholder and add the invocation logic for MXU
> decoding engine.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
>   target/mips/translate.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index fefe9ac..128cabe 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -23844,6 +23844,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
>       }
>   }
>   
> +static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
> +{
> +    MIPS_INVAL("decode_opc_mxu");
> +    generate_exception_end(ctx, EXCP_RI);
> +}
> +
>   static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
>   {
>       int rs, rt, rd;
> @@ -26087,6 +26093,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
>       case OPC_SPECIAL2:
>           if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
>               decode_tx79_mmi(env, ctx);
> +        } else if (ctx->insn_flags & ASE_MXU) {
> +            decode_opc_mxu(env, ctx);


Is the best way to implement this to include processing of MUL, CLZ, 
CLO, SDDP instructions into decode_opc_mxu as their encodings aren't 
overlaid by MXU instructions

considering MIPS SPECIAL2 instruction pool and MXU Instruction Set?


>           } else {
>               decode_opc_special2_legacy(env, ctx);
>           }

> Is the best way to implement this to include processing of MUL, CLZ,
> CLO, SDBBP instructions into decode_opc_mxu as their encodings aren't
> overlaid by MXU instructions considering MIPS SPECIAL2 instruction
> pool and MXU Instruction Set?

The problem is that we don't have the documentation for Ingenic's base
instruction set. My understanding is that Craig established necessity of
including non-MXU MUL into decode_opc_mxu() by experimentation,
or by looking at Ingenic's toolchain source code.

Note that CLZ, CLO, SDBBP are moved from SPECIAL2 to another
place in opcode space in MIPS R6.

Craig, can you offer any insight on CLZ, CLO, SDBBP in Ingenic's base
instruction set? They are in SPECIAL2 opcode space for MIPS pre-R6.

Worse come to worst, I recommend adding "TODO" comment to an
appropriate place in decode_opc_mxu(), and go forward without handling
CLZ, CLO, SDBBP - given that all changes in this series are just the first
phase of implementing MXU support - they won't affect any production
code at this moment.

I appreciate your review,
Aleksandar

> Subject: Re: [PATCH v7 04/20] target/mips: Add and integrate MXU decoding engine > placeholder
> 
> > Is the best way to implement this to include processing of MUL, CLZ,
> > CLO, SDBBP instructions into decode_opc_mxu as their encodings aren't
> > overlaid by MXU instructions considering MIPS SPECIAL2 instruction
> > pool and MXU Instruction Set?
> 
> The problem is that we don't have the documentation for Ingenic's base
> instruction set. My understanding is that Craig established necessity of
> including non-MXU MUL into decode_opc_mxu() by experimentation,
> or by looking at Ingenic's toolchain source code.
> 
> Note that CLZ, CLO, SDBBP are moved from SPECIAL2 to another
> place in opcode space in MIPS R6.
> 
> Craig, can you offer any insight on CLZ, CLO, SDBBP in Ingenic's base
> instruction set? They are in SPECIAL2 opcode space for MIPS pre-R6.
> 
> Worse come to worst, I recommend adding "TODO" comment to an
> appropriate place in decode_opc_mxu(), and go forward without handling
> CLZ, CLO, SDBBP - given that all changes in this series are just the first
> phase of implementing MXU support - they won't affect any production
> code at this moment.
> 

I think this comment should be added to the decode_opc_mxu(), within patch 11:

    /*
     * TODO: Investigate necessity of including handling of
     * CLZ, CLO, SDBB in this function, as they belong to
     * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs.
     */

Thanks,
Aleksandar

In that case, I guess this should be OK for now, as MXU support is 
initiated by Craig and this will be

an easy add-on when he provide necessary information.


Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>


On 28.10.18. 19:39, Aleksandar Markovic wrote:
>> Subject: Re: [PATCH v7 04/20] target/mips: Add and integrate MXU decoding engine > placeholder
>>
>>> Is the best way to implement this to include processing of MUL, CLZ,
>>> CLO, SDBBP instructions into decode_opc_mxu as their encodings aren't
>>> overlaid by MXU instructions considering MIPS SPECIAL2 instruction
>>> pool and MXU Instruction Set?
>> The problem is that we don't have the documentation for Ingenic's base
>> instruction set. My understanding is that Craig established necessity of
>> including non-MXU MUL into decode_opc_mxu() by experimentation,
>> or by looking at Ingenic's toolchain source code.
>>
>> Note that CLZ, CLO, SDBBP are moved from SPECIAL2 to another
>> place in opcode space in MIPS R6.
>>
>> Craig, can you offer any insight on CLZ, CLO, SDBBP in Ingenic's base
>> instruction set? They are in SPECIAL2 opcode space for MIPS pre-R6.
>>
>> Worse come to worst, I recommend adding "TODO" comment to an
>> appropriate place in decode_opc_mxu(), and go forward without handling
>> CLZ, CLO, SDBBP - given that all changes in this series are just the first
>> phase of implementing MXU support - they won't affect any production
>> code at this moment.
>>
> I think this comment should be added to the decode_opc_mxu(), within patch 11:
>
>      /*
>       * TODO: Investigate necessity of including handling of
>       * CLZ, CLO, SDBB in this function, as they belong to
>       * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs.
>       */
>
> Thanks,
> Aleksandar