From: Craig Janeczek <jancraig@amazon.com>

Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/mips-defs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 71ea4ef..4c624a4 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -67,6 +67,7 @@
 /*
  *   bits 56-63: vendor-specific ASEs
  */
+#define ASE_MXU           0x0100000000000000ULL
 
 /* MIPS CPU defines. */
 #define		CPU_MIPS1	(ISA_MIPS1)
-- 
2.7.4