On Fri, Oct 12, 2018 at 6:47 PM Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
>
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Add PWBase register (CP0 Register 5, Select 5).
>
> The PWBase register contains the Page Table Base virtual address.
>
> This register is required for the hardware page walker feature. It
> exists only if Config3 PW bit is set to 1.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/cpu.h | 1 +
> target/mips/machine.c | 5 +++--
> target/mips/translate.c | 31 +++++++++++++++++++++++++++++++
> 3 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 28af4d1..c8999a8 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -289,6 +289,7 @@ struct CPUMIPSState {
> #define CP0SC2_XR 56
> #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
> #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
> + target_ulong CP0_PWBase;
> int32_t CP0_Wired;
> int32_t CP0_SRSConf0_rw_bitmask;
> int32_t CP0_SRSConf0;
> diff --git a/target/mips/machine.c b/target/mips/machine.c
> index 5ba78ac..3592bb7 100644
> --- a/target/mips/machine.c
> +++ b/target/mips/machine.c
> @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
>
> const VMStateDescription vmstate_mips_cpu = {
> .name = "cpu",
> - .version_id = 11,
> - .minimum_version_id = 11,
> + .version_id = 12,
> + .minimum_version_id = 12,
> .post_load = cpu_post_load,
> .fields = (VMStateField[]) {
> /* Active TC */
> @@ -256,6 +256,7 @@ const VMStateDescription vmstate_mips_cpu = {
> VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
> VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
> VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
> + VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
> VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
> VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
> VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index ab16cdb..7af9a21 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1929,6 +1929,17 @@ static inline void check_xnp(DisasContext *ctx)
>
> /*
> * This code generates a "reserved instruction" exception if the
> + * Config3 PW bit is NOT set.
> + */
> +static inline void check_pw(DisasContext *ctx)
> +{
> + if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
> + generate_exception_end(ctx, EXCP_RI);
> + }
> +}
> +
> +/*
> + * This code generates a "reserved instruction" exception if the
> * Config3 MT bit is NOT set.
> */
> static inline void check_mt(DisasContext *ctx)
> @@ -5537,6 +5548,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> tcg_gen_ext32s_tl(arg, arg);
> rn = "SegCtl2";
> break;
> + case 5:
> + check_pw(ctx);
> + gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
> + rn = "PWBase";
> + break;
> default:
> goto cp0_unimplemented;
> }
> @@ -6238,6 +6254,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_segctl2(cpu_env, arg);
> rn = "SegCtl2";
> break;
> + case 5:
> + check_pw(ctx);
> + gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
> + rn = "PWBase";
> + break;
> default:
> goto cp0_unimplemented;
> }
> @@ -6948,6 +6969,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
> rn = "SegCtl2";
> break;
> + case 5:
> + check_pw(ctx);
> + tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
Shouldn't you use gen_mfc0_load64()?
> + rn = "PWBase";
> + break;
> default:
> goto cp0_unimplemented;
> }
> @@ -7631,6 +7657,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_helper_mtc0_segctl2(cpu_env, arg);
> rn = "SegCtl2";
> break;
> + case 5:
> + check_pw(ctx);
> + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
> + rn = "PWBase";
> + break;
> default:
> goto cp0_unimplemented;
> }
> --
> 2.7.4
>
>