[Qemu-devel] [PATCH v7 03/80] target/mips: Mark switch fallthroughs with interpretable comments

Aleksandar Markovic posted 80 patches 7 years, 3 months ago
There is a newer version of this series
[Qemu-devel] [PATCH v7 03/80] target/mips: Mark switch fallthroughs with interpretable comments
Posted by Aleksandar Markovic 7 years, 3 months ago
From: Aleksandar Markovic <amarkovic@wavecomp.com>

Mark switch fallthroughs with comments, in cases fallthroughs
are intentional.

The comments "/* fall through */" are interpreted by compilers and
other tools, and they will not issue warnings in such cases. For gcc,
the warning is turnend on by -Wimplicit-fallthrough. With this patch,
there will be no such warnings in target/mips directory. If such
warning appears in future, it should be checked if it is intentional,
and, if yes, marked with a comment similar to those from this patch.

The comment must be just before next "case", otherwise gcc won't
understand it.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
 target/mips/translate.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 051dda5..e32fd5f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -14255,8 +14255,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
         case SDP:
             check_insn(ctx, ISA_MIPS3);
             check_mips_64(ctx);
-            /* Fallthrough */
 #endif
+            /* fall through */
         case LWP:
         case SWP:
             gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@@ -14266,8 +14266,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
         case SDM:
             check_insn(ctx, ISA_MIPS3);
             check_mips_64(ctx);
-            /* Fallthrough */
 #endif
+            /* fall through */
         case LWM32:
         case SWM32:
             gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
@@ -20023,6 +20023,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         case OPC_MTHC1:
             check_cp1_enabled(ctx);
             check_insn(ctx, ISA_MIPS32R2);
+            /* fall through */
         case OPC_MFC1:
         case OPC_CFC1:
         case OPC_MTC1:
-- 
2.7.4


Re: [Qemu-devel] [PATCH v7 03/80] target/mips: Mark switch fallthroughs with interpretable comments
Posted by Philippe Mathieu-Daudé 7 years, 2 months ago
On 08/06/2018 01:59 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
> 
> Mark switch fallthroughs with comments, in cases fallthroughs
> are intentional.
> 
> The comments "/* fall through */" are interpreted by compilers and
> other tools, and they will not issue warnings in such cases. For gcc,
> the warning is turnend on by -Wimplicit-fallthrough. With this patch,
> there will be no such warnings in target/mips directory. If such
> warning appears in future, it should be checked if it is intentional,
> and, if yes, marked with a comment similar to those from this patch.
> 
> The comment must be just before next "case", otherwise gcc won't
> understand it.
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/mips/translate.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 051dda5..e32fd5f 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -14255,8 +14255,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
>          case SDP:
>              check_insn(ctx, ISA_MIPS3);
>              check_mips_64(ctx);
> -            /* Fallthrough */
>  #endif
> +            /* fall through */
>          case LWP:
>          case SWP:
>              gen_ldst_pair(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
> @@ -14266,8 +14266,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
>          case SDM:
>              check_insn(ctx, ISA_MIPS3);
>              check_mips_64(ctx);
> -            /* Fallthrough */
>  #endif
> +            /* fall through */
>          case LWM32:
>          case SWM32:
>              gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));
> @@ -20023,6 +20023,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
>          case OPC_MTHC1:
>              check_cp1_enabled(ctx);
>              check_insn(ctx, ISA_MIPS32R2);
> +            /* fall through */
>          case OPC_MFC1:
>          case OPC_CFC1:
>          case OPC_MTC1:
>