From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in ctx->insn_flags.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
target/mips/translate.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 227b2c0..c64efbe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16458,6 +16458,19 @@ enum {
NM_EVP = 0x01,
};
+
+/*
+ *
+ * nanoMIPS decoding engine
+ *
+ */
+
+static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ return 2;
+}
+
+
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
@@ -21262,6 +21275,9 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
insn_bytes = 4;
decode_opc(env, ctx);
+ } else if (ctx->insn_flags & ISA_NANOMIPS32) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_nanomips_opc(env, ctx);
} else if (ctx->insn_flags & ASE_MICROMIPS) {
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
insn_bytes = decode_micromips_opc(env, ctx);
--
2.7.4