On 07/19/2018 05:55 AM, Stefan Markovic wrote:
> From: James Hogan <james.hogan@mips.com>
>
> We shouldn't set the ISA bit in CP0_EPC for nanoMIPS.
>
> Signed-off-by: James Hogan <james.hogan@mips.com>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> ---
> target/mips/helper.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index dc8f2a5..fb47018 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -656,7 +656,8 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
> target_ulong bad_pc;
> target_ulong isa_mode;
>
> - isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
> + isa_mode = env->hflags & MIPS_HFLAG_M16 &&
> + !(env->insn_flags & ISA_NANOMIPS32);
Is there a compelling reason to have MIPS_HFLAG_M16 *set* for ISA_NANOMIPS?
This seems like the 6th or 7th patch that works around M16. If M16 were always
unset for nanomips, it would have avoided a lot of extra effort, it would seem.
In addition, looking at the fully patched tree and grepping for HFLAG_M16,
there appear to be further uses that have been missed for the extra NANOMIPS check.
r~