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[Qemu-devel] [PATCH v7 3/9] i386: Initialize cache information for EPYC family processors

Babu Moger posted 9 patches 7 years, 6 months ago
There is a newer version of this series
[Qemu-devel] [PATCH v7 3/9] i386: Initialize cache information for EPYC family processors
Posted by Babu Moger 7 years, 6 months ago 
Initialize pre-determined cache information for EPYC processors.

Signed-off-by: Babu Moger <babu.moger@amd.com>
Tested-by: Geoffrey McRae <geoff@hostfission.com>
---
 target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a518a0f..5d88363 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2302,6 +2302,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_6_EAX_ARAT,
         .xlevel = 0x8000000A,
         .model_id = "AMD EPYC Processor",
+        .cache_info.valid = 1,
+        .cache_info.l1d_cache = {
+            .type = DCACHE,
+            .level = 1,
+            .size = 32 * KiB,
+            .line_size = 64,
+            .associativity = 8,
+            .partitions = 1,
+            .sets = 64,
+            .lines_per_tag = 1,
+            .self_init = 1,
+            .no_invd_sharing = true,
+        },
+        .cache_info.l1i_cache = {
+            .type = ICACHE,
+            .level = 1,
+            .size = 64 * KiB,
+            .line_size = 64,
+            .associativity = 4,
+            .partitions = 1,
+            .sets = 256,
+            .lines_per_tag = 1,
+            .self_init = 1,
+            .no_invd_sharing = true,
+        },
+        .cache_info.l2_cache = {
+            .type = UNIFIED_CACHE,
+            .level = 2,
+            .size = 512 * KiB,
+            .line_size = 64,
+            .associativity = 8,
+            .partitions = 1,
+            .sets = 1024,
+            .lines_per_tag = 1,
+        },
+        .cache_info.l3_cache = {
+            .type = UNIFIED_CACHE,
+            .level = 3,
+            .size = 8 * MiB,
+            .line_size = 64,
+            .associativity = 16,
+            .partitions = 1,
+            .sets = 8192,
+            .lines_per_tag = 1,
+            .self_init = true,
+            .inclusive = true,
+            .complex_indexing = true,
+        },
     },
     {
         .name = "EPYC-IBPB",
@@ -2348,6 +2396,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_6_EAX_ARAT,
         .xlevel = 0x8000000A,
         .model_id = "AMD EPYC Processor (with IBPB)",
+        .cache_info.valid = 1,
+        .cache_info.l1d_cache = {
+            .type = DCACHE,
+            .level = 1,
+            .size = 32 * KiB,
+            .line_size = 64,
+            .associativity = 8,
+            .partitions = 1,
+            .sets = 64,
+            .lines_per_tag = 1,
+            .self_init = 1,
+            .no_invd_sharing = true,
+        },
+        .cache_info.l1i_cache = {
+            .type = ICACHE,
+            .level = 1,
+            .size = 64 * KiB,
+            .line_size = 64,
+            .associativity = 4,
+            .partitions = 1,
+            .sets = 256,
+            .lines_per_tag = 1,
+            .self_init = 1,
+            .no_invd_sharing = true,
+        },
+        .cache_info.l2_cache = {
+            .type = UNIFIED_CACHE,
+            .level = 2,
+            .size = 512 * KiB,
+            .line_size = 64,
+            .associativity = 8,
+            .partitions = 1,
+            .sets = 1024,
+            .lines_per_tag = 1,
+        },
+        .cache_info.l3_cache = {
+            .type = UNIFIED_CACHE,
+            .level = 3,
+            .size = 8 * MiB,
+            .line_size = 64,
+            .associativity = 16,
+            .partitions = 1,
+            .sets = 8192,
+            .lines_per_tag = 1,
+            .self_init = true,
+            .inclusive = true,
+            .complex_indexing = true,
+        },
     },
 };
 
-- 
2.7.4
Re: [Qemu-devel] [PATCH v7 3/9] i386: Initialize cache information for EPYC family processors
Posted by Eduardo Habkost 7 years, 5 months ago 
On Thu, Apr 26, 2018 at 11:26:43AM -0500, Babu Moger wrote:
> Initialize pre-determined cache information for EPYC processors.
> 
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> Tested-by: Geoffrey McRae <geoff@hostfission.com>

Assuming that the cache information below was validated by people
from AMD, patch looks good to me.

> ---
>  target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index a518a0f..5d88363 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2302,6 +2302,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              CPUID_6_EAX_ARAT,
>          .xlevel = 0x8000000A,
>          .model_id = "AMD EPYC Processor",
> +        .cache_info.valid = 1,
> +        .cache_info.l1d_cache = {
> +            .type = DCACHE,
> +            .level = 1,
> +            .size = 32 * KiB,
> +            .line_size = 64,
> +            .associativity = 8,
> +            .partitions = 1,
> +            .sets = 64,
> +            .lines_per_tag = 1,
> +            .self_init = 1,
> +            .no_invd_sharing = true,
> +        },
> +        .cache_info.l1i_cache = {
> +            .type = ICACHE,
> +            .level = 1,
> +            .size = 64 * KiB,
> +            .line_size = 64,
> +            .associativity = 4,
> +            .partitions = 1,
> +            .sets = 256,
> +            .lines_per_tag = 1,
> +            .self_init = 1,
> +            .no_invd_sharing = true,
> +        },
> +        .cache_info.l2_cache = {
> +            .type = UNIFIED_CACHE,
> +            .level = 2,
> +            .size = 512 * KiB,
> +            .line_size = 64,
> +            .associativity = 8,
> +            .partitions = 1,
> +            .sets = 1024,
> +            .lines_per_tag = 1,
> +        },
> +        .cache_info.l3_cache = {
> +            .type = UNIFIED_CACHE,
> +            .level = 3,
> +            .size = 8 * MiB,
> +            .line_size = 64,
> +            .associativity = 16,
> +            .partitions = 1,
> +            .sets = 8192,
> +            .lines_per_tag = 1,
> +            .self_init = true,
> +            .inclusive = true,
> +            .complex_indexing = true,
> +        },
>      },
>      {
>          .name = "EPYC-IBPB",
> @@ -2348,6 +2396,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              CPUID_6_EAX_ARAT,
>          .xlevel = 0x8000000A,
>          .model_id = "AMD EPYC Processor (with IBPB)",
> +        .cache_info.valid = 1,
> +        .cache_info.l1d_cache = {
> +            .type = DCACHE,
> +            .level = 1,
> +            .size = 32 * KiB,
> +            .line_size = 64,
> +            .associativity = 8,
> +            .partitions = 1,
> +            .sets = 64,
> +            .lines_per_tag = 1,
> +            .self_init = 1,
> +            .no_invd_sharing = true,
> +        },
> +        .cache_info.l1i_cache = {
> +            .type = ICACHE,
> +            .level = 1,
> +            .size = 64 * KiB,
> +            .line_size = 64,
> +            .associativity = 4,
> +            .partitions = 1,
> +            .sets = 256,
> +            .lines_per_tag = 1,
> +            .self_init = 1,
> +            .no_invd_sharing = true,
> +        },
> +        .cache_info.l2_cache = {
> +            .type = UNIFIED_CACHE,
> +            .level = 2,
> +            .size = 512 * KiB,
> +            .line_size = 64,
> +            .associativity = 8,
> +            .partitions = 1,
> +            .sets = 1024,
> +            .lines_per_tag = 1,
> +        },
> +        .cache_info.l3_cache = {
> +            .type = UNIFIED_CACHE,
> +            .level = 3,
> +            .size = 8 * MiB,
> +            .line_size = 64,
> +            .associativity = 16,
> +            .partitions = 1,
> +            .sets = 8192,
> +            .lines_per_tag = 1,
> +            .self_init = true,
> +            .inclusive = true,
> +            .complex_indexing = true,
> +        },
>      },
>  };
>  
> -- 
> 2.7.4
> 
> 

-- 
Eduardo

Patchew 2.1-devel-b67e4c2

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