[Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case

Michael Clark posted 35 patches 7 years, 9 months ago
[Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case
Posted by Michael Clark 7 years, 9 months ago
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.

It seems the RISC-V WARL behaviour is preferred to having to
trap overhead versus simply reading back the value and checking
if the write took (saves hundreds of cycles and more complex
trap handling code).

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 target/riscv/op_helper.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 7c6068b..101dac1 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -255,7 +255,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
     }
     case CSR_SATP: /* CSR_SPTBR */ {
         if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
-            goto do_illegal;
+            break;
         }
         if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val_to_write ^ env->sptbr))
         {
@@ -465,7 +465,10 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
         return env->scounteren;
     case CSR_SCAUSE:
         return env->scause;
-    case CSR_SPTBR:
+    case CSR_SATP: /* CSR_SPTBR */
+        if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+            return 0;
+        }
         if (env->priv_ver >= PRIV_VERSION_1_10_0) {
             return env->satp;
         } else {
-- 
2.7.0


Re: [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case
Posted by Alistair Francis 7 years, 9 months ago
On Wed, Apr 25, 2018 at 4:56 PM Michael Clark <mjc@sifive.com> wrote:

> satp is WARL so it should not trap on illegal writes, rather
> it can be hardwired to zero and silently ignore illegal writes.

> It seems the RISC-V WARL behaviour is preferred to having to
> trap overhead versus simply reading back the value and checking
> if the write took (saves hundreds of cycles and more complex
> trap handling code).

> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>   target/riscv/op_helper.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)

> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 7c6068b..101dac1 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -255,7 +255,7 @@ void csr_write_helper(CPURISCVState *env,
target_ulong val_to_write,
>       }
>       case CSR_SATP: /* CSR_SPTBR */ {
>           if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
> -            goto do_illegal;
> +            break;
>           }
>           if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val_to_write ^
env->sptbr))
>           {
> @@ -465,7 +465,10 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
>           return env->scounteren;
>       case CSR_SCAUSE:
>           return env->scause;
> -    case CSR_SPTBR:
> +    case CSR_SATP: /* CSR_SPTBR */
> +        if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
> +            return 0;
> +        }
>           if (env->priv_ver >= PRIV_VERSION_1_10_0) {
>               return env->satp;
>           } else {
> --
> 2.7.0