Signed-off-by: Emilio G. Cota <cota@braap.org>
---
 target/i386/translate.c | 2 +-
 target/m68k/translate.c | 2 +-
 tcg/README              | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/i386/translate.c b/target/i386/translate.c
index 0135415..2e923c0 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -113,7 +113,7 @@ typedef struct DisasContext {
     int rex_x, rex_b;
 #endif
     int vex_l;  /* vex vector length */
-    int vex_v;  /* vex vvvv register, without 1's compliment.  */
+    int vex_v;  /* vex vvvv register, without 1's complement.  */
     int ss32;   /* 32 bit stack segment */
     CCOp cc_op;  /* current CC operation */
     bool cc_op_dirty;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index dbb24f8..8f0b7c9 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -3974,7 +3974,7 @@ DISAS_INSN(bfext_reg)
     TCGv shift;
 
     /* In general, we're going to rotate the field so that it's at the
-       top of the word and then right-shift by the compliment of the
+       top of the word and then right-shift by the complement of the
        width to extend the field.  */
     if (ext & 0x20) {
         /* Variable width.  */
diff --git a/tcg/README b/tcg/README
index bb2ea51..8a8d7e2 100644
--- a/tcg/README
+++ b/tcg/README
@@ -553,7 +553,7 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
 * orc_vec   v0, v1, v2
 * not_vec   v0, v1
 
-  Similarly, logical operations with and without compliment.
+  Similarly, logical operations with and without complement.
   Note that VECE is unused.
 
 * shli_vec   v0, v1, i2
-- 
2.7.4