[ What is this all about? See this message:
  http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]

Merged the separate patchsets I sent in the last couple of weeks into
one set. This will be easier to merge since it will avoid potential
merge conflicts due to adding max_insns to dc->base.

Changes since sending the separate series for sh4/sparc/mips/s390x/openrisc:
- Rebased on top of master (669743979)
- Added R-b's
- sh4: no changes since v3
- mips: no changes (no reviews yet!)
- sparc:
  + Use base.singlestep_enabled and singlestep like in other targets,
    e.g. Alpha.
  + Remove the unnecessary
     (dc.pc - pc_start) < (TARGET_PAGE_SIZE - 32))
    check.
- s390x:
  + Remove dc->pc, use pc_next instead as David suggested.
  + Use dc for DisasContext instead of s.
  + Compute next_page in translate_insn instead of keeping it in dc.
  + Looked into dropping dc->do_debug, but don't see an easy way to do so.
- openrisc:
  + Consistently use DISAS_NORETURN after generating an
    exception; fixed the two call sites that Richard pointed out,
    plus a couple of others that weren't visible in the previous patch.
  + Remove the dc->next_page_start field; instead, set the max_insn
    bound in translate_insn.

You can fetch this series from:
  https://github.com/cota/qemu/tree/trloop-conv-v1

Diffstat below.

Thanks,

		Emilio

 accel/tcg/translator.c      |   21 +-
 include/exec/translator.h   |    8 +-
 target/alpha/translate.c    |    6 +-
 target/arm/translate-a64.c  |    8 +-
 target/arm/translate.c      |    9 +-
 target/hppa/translate.c     |    7 +-
 target/i386/translate.c     |    5 +-
 target/mips/translate.c     |  623 +++++------
 target/openrisc/translate.c |  226 ++--
 target/ppc/translate.c      |    5 +-
 target/s390x/translate.c    | 1527 +++++++++++++--------------
 target/sh4/translate.c      |  171 +--
 target/sparc/translate.c    |  207 ++--
 13 files changed, 1401 insertions(+), 1422 deletions(-)

On Thu,  1 Mar 2018 17:53:44 -0500
"Emilio G. Cota" <cota@braap.org> wrote:

> [ What is this all about? See this message:
>   http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
> 
> Merged the separate patchsets I sent in the last couple of weeks into
> one set. This will be easier to merge since it will avoid potential
> merge conflicts due to adding max_insns to dc->base.

So, the plan is to merge that as a series? I'll go ahead and ack the
s390x patches, then.

On Thu, Mar 01, 2018 at 17:53:44 -0500, Emilio G. Cota wrote:
> [ What is this all about? See this message:
>   http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
(snip)
> You can fetch this series from:
>   https://github.com/cota/qemu/tree/trloop-conv-v1

*ping* on this series. A few patches are missing reviews, mostly mips/openrisc
bits.

Thanks,

		Emilio

On Fri, Mar 2, 2018 at 11:53 AM, Emilio G. Cota <cota@braap.org> wrote:

> [ What is this all about? See this message:
>   http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
>
> Merged the separate patchsets I sent in the last couple of weeks into
> one set. This will be easier to merge since it will avoid potential
> merge conflicts due to adding max_insns to dc->base.
>
> Changes since sending the separate series for
> sh4/sparc/mips/s390x/openrisc:
> - Rebased on top of master (669743979)
> - Added R-b's
> - sh4: no changes since v3
> - mips: no changes (no reviews yet!)
> - sparc:
>   + Use base.singlestep_enabled and singlestep like in other targets,
>     e.g. Alpha.
>   + Remove the unnecessary
>      (dc.pc - pc_start) < (TARGET_PAGE_SIZE - 32))
>     check.
> - s390x:
>   + Remove dc->pc, use pc_next instead as David suggested.
>   + Use dc for DisasContext instead of s.
>   + Compute next_page in translate_insn instead of keeping it in dc.
>   + Looked into dropping dc->do_debug, but don't see an easy way to do so.
> - openrisc:
>   + Consistently use DISAS_NORETURN after generating an
>     exception; fixed the two call sites that Richard pointed out,
>     plus a couple of others that weren't visible in the previous patch.
>   + Remove the dc->next_page_start field; instead, set the max_insn
>     bound in translate_insn.
>
> You can fetch this series from:
>   https://github.com/cota/qemu/tree/trloop-conv-v1


Curious to know what we would need to change in RISC-V translate.c:

-
https://github.com/riscv/riscv-qemu/blob/qemu-upstream-v8/target/riscv/translate.c

I'm going to make a v8.1 branch and tag that is a rebase of the v8 patch
series against current QEMU master, and hopefully we get the RISC-V port
merged before the soft-freeze. Fingers crossed.

Diffstat below.
>
> Thanks,
>
>                 Emilio
>
>  accel/tcg/translator.c      |   21 +-
>  include/exec/translator.h   |    8 +-
>  target/alpha/translate.c    |    6 +-
>  target/arm/translate-a64.c  |    8 +-
>  target/arm/translate.c      |    9 +-
>  target/hppa/translate.c     |    7 +-
>  target/i386/translate.c     |    5 +-
>  target/mips/translate.c     |  623 +++++------
>  target/openrisc/translate.c |  226 ++--
>  target/ppc/translate.c      |    5 +-
>  target/s390x/translate.c    | 1527 +++++++++++++--------------
>  target/sh4/translate.c      |  171 +--
>  target/sparc/translate.c    |  207 ++--
>  13 files changed, 1401 insertions(+), 1422 deletions(-)
>
>

On Tue, Mar 06, 2018 at 12:57:13 +1300, Michael Clark wrote:
> On Fri, Mar 2, 2018 at 11:53 AM, Emilio G. Cota <cota@braap.org> wrote:
> 
> > [ What is this all about? See this message:
> >   http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
(snip)
> > You can fetch this series from:
> >   https://github.com/cota/qemu/tree/trloop-conv-v1
> 
> 
> Curious to know what we would need to change in RISC-V translate.c:
> 
> -
> https://github.com/riscv/riscv-qemu/blob/qemu-upstream-v8/target/riscv/translate.c
> 
> I'm going to make a v8.1 branch and tag that is a rebase of the v8 patch
> series against current QEMU master, and hopefully we get the RISC-V port
> merged before the soft-freeze. Fingers crossed.

I have patches that convert riscv as well.

Once riscv is on master I'll send the patches to the list; I don't want
this work to delay the riscv merge even more!

		Emilio

On Tue, 6 Mar 2018 at 3:57 PM, Emilio G. Cota <cota@braap.org> wrote:

> On Tue, Mar 06, 2018 at 12:57:13 +1300, Michael Clark wrote:
> > On Fri, Mar 2, 2018 at 11:53 AM, Emilio G. Cota <cota@braap.org> wrote:
> >
> > > [ What is this all about? See this message:
> > >   http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
> (snip)
> > > You can fetch this series from:
> > >   https://github.com/cota/qemu/tree/trloop-conv-v1
> >
> >
> > Curious to know what we would need to change in RISC-V translate.c:
> >
> > -
> >
> https://github.com/riscv/riscv-qemu/blob/qemu-upstream-v8/target/riscv/translate.c
> >
> > I'm going to make a v8.1 branch and tag that is a rebase of the v8 patch
> > series against current QEMU master, and hopefully we get the RISC-V port
> > merged before the soft-freeze. Fingers crossed.
>
> I have patches that convert riscv as well.
>
> Once riscv is on master I'll send the patches to the list; I don't want
> this work to delay the riscv merge even more!


Appreciated. Thanks very much!

Michael

>
>

On 01/03/18 22:53, Emilio G. Cota wrote:

> [ What is this all about? See this message:
>    http://lists.gnu.org/archive/html/qemu-devel/2018-02/msg04785.html ]
> 
> Merged the separate patchsets I sent in the last couple of weeks into
> one set. This will be easier to merge since it will avoid potential
> merge conflicts due to adding max_insns to dc->base.
> 
> Changes since sending the separate series for sh4/sparc/mips/s390x/openrisc:
> - Rebased on top of master (669743979)
> - Added R-b's
> - sh4: no changes since v3
> - mips: no changes (no reviews yet!)
> - sparc:
>    + Use base.singlestep_enabled and singlestep like in other targets,
>      e.g. Alpha.
>    + Remove the unnecessary
>       (dc.pc - pc_start) < (TARGET_PAGE_SIZE - 32))
>      check.
> - s390x:
>    + Remove dc->pc, use pc_next instead as David suggested.
>    + Use dc for DisasContext instead of s.
>    + Compute next_page in translate_insn instead of keeping it in dc.
>    + Looked into dropping dc->do_debug, but don't see an easy way to do so.
> - openrisc:
>    + Consistently use DISAS_NORETURN after generating an
>      exception; fixed the two call sites that Richard pointed out,
>      plus a couple of others that weren't visible in the previous patch.
>    + Remove the dc->next_page_start field; instead, set the max_insn
>      bound in translate_insn.
> 
> You can fetch this series from:
>    https://github.com/cota/qemu/tree/trloop-conv-v1
> 
> Diffstat below.
> 
> Thanks,
> 
> 		Emilio

Hi Emilio,

I don't have enough knowledge of TCG internals to review this myself, 
however I can run it through my complete set of OpenBIOS test images for 
qemu-system-sparc and qemu-system-sparc64 if that helps?


ATB,

Mark.

On Mon, Mar 05, 2018 at 21:58:52 +0000, Mark Cave-Ayland wrote:
> I don't have enough knowledge of TCG internals to review this myself,
> however I can run it through my complete set of OpenBIOS test images for
> qemu-system-sparc and qemu-system-sparc64 if that helps?

That would be appreciated -- I only tested sparc64 by booting a NetBSD
guest.

Thanks,

		Emilio

On 05/03/18 22:43, Emilio G. Cota wrote:

> On Mon, Mar 05, 2018 at 21:58:52 +0000, Mark Cave-Ayland wrote:
>> I don't have enough knowledge of TCG internals to review this myself,
>> however I can run it through my complete set of OpenBIOS test images for
>> qemu-system-sparc and qemu-system-sparc64 if that helps?
> 
> That would be appreciated -- I only tested sparc64 by booting a NetBSD
> guest.

Hi Emilio,

I've given this a run through all my OpenBIOS test images for 
qemu-system-sparc and qemu-system-sparc64 (including single-stepping via 
gdb) and everything appears to be working fine using your trloop-conv-v1
branch.

Whilst I don't know enough about TCG to be able to review this patch, 
for the sparc/sparc64 parts:

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


ATB,

Mark.