1 | More arm patches (mostly the SDHCI ones from Philippe) | 1 | The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9: |
---|---|---|---|
2 | 2 | ||
3 | thanks | 3 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-02-16 11:16:39 +0000) |
4 | -- PMM | ||
5 | 4 | ||
6 | The following changes since commit f521eeee3bd060b460c99e605472b7e03967db43: | 5 | are available in the Git repository at: |
7 | 6 | ||
8 | Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180115' into staging (2018-01-15 13:17:47 +0000) | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230216 |
9 | 8 | ||
10 | are available in the git repository at: | 9 | for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8: |
11 | 10 | ||
12 | git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180116 | 11 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16 16:28:53 +0000) |
13 | |||
14 | for you to fetch changes up to 60765b6ceeb4998a0d4220b3a53f1f185061da77: | ||
15 | |||
16 | sdhci: add a 'dma' property to the sysbus devices (2018-01-16 13:28:21 +0000) | ||
17 | 12 | ||
18 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
19 | target-arm queue: | 14 | target-arm queue: |
20 | * SDHCI: cleanups and minor bug fixes | 15 | * Some mostly M-profile-related code cleanups |
21 | * target/arm: minor refactor preparatory to fp16 support | 16 | * avocado: Retire the boot_linux.py AArch64 TCG tests |
22 | * omap_ssd, ssi-sd, pl181, milkymist-memcard: reset the SD | 17 | * hw/arm/smmuv3: Add GBPA register |
23 | card on controller reset (fixes migration failures) | 18 | * arm/virt: don't try to spell out the accelerator |
24 | * target/arm: Handle page table walk load failures correctly | 19 | * hw/arm: Attach PSPI module to NPCM7XX SoC |
25 | * hw/arm/virt: Add virt-2.12 machine type | 20 | * Some cleanup/refactoring patches aiming towards |
26 | * get_phys_addr_pmsav7: Support AP=0b111 for v7M | 21 | allowing building Arm targets without CONFIG_TCG |
27 | * hw/intc/armv7m: Support byte and halfword accesses to CFSR | ||
28 | 22 | ||
29 | ---------------------------------------------------------------- | 23 | ---------------------------------------------------------------- |
30 | Andrey Smirnov (1): | 24 | Alex Bennée (1): |
31 | sdhci: Implement write method of ACMD12ERRSTS register | 25 | tests/avocado: retire the Aarch64 TCG tests from boot_linux.py |
32 | 26 | ||
33 | Peter Maydell (8): | 27 | Claudio Fontana (3): |
34 | hw/intc/armv7m: Support byte and halfword accesses to CFSR | 28 | target/arm: rename handle_semihosting to tcg_handle_semihosting |
35 | get_phys_addr_pmsav7: Support AP=0b111 for v7M | 29 | target/arm: wrap psci call with tcg_enabled |
36 | hw/arm/virt: Add virt-2.12 machine type | 30 | target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() |
37 | target/arm: Handle page table walk load failures correctly | ||
38 | hw/sd/pl181: Reset SD card on controller reset | ||
39 | hw/sd/milkymist-memcard: Reset SD card on controller reset | ||
40 | hw/sd/ssi-sd: Reset SD card on controller reset | ||
41 | hw/sd/omap_mmc: Reset SD card on controller reset | ||
42 | 31 | ||
43 | Philippe Mathieu-Daudé (13): | 32 | Cornelia Huck (1): |
44 | sdhci: clean up includes | 33 | arm/virt: don't try to spell out the accelerator |
45 | sdhci: remove dead code | ||
46 | sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties | ||
47 | sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init() | ||
48 | sdhci: refactor common sysbus/pci realize() into sdhci_common_realize() | ||
49 | sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize() | ||
50 | sdhci: use qemu_log_mask(UNIMP) instead of fprintf() | ||
51 | sdhci: convert the DPRINT() calls into trace events | ||
52 | sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h" | ||
53 | sdhci: rename the SDHC_CAPAB register | ||
54 | sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only | ||
55 | sdhci: fix the PCI device, using the PCI address space for DMA | ||
56 | sdhci: add a 'dma' property to the sysbus devices | ||
57 | 34 | ||
58 | Richard Henderson (2): | 35 | Fabiano Rosas (7): |
59 | target/arm: Split out vfp_expand_imm | 36 | target/arm: Move PC alignment check |
60 | target/arm: Add fp16 support to vfp_expand_imm | 37 | target/arm: Move cpregs code out of cpu.h |
38 | tests/avocado: Skip tests that require a missing accelerator | ||
39 | tests/avocado: Tag TCG tests with accel:tcg | ||
40 | target/arm: Use "max" as default cpu for the virt machine with KVM | ||
41 | tests/qtest: arm-cpu-features: Match tests to required accelerators | ||
42 | tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG | ||
61 | 43 | ||
62 | hw/sd/sdhci-internal.h | 7 +- | 44 | Hao Wu (3): |
63 | include/hw/sd/sdhci.h | 19 +++- | 45 | MAINTAINERS: Add myself to maintainers and remove Havard |
64 | target/arm/internals.h | 10 ++ | 46 | hw/ssi: Add Nuvoton PSPI Module |
65 | hw/arm/virt.c | 19 +++- | 47 | hw/arm: Attach PSPI module to NPCM7XX SoC |
66 | hw/intc/armv7m_nvic.c | 38 ++++--- | ||
67 | hw/sd/milkymist-memcard.c | 4 + | ||
68 | hw/sd/omap_mmc.c | 14 ++- | ||
69 | hw/sd/pl181.c | 4 + | ||
70 | hw/sd/sdhci.c | 266 +++++++++++++++++++++++++++------------------ | ||
71 | hw/sd/ssi-sd.c | 25 ++++- | ||
72 | target/arm/helper.c | 53 ++++++++- | ||
73 | target/arm/op_helper.c | 7 +- | ||
74 | target/arm/translate-a64.c | 49 ++++++--- | ||
75 | hw/sd/trace-events | 14 +++ | ||
76 | 14 files changed, 362 insertions(+), 167 deletions(-) | ||
77 | 48 | ||
49 | Jean-Philippe Brucker (2): | ||
50 | hw/arm/smmu-common: Support 64-bit addresses | ||
51 | hw/arm/smmu-common: Fix TTB1 handling | ||
52 | |||
53 | Mostafa Saleh (1): | ||
54 | hw/arm/smmuv3: Add GBPA register | ||
55 | |||
56 | Philippe Mathieu-Daudé (12): | ||
57 | hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro | ||
58 | target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation | ||
59 | target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope | ||
60 | target/arm: Constify ID_PFR1 on user emulation | ||
61 | target/arm: Convert CPUARMState::eabi to boolean | ||
62 | target/arm: Avoid resetting CPUARMState::eabi field | ||
63 | target/arm: Restrict CPUARMState::gicv3state to sysemu | ||
64 | target/arm: Restrict CPUARMState::arm_boot_info to sysemu | ||
65 | target/arm: Restrict CPUARMState::nvic to sysemu | ||
66 | target/arm: Store CPUARMState::nvic as NVICState* | ||
67 | target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h' | ||
68 | hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency | ||
69 | |||
70 | MAINTAINERS | 8 +- | ||
71 | docs/system/arm/nuvoton.rst | 2 +- | ||
72 | hw/arm/smmuv3-internal.h | 7 + | ||
73 | include/hw/arm/npcm7xx.h | 2 + | ||
74 | include/hw/arm/smmu-common.h | 2 - | ||
75 | include/hw/arm/smmuv3.h | 1 + | ||
76 | include/hw/intc/armv7m_nvic.h | 128 +++++++++++++++++- | ||
77 | include/hw/ssi/npcm_pspi.h | 53 ++++++++ | ||
78 | linux-user/user-internals.h | 2 +- | ||
79 | target/arm/cpregs.h | 98 ++++++++++++++ | ||
80 | target/arm/cpu.h | 228 ++------------------------------- | ||
81 | target/arm/internals.h | 14 -- | ||
82 | hw/arm/npcm7xx.c | 25 +++- | ||
83 | hw/arm/smmu-common.c | 4 +- | ||
84 | hw/arm/smmuv3.c | 43 ++++++- | ||
85 | hw/arm/virt.c | 10 +- | ||
86 | hw/intc/armv7m_nvic.c | 38 ++---- | ||
87 | hw/ssi/npcm_pspi.c | 221 ++++++++++++++++++++++++++++++++ | ||
88 | linux-user/arm/cpu_loop.c | 4 +- | ||
89 | target/arm/cpu.c | 5 +- | ||
90 | target/arm/cpu_tcg.c | 3 + | ||
91 | target/arm/helper.c | 31 +++-- | ||
92 | target/arm/m_helper.c | 86 +++++++------ | ||
93 | target/arm/machine.c | 18 +-- | ||
94 | tests/qtest/arm-cpu-features.c | 28 ++-- | ||
95 | hw/arm/Kconfig | 1 + | ||
96 | hw/ssi/meson.build | 2 +- | ||
97 | hw/ssi/trace-events | 5 + | ||
98 | tests/avocado/avocado_qemu/__init__.py | 4 + | ||
99 | tests/avocado/boot_linux.py | 48 ++----- | ||
100 | tests/avocado/boot_linux_console.py | 1 + | ||
101 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++- | ||
102 | tests/avocado/reverse_debugging.py | 8 ++ | ||
103 | tests/qtest/meson.build | 4 +- | ||
104 | 34 files changed, 798 insertions(+), 399 deletions(-) | ||
105 | create mode 100644 include/hw/ssi/npcm_pspi.h | ||
106 | create mode 100644 hw/ssi/npcm_pspi.c | ||
107 | diff view generated by jsdifflib |
1 | From: Andrey Smirnov <andrew.smirnov@gmail.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> | 3 | Manually convert to OBJECT_DECLARE_SIMPLE_TYPE() macro, |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | similarly to automatic conversion from commit 8063396bf3 |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). |
6 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 6 | |
7 | Message-id: 20180115182436.2066-13-f4bug@amsat.org | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230206223502.25122-2-philmd@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | hw/sd/sdhci.c | 3 +++ | 12 | include/hw/intc/armv7m_nvic.h | 5 +---- |
11 | 1 file changed, 3 insertions(+) | 13 | 1 file changed, 1 insertion(+), 4 deletions(-) |
12 | 14 | ||
13 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 15 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/sd/sdhci.c | 17 | --- a/include/hw/intc/armv7m_nvic.h |
16 | +++ b/hw/sd/sdhci.c | 18 | +++ b/include/hw/intc/armv7m_nvic.h |
17 | @@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) | 19 | @@ -XXX,XX +XXX,XX @@ |
18 | } | 20 | #include "qom/object.h" |
19 | sdhci_update_irq(s); | 21 | |
20 | break; | 22 | #define TYPE_NVIC "armv7m_nvic" |
21 | + case SDHC_ACMD12ERRSTS: | 23 | - |
22 | + MASKED_WRITE(s->acmd12errsts, mask, value); | 24 | -typedef struct NVICState NVICState; |
23 | + break; | 25 | -DECLARE_INSTANCE_CHECKER(NVICState, NVIC, |
24 | 26 | - TYPE_NVIC) | |
25 | case SDHC_CAPAB: | 27 | +OBJECT_DECLARE_SIMPLE_TYPE(NVICState, NVIC) |
26 | case SDHC_CAPAB + 4: | 28 | |
29 | /* Highest permitted number of exceptions (architectural limit) */ | ||
30 | #define NVIC_MAX_VECTORS 512 | ||
27 | -- | 31 | -- |
28 | 2.7.4 | 32 | 2.34.1 |
29 | 33 | ||
30 | 34 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | Message-id: 20180115182436.2066-7-f4bug@amsat.org | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20230206223502.25122-3-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 8 | --- |
8 | hw/sd/sdhci.c | 22 ++++++++++++++++++++++ | 9 | target/arm/m_helper.c | 11 ++++++++--- |
9 | 1 file changed, 22 insertions(+) | 10 | 1 file changed, 8 insertions(+), 3 deletions(-) |
10 | 11 | ||
11 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 12 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
12 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/sd/sdhci.c | 14 | --- a/target/arm/m_helper.c |
14 | +++ b/hw/sd/sdhci.c | 15 | +++ b/target/arm/m_helper.c |
15 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
16 | #include "qemu/bitops.h" | 17 | return 0; |
17 | #include "hw/sd/sdhci.h" | ||
18 | #include "sdhci-internal.h" | ||
19 | +#include "qapi/error.h" | ||
20 | #include "qemu/log.h" | ||
21 | |||
22 | /* host controller debug messages */ | ||
23 | @@ -XXX,XX +XXX,XX @@ static void sdhci_common_realize(SDHCIState *s, Error **errp) | ||
24 | SDHC_REGISTERS_MAP_SIZE); | ||
25 | } | 18 | } |
26 | 19 | ||
27 | +static void sdhci_common_unrealize(SDHCIState *s, Error **errp) | 20 | -#else |
21 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
28 | +{ | 22 | +{ |
29 | + /* This function is expected to be called only once for each class: | 23 | + return ARMMMUIdx_MUser; |
30 | + * - SysBus: via DeviceClass->unrealize(), | ||
31 | + * - PCI: via PCIDeviceClass->exit(). | ||
32 | + * However to avoid double-free and/or use-after-free we still nullify | ||
33 | + * this variable (better safe than sorry!). */ | ||
34 | + g_free(s->fifo_buffer); | ||
35 | + s->fifo_buffer = NULL; | ||
36 | +} | 24 | +} |
37 | + | 25 | + |
38 | static bool sdhci_pending_insert_vmstate_needed(void *opaque) | 26 | +#else /* !CONFIG_USER_ONLY */ |
27 | |||
28 | /* | ||
29 | * What kind of stack write are we doing? This affects how exceptions | ||
30 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
31 | return tt_resp; | ||
32 | } | ||
33 | |||
34 | -#endif /* !CONFIG_USER_ONLY */ | ||
35 | - | ||
36 | ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
37 | bool secstate, bool priv, bool negpri) | ||
39 | { | 38 | { |
40 | SDHCIState *s = opaque; | 39 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
41 | @@ -XXX,XX +XXX,XX @@ static void sdhci_pci_realize(PCIDevice *dev, Error **errp) | 40 | |
42 | static void sdhci_pci_exit(PCIDevice *dev) | 41 | return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); |
43 | { | 42 | } |
44 | SDHCIState *s = PCI_SDHCI(dev); | ||
45 | + | 43 | + |
46 | + sdhci_common_unrealize(s, &error_abort); | 44 | +#endif /* !CONFIG_USER_ONLY */ |
47 | sdhci_uninitfn(s); | ||
48 | } | ||
49 | |||
50 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) | ||
51 | sysbus_init_mmio(sbd, &s->iomem); | ||
52 | } | ||
53 | |||
54 | +static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp) | ||
55 | +{ | ||
56 | + SDHCIState *s = SYSBUS_SDHCI(dev); | ||
57 | + | ||
58 | + sdhci_common_unrealize(s, &error_abort); | ||
59 | +} | ||
60 | + | ||
61 | static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) | ||
62 | { | ||
63 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
64 | |||
65 | dc->props = sdhci_sysbus_properties; | ||
66 | dc->realize = sdhci_sysbus_realize; | ||
67 | + dc->unrealize = sdhci_sysbus_unrealize; | ||
68 | |||
69 | sdhci_common_class_init(klass, data); | ||
70 | } | ||
71 | -- | 45 | -- |
72 | 2.7.4 | 46 | 2.34.1 |
73 | 47 | ||
74 | 48 | diff view generated by jsdifflib |
1 | Instead of ignoring the response from address_space_ld*() | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | (indicating an attempt to read a page table descriptor from | ||
3 | an invalid physical address), use it to report the failure | ||
4 | correctly. | ||
5 | 2 | ||
6 | Since this is another couple of locations where we need to | 3 | arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv() |
7 | decide the value of the ARMMMUFaultInfo ea bit based on a | 4 | are only used for system emulation in m_helper.c. |
8 | MemTxResult, we factor out that operation into a helper | 5 | Move the definitions to avoid prototype forward declarations. |
9 | function. | ||
10 | 6 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20230206223502.25122-4-philmd@linaro.org | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 11 | --- |
13 | target/arm/internals.h | 10 ++++++++++ | 12 | target/arm/internals.h | 14 -------- |
14 | target/arm/helper.c | 39 ++++++++++++++++++++++++++++++++++----- | 13 | target/arm/m_helper.c | 74 +++++++++++++++++++++--------------------- |
15 | target/arm/op_helper.c | 7 +------ | 14 | 2 files changed, 37 insertions(+), 51 deletions(-) |
16 | 3 files changed, 45 insertions(+), 11 deletions(-) | ||
17 | 15 | ||
18 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
19 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/internals.h | 18 | --- a/target/arm/internals.h |
21 | +++ b/target/arm/internals.h | 19 | +++ b/target/arm/internals.h |
22 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) | 20 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx) |
23 | return fsc; | 21 | |
24 | } | 22 | int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); |
25 | 23 | ||
26 | +static inline bool arm_extabort_type(MemTxResult result) | 24 | -/* |
25 | - * Return the MMU index for a v7M CPU with all relevant information | ||
26 | - * manually specified. | ||
27 | - */ | ||
28 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
29 | - bool secstate, bool priv, bool negpri); | ||
30 | - | ||
31 | -/* | ||
32 | - * Return the MMU index for a v7M CPU in the specified security and | ||
33 | - * privilege state. | ||
34 | - */ | ||
35 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
36 | - bool secstate, bool priv); | ||
37 | - | ||
38 | /* Return the MMU index for a v7M CPU in the specified security state */ | ||
39 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); | ||
40 | |||
41 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
42 | index XXXXXXX..XXXXXXX 100644 | ||
43 | --- a/target/arm/m_helper.c | ||
44 | +++ b/target/arm/m_helper.c | ||
45 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | ||
46 | |||
47 | #else /* !CONFIG_USER_ONLY */ | ||
48 | |||
49 | +static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
50 | + bool secstate, bool priv, bool negpri) | ||
27 | +{ | 51 | +{ |
28 | + /* The EA bit in syndromes and fault status registers is an | 52 | + ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; |
29 | + * IMPDEF classification of external aborts. ARM implementations | 53 | + |
30 | + * usually use this to indicate AXI bus Decode error (0) or | 54 | + if (priv) { |
31 | + * Slave error (1); in QEMU we follow that. | 55 | + mmu_idx |= ARM_MMU_IDX_M_PRIV; |
32 | + */ | 56 | + } |
33 | + return result != MEMTX_DECODE_ERROR; | 57 | + |
58 | + if (negpri) { | ||
59 | + mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | ||
60 | + } | ||
61 | + | ||
62 | + if (secstate) { | ||
63 | + mmu_idx |= ARM_MMU_IDX_M_S; | ||
64 | + } | ||
65 | + | ||
66 | + return mmu_idx; | ||
34 | +} | 67 | +} |
35 | + | 68 | + |
36 | /* Do a page table walk and add page to TLB if possible */ | 69 | +static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
37 | bool arm_tlb_fill(CPUState *cpu, vaddr address, | 70 | + bool secstate, bool priv) |
38 | MMUAccessType access_type, int mmu_idx, | 71 | +{ |
39 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 72 | + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); |
40 | index XXXXXXX..XXXXXXX 100644 | 73 | + |
41 | --- a/target/arm/helper.c | 74 | + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); |
42 | +++ b/target/arm/helper.c | 75 | +} |
43 | @@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | 76 | + |
44 | ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, | 77 | +/* Return the MMU index for a v7M CPU in the specified security state */ |
45 | &txattrs, &s2prot, &s2size, fi, NULL); | 78 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
46 | if (ret) { | 79 | +{ |
47 | + assert(fi->type != ARMFault_None); | 80 | + bool priv = arm_v7m_is_handler_mode(env) || |
48 | fi->s2addr = addr; | 81 | + !(env->v7m.control[secstate] & 1); |
49 | fi->stage2 = true; | 82 | + |
50 | fi->s1ptw = true; | 83 | + return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); |
51 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, | 84 | +} |
52 | ARMCPU *cpu = ARM_CPU(cs); | 85 | + |
53 | CPUARMState *env = &cpu->env; | 86 | /* |
54 | MemTxAttrs attrs = {}; | 87 | * What kind of stack write are we doing? This affects how exceptions |
55 | + MemTxResult result = MEMTX_OK; | 88 | * generated during the stacking are treated. |
56 | AddressSpace *as; | 89 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) |
57 | + uint32_t data; | 90 | return tt_resp; |
58 | |||
59 | attrs.secure = is_secure; | ||
60 | as = arm_addressspace(cs, attrs); | ||
61 | @@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, | ||
62 | return 0; | ||
63 | } | ||
64 | if (regime_translation_big_endian(env, mmu_idx)) { | ||
65 | - return address_space_ldl_be(as, addr, attrs, NULL); | ||
66 | + data = address_space_ldl_be(as, addr, attrs, &result); | ||
67 | } else { | ||
68 | - return address_space_ldl_le(as, addr, attrs, NULL); | ||
69 | + data = address_space_ldl_le(as, addr, attrs, &result); | ||
70 | } | ||
71 | + if (result == MEMTX_OK) { | ||
72 | + return data; | ||
73 | + } | ||
74 | + fi->type = ARMFault_SyncExternalOnWalk; | ||
75 | + fi->ea = arm_extabort_type(result); | ||
76 | + return 0; | ||
77 | } | 91 | } |
78 | 92 | ||
79 | static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, | 93 | -ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, |
80 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, | 94 | - bool secstate, bool priv, bool negpri) |
81 | ARMCPU *cpu = ARM_CPU(cs); | 95 | -{ |
82 | CPUARMState *env = &cpu->env; | 96 | - ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; |
83 | MemTxAttrs attrs = {}; | 97 | - |
84 | + MemTxResult result = MEMTX_OK; | 98 | - if (priv) { |
85 | AddressSpace *as; | 99 | - mmu_idx |= ARM_MMU_IDX_M_PRIV; |
86 | + uint32_t data; | 100 | - } |
87 | 101 | - | |
88 | attrs.secure = is_secure; | 102 | - if (negpri) { |
89 | as = arm_addressspace(cs, attrs); | 103 | - mmu_idx |= ARM_MMU_IDX_M_NEGPRI; |
90 | @@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, | 104 | - } |
91 | return 0; | 105 | - |
92 | } | 106 | - if (secstate) { |
93 | if (regime_translation_big_endian(env, mmu_idx)) { | 107 | - mmu_idx |= ARM_MMU_IDX_M_S; |
94 | - return address_space_ldq_be(as, addr, attrs, NULL); | 108 | - } |
95 | + data = address_space_ldq_be(as, addr, attrs, &result); | 109 | - |
96 | } else { | 110 | - return mmu_idx; |
97 | - return address_space_ldq_le(as, addr, attrs, NULL); | 111 | -} |
98 | + data = address_space_ldq_le(as, addr, attrs, &result); | 112 | - |
99 | + } | 113 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, |
100 | + if (result == MEMTX_OK) { | 114 | - bool secstate, bool priv) |
101 | + return data; | 115 | -{ |
102 | } | 116 | - bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); |
103 | + fi->type = ARMFault_SyncExternalOnWalk; | 117 | - |
104 | + fi->ea = arm_extabort_type(result); | 118 | - return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); |
105 | + return 0; | 119 | -} |
106 | } | 120 | - |
107 | 121 | -/* Return the MMU index for a v7M CPU in the specified security state */ | |
108 | static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, | 122 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) |
109 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, | 123 | -{ |
110 | } | 124 | - bool priv = arm_v7m_is_handler_mode(env) || |
111 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), | 125 | - !(env->v7m.control[secstate] & 1); |
112 | mmu_idx, fi); | 126 | - |
113 | + if (fi->type != ARMFault_None) { | 127 | - return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); |
114 | + goto do_fault; | 128 | -} |
115 | + } | 129 | - |
116 | type = (desc & 3); | 130 | #endif /* !CONFIG_USER_ONLY */ |
117 | domain = (desc >> 5) & 0x0f; | ||
118 | if (regime_el(env, mmu_idx) == 1) { | ||
119 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, | ||
120 | } | ||
121 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), | ||
122 | mmu_idx, fi); | ||
123 | + if (fi->type != ARMFault_None) { | ||
124 | + goto do_fault; | ||
125 | + } | ||
126 | switch (desc & 3) { | ||
127 | case 0: /* Page translation fault. */ | ||
128 | fi->type = ARMFault_Translation; | ||
129 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, | ||
130 | } | ||
131 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), | ||
132 | mmu_idx, fi); | ||
133 | + if (fi->type != ARMFault_None) { | ||
134 | + goto do_fault; | ||
135 | + } | ||
136 | type = (desc & 3); | ||
137 | if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { | ||
138 | /* Section translation fault, or attempt to use the encoding | ||
139 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, | ||
140 | table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); | ||
141 | desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), | ||
142 | mmu_idx, fi); | ||
143 | + if (fi->type != ARMFault_None) { | ||
144 | + goto do_fault; | ||
145 | + } | ||
146 | ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); | ||
147 | switch (desc & 3) { | ||
148 | case 0: /* Page translation fault. */ | ||
149 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | ||
150 | descaddr &= ~7ULL; | ||
151 | nstable = extract32(tableattrs, 4, 1); | ||
152 | descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); | ||
153 | - if (fi->s1ptw) { | ||
154 | + if (fi->type != ARMFault_None) { | ||
155 | goto do_fault; | ||
156 | } | ||
157 | |||
158 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
159 | index XXXXXXX..XXXXXXX 100644 | ||
160 | --- a/target/arm/op_helper.c | ||
161 | +++ b/target/arm/op_helper.c | ||
162 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, | ||
163 | /* now we have a real cpu fault */ | ||
164 | cpu_restore_state(cs, retaddr); | ||
165 | |||
166 | - /* The EA bit in syndromes and fault status registers is an | ||
167 | - * IMPDEF classification of external aborts. ARM implementations | ||
168 | - * usually use this to indicate AXI bus Decode error (0) or | ||
169 | - * Slave error (1); in QEMU we follow that. | ||
170 | - */ | ||
171 | - fi.ea = (response != MEMTX_DECODE_ERROR); | ||
172 | + fi.ea = arm_extabort_type(response); | ||
173 | fi.type = ARMFault_SyncExternal; | ||
174 | deliver_fault(cpu, addr, access_type, mmu_idx, &fi); | ||
175 | } | ||
176 | -- | 131 | -- |
177 | 2.7.4 | 132 | 2.34.1 |
178 | 133 | ||
179 | 134 | diff view generated by jsdifflib |
1 | Since ssi-sd is still using the legacy SD card API, the SD | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | card created by sd_init() is not plugged into any bus. This | ||
3 | means that the controller has to reset it manually. | ||
4 | 2 | ||
5 | Failing to do this mostly didn't affect the guest since the | 3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | guest typically does a programmed SD card reset as part of | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | its SD controller driver initialization, but meant that | 5 | Message-id: 20230206223502.25122-5-philmd@linaro.org |
8 | migration failed because it's only in sd_reset() that we | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | set up the wpgrps_size field. | 7 | --- |
8 | target/arm/helper.c | 12 ++++++++++-- | ||
9 | 1 file changed, 10 insertions(+), 2 deletions(-) | ||
10 | 10 | ||
11 | In the case of sd-ssi, we have to implement an entire | 11 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
12 | reset function since there wasn't one previously, and | ||
13 | that requires a QOM cast macro that got omitted when this | ||
14 | device was QOMified. | ||
15 | |||
16 | Cc: qemu-stable@nongnu.org | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
19 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
20 | Message-id: 1515506513-31961-4-git-send-email-peter.maydell@linaro.org | ||
21 | --- | ||
22 | hw/sd/ssi-sd.c | 25 +++++++++++++++++++++++-- | ||
23 | 1 file changed, 23 insertions(+), 2 deletions(-) | ||
24 | |||
25 | diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/hw/sd/ssi-sd.c | 13 | --- a/target/arm/helper.c |
28 | +++ b/hw/sd/ssi-sd.c | 14 | +++ b/target/arm/helper.c |
29 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 15 | @@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu) |
30 | SDState *sd; | ||
31 | } ssi_sd_state; | ||
32 | |||
33 | +#define TYPE_SSI_SD "ssi-sd" | ||
34 | +#define SSI_SD(obj) OBJECT_CHECK(ssi_sd_state, (obj), TYPE_SSI_SD) | ||
35 | + | ||
36 | /* State word bits. */ | ||
37 | #define SSI_SDR_LOCKED 0x0001 | ||
38 | #define SSI_SDR_WP_ERASE 0x0002 | ||
39 | @@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSISlave *d, Error **errp) | ||
40 | ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d); | ||
41 | DriveInfo *dinfo; | ||
42 | |||
43 | - s->mode = SSI_SD_CMD; | ||
44 | /* FIXME use a qdev drive property instead of drive_get_next() */ | ||
45 | dinfo = drive_get_next(IF_SD); | ||
46 | s->sd = sd_init(dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, true); | ||
47 | @@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSISlave *d, Error **errp) | ||
48 | } | 16 | } |
49 | } | 17 | } |
50 | 18 | ||
51 | +static void ssi_sd_reset(DeviceState *dev) | 19 | +#ifndef CONFIG_USER_ONLY |
52 | +{ | 20 | /* |
53 | + ssi_sd_state *s = SSI_SD(dev); | 21 | * We don't know until after realize whether there's a GICv3 |
54 | + | 22 | * attached, and that is what registers the gicv3 sysregs. |
55 | + s->mode = SSI_SD_CMD; | 23 | @@ -XXX,XX +XXX,XX @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) |
56 | + s->cmd = 0; | 24 | return pfr1; |
57 | + memset(s->cmdarg, 0, sizeof(s->cmdarg)); | 25 | } |
58 | + memset(s->response, 0, sizeof(s->response)); | 26 | |
59 | + s->arglen = 0; | 27 | -#ifndef CONFIG_USER_ONLY |
60 | + s->response_pos = 0; | 28 | static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) |
61 | + s->stopping = 0; | ||
62 | + | ||
63 | + /* Since we're still using the legacy SD API the card is not plugged | ||
64 | + * into any bus, and we must reset it manually. | ||
65 | + */ | ||
66 | + device_reset(DEVICE(s->sd)); | ||
67 | +} | ||
68 | + | ||
69 | static void ssi_sd_class_init(ObjectClass *klass, void *data) | ||
70 | { | 29 | { |
71 | DeviceClass *dc = DEVICE_CLASS(klass); | 30 | ARMCPU *cpu = env_archcpu(env); |
72 | @@ -XXX,XX +XXX,XX @@ static void ssi_sd_class_init(ObjectClass *klass, void *data) | 31 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
73 | k->transfer = ssi_sd_transfer; | 32 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1, |
74 | k->cs_polarity = SSI_CS_LOW; | 33 | .access = PL1_R, .type = ARM_CP_NO_RAW, |
75 | dc->vmsd = &vmstate_ssi_sd; | 34 | .accessfn = access_aa32_tid3, |
76 | + dc->reset = ssi_sd_reset; | 35 | +#ifdef CONFIG_USER_ONLY |
77 | } | 36 | + .type = ARM_CP_CONST, |
78 | 37 | + .resetvalue = cpu->isar.id_pfr1, | |
79 | static const TypeInfo ssi_sd_info = { | 38 | +#else |
80 | - .name = "ssi-sd", | 39 | + .type = ARM_CP_NO_RAW, |
81 | + .name = TYPE_SSI_SD, | 40 | + .accessfn = access_aa32_tid3, |
82 | .parent = TYPE_SSI_SLAVE, | 41 | .readfn = id_pfr1_read, |
83 | .instance_size = sizeof(ssi_sd_state), | 42 | - .writefn = arm_cp_write_ignore }, |
84 | .class_init = ssi_sd_class_init, | 43 | + .writefn = arm_cp_write_ignore |
44 | +#endif | ||
45 | + }, | ||
46 | { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH, | ||
47 | .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2, | ||
48 | .access = PL1_R, .type = ARM_CP_CONST, | ||
85 | -- | 49 | -- |
86 | 2.7.4 | 50 | 2.34.1 |
87 | 51 | ||
88 | 52 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | Message-id: 20180115182436.2066-2-f4bug@amsat.org | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20230206223502.25122-6-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 8 | --- |
8 | hw/sd/sdhci-internal.h | 4 ---- | 9 | linux-user/user-internals.h | 2 +- |
9 | include/hw/sd/sdhci.h | 7 ++++++- | 10 | target/arm/cpu.h | 2 +- |
10 | hw/sd/sdhci.c | 1 + | 11 | linux-user/arm/cpu_loop.c | 4 ++-- |
11 | 3 files changed, 7 insertions(+), 5 deletions(-) | 12 | 3 files changed, 4 insertions(+), 4 deletions(-) |
12 | 13 | ||
13 | diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h | 14 | diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/sd/sdhci-internal.h | 16 | --- a/linux-user/user-internals.h |
16 | +++ b/hw/sd/sdhci-internal.h | 17 | +++ b/linux-user/user-internals.h |
17 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ void print_termios(void *arg); |
18 | #ifndef SDHCI_INTERNAL_H | 19 | #ifdef TARGET_ARM |
19 | #define SDHCI_INTERNAL_H | 20 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) |
20 | 21 | { | |
21 | -#include "hw/sd/sdhci.h" | 22 | - return cpu_env->eabi == 1; |
22 | - | 23 | + return cpu_env->eabi; |
23 | /* R/W SDMA System Address register 0x0 */ | 24 | } |
24 | #define SDHC_SYSAD 0x00 | 25 | #elif defined(TARGET_MIPS) && defined(TARGET_ABI_MIPSO32) |
25 | 26 | static inline int regpairs_aligned(CPUArchState *cpu_env, int num) { return 1; } | |
26 | @@ -XXX,XX +XXX,XX @@ enum { | 27 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
27 | sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */ | 28 | index XXXXXXX..XXXXXXX 100644 |
28 | }; | 29 | --- a/target/arm/cpu.h |
29 | 30 | +++ b/target/arm/cpu.h | |
30 | -extern const VMStateDescription sdhci_vmstate; | 31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
31 | - | 32 | |
33 | #if defined(CONFIG_USER_ONLY) | ||
34 | /* For usermode syscall translation. */ | ||
35 | - int eabi; | ||
36 | + bool eabi; | ||
32 | #endif | 37 | #endif |
33 | diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h | 38 | |
39 | struct CPUBreakpoint *cpu_breakpoint[16]; | ||
40 | diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/include/hw/sd/sdhci.h | 42 | --- a/linux-user/arm/cpu_loop.c |
36 | +++ b/include/hw/sd/sdhci.h | 43 | +++ b/linux-user/arm/cpu_loop.c |
37 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) |
38 | #define SDHCI_H | 45 | break; |
39 | 46 | case EXCP_SWI: | |
40 | #include "qemu-common.h" | 47 | { |
41 | -#include "hw/block/block.h" | 48 | - env->eabi = 1; |
42 | #include "hw/pci/pci.h" | 49 | + env->eabi = true; |
43 | #include "hw/sysbus.h" | 50 | /* system call */ |
44 | #include "hw/sd/sd.h" | 51 | if (env->thumb) { |
45 | 52 | /* Thumb is always EABI style with syscall number in r7 */ | |
46 | /* SD/MMC host controller state */ | 53 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) |
47 | typedef struct SDHCIState { | 54 | * > 0xfffff and are handled below as out-of-range. |
48 | + /*< private >*/ | 55 | */ |
49 | union { | 56 | n ^= ARM_SYSCALL_BASE; |
50 | PCIDevice pcidev; | 57 | - env->eabi = 0; |
51 | SysBusDevice busdev; | 58 | + env->eabi = false; |
52 | }; | 59 | } |
53 | + | 60 | } |
54 | + /*< public >*/ | ||
55 | SDBus sdbus; | ||
56 | MemoryRegion iomem; | ||
57 | |||
58 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | ||
59 | qemu_irq ro_cb; | ||
60 | qemu_irq irq; | ||
61 | |||
62 | + /* Registers cleared on reset */ | ||
63 | uint32_t sdmasysad; /* SDMA System Address register */ | ||
64 | uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */ | ||
65 | uint16_t blkcnt; /* Blocks count for current transfer */ | ||
66 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | ||
67 | uint16_t acmd12errsts; /* Auto CMD12 error status register */ | ||
68 | uint64_t admasysaddr; /* ADMA System Address Register */ | ||
69 | |||
70 | + /* Read-only registers */ | ||
71 | uint32_t capareg; /* Capabilities Register */ | ||
72 | uint32_t maxcurr; /* Maximum Current Capabilities Register */ | ||
73 | + | ||
74 | uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ | ||
75 | uint32_t buf_maxsz; | ||
76 | uint16_t data_count; /* current element in FIFO buffer */ | ||
77 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/hw/sd/sdhci.c | ||
80 | +++ b/hw/sd/sdhci.c | ||
81 | @@ -XXX,XX +XXX,XX @@ | ||
82 | #include "sysemu/dma.h" | ||
83 | #include "qemu/timer.h" | ||
84 | #include "qemu/bitops.h" | ||
85 | +#include "hw/sd/sdhci.h" | ||
86 | #include "sdhci-internal.h" | ||
87 | #include "qemu/log.h" | ||
88 | 61 | ||
89 | -- | 62 | -- |
90 | 2.7.4 | 63 | 2.34.1 |
91 | 64 | ||
92 | 65 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | running qtests: | 3 | Although the 'eabi' field is only used in user emulation where |
4 | CPU reset doesn't occur, it doesn't belong to the area to reset. | ||
5 | Move it after the 'end_reset_fields' for consistency. | ||
4 | 6 | ||
5 | $ make check-qtest-arm | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | GTESTER check-qtest-arm | 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | SDHC rd_4b @0x44 not implemented | 9 | Message-id: 20230206223502.25122-7-philmd@linaro.org |
8 | SDHC wr_4b @0x40 <- 0x89abcdef not implemented | ||
9 | SDHC wr_4b @0x44 <- 0x01234567 not implemented | ||
10 | |||
11 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
12 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | ||
13 | Message-id: 20180115182436.2066-12-f4bug@amsat.org | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 11 | --- |
16 | include/hw/sd/sdhci.h | 4 ++-- | 12 | target/arm/cpu.h | 9 ++++----- |
17 | hw/sd/sdhci.c | 23 +++++++++++++++++++---- | 13 | 1 file changed, 4 insertions(+), 5 deletions(-) |
18 | 2 files changed, 21 insertions(+), 6 deletions(-) | ||
19 | 14 | ||
20 | diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h | 15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
21 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/include/hw/sd/sdhci.h | 17 | --- a/target/arm/cpu.h |
23 | +++ b/include/hw/sd/sdhci.h | 18 | +++ b/target/arm/cpu.h |
24 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | 19 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
25 | uint64_t admasysaddr; /* ADMA System Address Register */ | 20 | ARMVectorReg zarray[ARM_MAX_VQ * 16]; |
26 | 21 | #endif | |
27 | /* Read-only registers */ | 22 | |
28 | - uint32_t capareg; /* Capabilities Register */ | 23 | -#if defined(CONFIG_USER_ONLY) |
29 | - uint32_t maxcurr; /* Maximum Current Capabilities Register */ | 24 | - /* For usermode syscall translation. */ |
30 | + uint64_t capareg; /* Capabilities Register */ | 25 | - bool eabi; |
31 | + uint64_t maxcurr; /* Maximum Current Capabilities Register */ | 26 | -#endif |
32 | 27 | - | |
33 | uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ | 28 | struct CPUBreakpoint *cpu_breakpoint[16]; |
34 | uint32_t buf_maxsz; | 29 | struct CPUWatchpoint *cpu_watchpoint[16]; |
35 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 30 | |
36 | index XXXXXXX..XXXXXXX 100644 | 31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
37 | --- a/hw/sd/sdhci.c | 32 | const struct arm_boot_info *boot_info; |
38 | +++ b/hw/sd/sdhci.c | 33 | /* Store GICv3CPUState to access from this struct */ |
39 | @@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) | 34 | void *gicv3state; |
40 | ret = s->acmd12errsts; | 35 | +#if defined(CONFIG_USER_ONLY) |
41 | break; | 36 | + /* For usermode syscall translation. */ |
42 | case SDHC_CAPAB: | 37 | + bool eabi; |
43 | - ret = s->capareg; | 38 | +#endif /* CONFIG_USER_ONLY */ |
44 | + ret = (uint32_t)s->capareg; | 39 | |
45 | + break; | 40 | #ifdef TARGET_TAGGED_ADDRESSES |
46 | + case SDHC_CAPAB + 4: | 41 | /* Linux syscall tagged address support */ |
47 | + ret = (uint32_t)(s->capareg >> 32); | ||
48 | break; | ||
49 | case SDHC_MAXCURR: | ||
50 | - ret = s->maxcurr; | ||
51 | + ret = (uint32_t)s->maxcurr; | ||
52 | + break; | ||
53 | + case SDHC_MAXCURR + 4: | ||
54 | + ret = (uint32_t)(s->maxcurr >> 32); | ||
55 | break; | ||
56 | case SDHC_ADMAERR: | ||
57 | ret = s->admaerr; | ||
58 | @@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) | ||
59 | } | ||
60 | sdhci_update_irq(s); | ||
61 | break; | ||
62 | + | ||
63 | + case SDHC_CAPAB: | ||
64 | + case SDHC_CAPAB + 4: | ||
65 | + case SDHC_MAXCURR: | ||
66 | + case SDHC_MAXCURR + 4: | ||
67 | + qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx | ||
68 | + " <- 0x%08x read-only\n", size, offset, value >> shift); | ||
69 | + break; | ||
70 | + | ||
71 | default: | ||
72 | qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " | ||
73 | "not implemented\n", size, offset, value >> shift); | ||
74 | @@ -XXX,XX +XXX,XX @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s) | ||
75 | #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ | ||
76 | /* Capabilities registers provide information on supported features | ||
77 | * of this specific host controller implementation */ \ | ||
78 | - DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ | ||
79 | - DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0) | ||
80 | + DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ | ||
81 | + DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) | ||
82 | |||
83 | static void sdhci_initfn(SDHCIState *s) | ||
84 | { | ||
85 | -- | 42 | -- |
86 | 2.7.4 | 43 | 2.34.1 |
87 | 44 | ||
88 | 45 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | Message-id: 20180115182436.2066-11-f4bug@amsat.org | 5 | Message-id: 20230206223502.25122-8-philmd@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | hw/sd/sdhci-internal.h | 2 +- | 8 | target/arm/cpu.h | 3 ++- |
9 | hw/sd/sdhci.c | 2 +- | 9 | 1 file changed, 2 insertions(+), 1 deletion(-) |
10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | 10 | ||
12 | diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
13 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/sd/sdhci-internal.h | 13 | --- a/target/arm/cpu.h |
15 | +++ b/hw/sd/sdhci-internal.h | 14 | +++ b/target/arm/cpu.h |
16 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
17 | #define SDHC_ACMD12ERRSTS 0x3C | 16 | |
18 | 17 | void *nvic; | |
19 | /* HWInit Capabilities Register 0x05E80080 */ | 18 | const struct arm_boot_info *boot_info; |
20 | -#define SDHC_CAPAREG 0x40 | 19 | +#if !defined(CONFIG_USER_ONLY) |
21 | +#define SDHC_CAPAB 0x40 | 20 | /* Store GICv3CPUState to access from this struct */ |
22 | #define SDHC_CAN_DO_DMA 0x00400000 | 21 | void *gicv3state; |
23 | #define SDHC_CAN_DO_ADMA2 0x00080000 | 22 | -#if defined(CONFIG_USER_ONLY) |
24 | #define SDHC_CAN_DO_ADMA1 0x00100000 | 23 | +#else /* CONFIG_USER_ONLY */ |
25 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 24 | /* For usermode syscall translation. */ |
26 | index XXXXXXX..XXXXXXX 100644 | 25 | bool eabi; |
27 | --- a/hw/sd/sdhci.c | 26 | #endif /* CONFIG_USER_ONLY */ |
28 | +++ b/hw/sd/sdhci.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) | ||
30 | case SDHC_ACMD12ERRSTS: | ||
31 | ret = s->acmd12errsts; | ||
32 | break; | ||
33 | - case SDHC_CAPAREG: | ||
34 | + case SDHC_CAPAB: | ||
35 | ret = s->capareg; | ||
36 | break; | ||
37 | case SDHC_MAXCURR: | ||
38 | -- | 27 | -- |
39 | 2.7.4 | 28 | 2.34.1 |
40 | 29 | ||
41 | 30 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | Message-id: 20180115182436.2066-10-f4bug@amsat.org | 5 | Message-id: 20230206223502.25122-9-philmd@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | hw/sd/sdhci-internal.h | 1 + | 8 | target/arm/cpu.h | 2 +- |
9 | hw/sd/sdhci.c | 3 +-- | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
11 | 10 | ||
12 | diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
13 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/sd/sdhci-internal.h | 13 | --- a/target/arm/cpu.h |
15 | +++ b/hw/sd/sdhci-internal.h | 14 | +++ b/target/arm/cpu.h |
16 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
17 | #define SDHC_TRNS_ACMD12 0x0004 | 16 | } sau; |
18 | #define SDHC_TRNS_READ 0x0010 | 17 | |
19 | #define SDHC_TRNS_MULTI 0x0020 | 18 | void *nvic; |
20 | +#define SDHC_TRNMOD_MASK 0x0037 | 19 | - const struct arm_boot_info *boot_info; |
21 | 20 | #if !defined(CONFIG_USER_ONLY) | |
22 | /* R/W Command Register 0x0 */ | 21 | + const struct arm_boot_info *boot_info; |
23 | #define SDHC_CMDREG 0x0E | 22 | /* Store GICv3CPUState to access from this struct */ |
24 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 23 | void *gicv3state; |
25 | index XXXXXXX..XXXXXXX 100644 | 24 | #else /* CONFIG_USER_ONLY */ |
26 | --- a/hw/sd/sdhci.c | ||
27 | +++ b/hw/sd/sdhci.c | ||
28 | @@ -XXX,XX +XXX,XX @@ | ||
29 | (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ | ||
30 | (SDHC_CAPAB_TOCLKFREQ)) | ||
31 | |||
32 | -#define MASK_TRNMOD 0x0037 | ||
33 | #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) | ||
34 | |||
35 | static uint8_t sdhci_slotint(SDHCIState *s) | ||
36 | @@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) | ||
37 | if (!(s->capareg & SDHC_CAN_DO_DMA)) { | ||
38 | value &= ~SDHC_TRNS_DMA; | ||
39 | } | ||
40 | - MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD); | ||
41 | + MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); | ||
42 | MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); | ||
43 | |||
44 | /* Writing to the upper byte of CMDREG triggers SD command generation */ | ||
45 | -- | 25 | -- |
46 | 2.7.4 | 26 | 2.34.1 |
47 | 27 | ||
48 | 28 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20180115182436.2066-3-f4bug@amsat.org | 5 | Message-id: 20230206223502.25122-10-philmd@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 7 | --- |
8 | include/hw/sd/sdhci.h | 2 -- | 8 | target/arm/cpu.h | 2 +- |
9 | hw/sd/sdhci.c | 2 -- | 9 | 1 file changed, 1 insertion(+), 1 deletion(-) |
10 | 2 files changed, 4 deletions(-) | ||
11 | 10 | ||
12 | diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h | 11 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
13 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/hw/sd/sdhci.h | 13 | --- a/target/arm/cpu.h |
15 | +++ b/include/hw/sd/sdhci.h | 14 | +++ b/target/arm/cpu.h |
16 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | 15 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { |
17 | 16 | uint32_t ctrl; | |
18 | QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ | 17 | } sau; |
19 | QEMUTimer *transfer_timer; | 18 | |
20 | - qemu_irq eject_cb; | 19 | - void *nvic; |
21 | - qemu_irq ro_cb; | 20 | #if !defined(CONFIG_USER_ONLY) |
22 | qemu_irq irq; | 21 | + void *nvic; |
23 | 22 | const struct arm_boot_info *boot_info; | |
24 | /* Registers cleared on reset */ | 23 | /* Store GICv3CPUState to access from this struct */ |
25 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 24 | void *gicv3state; |
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/hw/sd/sdhci.c | ||
28 | +++ b/hw/sd/sdhci.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static void sdhci_uninitfn(SDHCIState *s) | ||
30 | timer_free(s->insert_timer); | ||
31 | timer_del(s->transfer_timer); | ||
32 | timer_free(s->transfer_timer); | ||
33 | - qemu_free_irq(s->eject_cb); | ||
34 | - qemu_free_irq(s->ro_cb); | ||
35 | |||
36 | g_free(s->fifo_buffer); | ||
37 | s->fifo_buffer = NULL; | ||
38 | -- | 25 | -- |
39 | 2.7.4 | 26 | 2.34.1 |
40 | 27 | ||
41 | 28 | diff view generated by jsdifflib |
1 | The Configurable Fault Status Register for ARMv7M and v8M is | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | supposed to be byte and halfword accessible, but we were only | 2 | |
3 | implementing word accesses. Add support for the other access | 3 | There is no point in using a void pointer to access the NVIC. |
4 | sizes, which are used by the Zephyr RTOS. | 4 | Use the real type to avoid casting it while debugging. |
5 | 5 | ||
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20230206223502.25122-11-philmd@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reported-by: Andy Gross <andy.gross@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
9 | Message-id: 1512742372-31517-1-git-send-email-peter.maydell@linaro.org | ||
10 | --- | 10 | --- |
11 | hw/intc/armv7m_nvic.c | 38 ++++++++++++++++++++++---------------- | 11 | target/arm/cpu.h | 46 ++++++++++++++++++++++--------------------- |
12 | 1 file changed, 22 insertions(+), 16 deletions(-) | 12 | hw/intc/armv7m_nvic.c | 38 ++++++++++++----------------------- |
13 | 13 | target/arm/cpu.c | 1 + | |
14 | target/arm/m_helper.c | 2 +- | ||
15 | 4 files changed, 39 insertions(+), 48 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpu.h | ||
20 | +++ b/target/arm/cpu.h | ||
21 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMTBFlags { | ||
22 | |||
23 | typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; | ||
24 | |||
25 | +typedef struct NVICState NVICState; | ||
26 | + | ||
27 | typedef struct CPUArchState { | ||
28 | /* Regs for current mode. */ | ||
29 | uint32_t regs[16]; | ||
30 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState { | ||
31 | } sau; | ||
32 | |||
33 | #if !defined(CONFIG_USER_ONLY) | ||
34 | - void *nvic; | ||
35 | + NVICState *nvic; | ||
36 | const struct arm_boot_info *boot_info; | ||
37 | /* Store GICv3CPUState to access from this struct */ | ||
38 | void *gicv3state; | ||
39 | @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
40 | |||
41 | /* Interface between CPU and Interrupt controller. */ | ||
42 | #ifndef CONFIG_USER_ONLY | ||
43 | -bool armv7m_nvic_can_take_pending_exception(void *opaque); | ||
44 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
45 | #else | ||
46 | -static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
47 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
48 | { | ||
49 | return true; | ||
50 | } | ||
51 | #endif | ||
52 | /** | ||
53 | * armv7m_nvic_set_pending: mark the specified exception as pending | ||
54 | - * @opaque: the NVIC | ||
55 | + * @s: the NVIC | ||
56 | * @irq: the exception number to mark pending | ||
57 | * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | * version of a banked exception, true for the secure version of a banked | ||
59 | @@ -XXX,XX +XXX,XX @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
60 | * if @secure is true and @irq does not specify one of the fixed set | ||
61 | * of architecturally banked exceptions. | ||
62 | */ | ||
63 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
64 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
65 | /** | ||
66 | * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
67 | - * @opaque: the NVIC | ||
68 | + * @s: the NVIC | ||
69 | * @irq: the exception number to mark pending | ||
70 | * @secure: false for non-banked exceptions or for the nonsecure | ||
71 | * version of a banked exception, true for the secure version of a banked | ||
72 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | ||
73 | * exceptions (exceptions generated in the course of trying to take | ||
74 | * a different exception). | ||
75 | */ | ||
76 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
77 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
78 | /** | ||
79 | * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
80 | - * @opaque: the NVIC | ||
81 | + * @s: the NVIC | ||
82 | * @irq: the exception number to mark pending | ||
83 | * @secure: false for non-banked exceptions or for the nonsecure | ||
84 | * version of a banked exception, true for the secure version of a banked | ||
85 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | ||
86 | * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
87 | * generated in the course of lazy stacking of FP registers. | ||
88 | */ | ||
89 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
90 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
91 | /** | ||
92 | * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
93 | * exception, and whether it targets Secure state | ||
94 | - * @opaque: the NVIC | ||
95 | + * @s: the NVIC | ||
96 | * @pirq: set to pending exception number | ||
97 | * @ptargets_secure: set to whether pending exception targets Secure | ||
98 | * | ||
99 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | ||
100 | * to true if the current highest priority pending exception should | ||
101 | * be taken to Secure state, false for NS. | ||
102 | */ | ||
103 | -void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq, | ||
104 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
105 | bool *ptargets_secure); | ||
106 | /** | ||
107 | * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
108 | - * @opaque: the NVIC | ||
109 | + * @s: the NVIC | ||
110 | * | ||
111 | * Move the current highest priority pending exception from the pending | ||
112 | * state to the active state, and update v7m.exception to indicate that | ||
113 | * it is the exception currently being handled. | ||
114 | */ | ||
115 | -void armv7m_nvic_acknowledge_irq(void *opaque); | ||
116 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
117 | /** | ||
118 | * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
119 | - * @opaque: the NVIC | ||
120 | + * @s: the NVIC | ||
121 | * @irq: the exception number to complete | ||
122 | * @secure: true if this exception was secure | ||
123 | * | ||
124 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | ||
125 | * 0 if there is still an irq active after this one was completed | ||
126 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
127 | */ | ||
128 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
129 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
130 | /** | ||
131 | * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
132 | - * @opaque: the NVIC | ||
133 | + * @s: the NVIC | ||
134 | * @irq: the exception number to mark pending | ||
135 | * @secure: false for non-banked exceptions or for the nonsecure | ||
136 | * version of a banked exception, true for the secure version of a banked | ||
137 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | ||
138 | * interrupt the current execution priority. This controls whether the | ||
139 | * RDY bit for it in the FPCCR is set. | ||
140 | */ | ||
141 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); | ||
142 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
143 | /** | ||
144 | * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
145 | - * @opaque: the NVIC | ||
146 | + * @s: the NVIC | ||
147 | * | ||
148 | * Returns: the raw execution priority as defined by the v8M architecture. | ||
149 | * This is the execution priority minus the effects of AIRCR.PRIS, | ||
150 | * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
151 | * (v8M ARM ARM I_PKLD.) | ||
152 | */ | ||
153 | -int armv7m_nvic_raw_execution_priority(void *opaque); | ||
154 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
155 | /** | ||
156 | * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
157 | * priority is negative for the specified security state. | ||
158 | - * @opaque: the NVIC | ||
159 | + * @s: the NVIC | ||
160 | * @secure: the security state to test | ||
161 | * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
162 | */ | ||
163 | #ifndef CONFIG_USER_ONLY | ||
164 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); | ||
165 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
166 | #else | ||
167 | -static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) | ||
168 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
169 | { | ||
170 | return false; | ||
171 | } | ||
14 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 172 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c |
15 | index XXXXXXX..XXXXXXX 100644 | 173 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/intc/armv7m_nvic.c | 174 | --- a/hw/intc/armv7m_nvic.c |
17 | +++ b/hw/intc/armv7m_nvic.c | 175 | +++ b/hw/intc/armv7m_nvic.c |
18 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 176 | @@ -XXX,XX +XXX,XX @@ static inline int nvic_exec_prio(NVICState *s) |
19 | val |= (1 << 8); | 177 | return MIN(running, s->exception_prio); |
20 | } | 178 | } |
21 | return val; | 179 | |
22 | - case 0xd28: /* Configurable Fault Status. */ | 180 | -bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) |
23 | - /* The BFSR bits [15:8] are shared between security states | 181 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) |
24 | - * and we store them in the NS copy | 182 | { |
25 | - */ | 183 | /* Return true if the requested execution priority is negative |
26 | - val = cpu->env.v7m.cfsr[attrs.secure]; | 184 | * for the specified security state, ie that security state |
27 | - val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; | 185 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) |
28 | - return val; | 186 | * mean we don't allow FAULTMASK_NS to actually make the execution |
29 | case 0xd2c: /* Hard Fault Status. */ | 187 | * priority negative). Compare pseudocode IsReqExcPriNeg(). |
30 | return cpu->env.v7m.hfsr; | 188 | */ |
31 | case 0xd30: /* Debug Fault Status. */ | 189 | - NVICState *s = opaque; |
32 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | 190 | - |
33 | s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0; | 191 | if (s->cpu->env.v7m.faultmask[secure]) { |
34 | nvic_irq_update(s); | 192 | return true; |
35 | break; | ||
36 | - case 0xd28: /* Configurable Fault Status. */ | ||
37 | - cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */ | ||
38 | - if (attrs.secure) { | ||
39 | - /* The BFSR bits [15:8] are shared between security states | ||
40 | - * and we store them in the NS copy. | ||
41 | - */ | ||
42 | - cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); | ||
43 | - } | ||
44 | - break; | ||
45 | case 0xd2c: /* Hard Fault Status. */ | ||
46 | cpu->env.v7m.hfsr &= ~value; /* W1C */ | ||
47 | break; | ||
48 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, | ||
49 | val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank)); | ||
50 | } | ||
51 | break; | ||
52 | + case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ | ||
53 | + /* The BFSR bits [15:8] are shared between security states | ||
54 | + * and we store them in the NS copy | ||
55 | + */ | ||
56 | + val = s->cpu->env.v7m.cfsr[attrs.secure]; | ||
57 | + val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; | ||
58 | + val = extract32(val, (offset - 0xd28) * 8, size * 8); | ||
59 | + break; | ||
60 | case 0xfe0 ... 0xfff: /* ID. */ | ||
61 | if (offset & 3) { | ||
62 | val = 0; | ||
63 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, | ||
64 | } | ||
65 | nvic_irq_update(s); | ||
66 | return MEMTX_OK; | ||
67 | + case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ | ||
68 | + /* All bits are W1C, so construct 32 bit value with 0s in | ||
69 | + * the parts not written by the access size | ||
70 | + */ | ||
71 | + value <<= ((offset - 0xd28) * 8); | ||
72 | + | ||
73 | + s->cpu->env.v7m.cfsr[attrs.secure] &= ~value; | ||
74 | + if (attrs.secure) { | ||
75 | + /* The BFSR bits [15:8] are shared between security states | ||
76 | + * and we store them in the NS copy. | ||
77 | + */ | ||
78 | + s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK); | ||
79 | + } | ||
80 | + return MEMTX_OK; | ||
81 | } | 193 | } |
82 | if (size == 4) { | 194 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) |
83 | nvic_writel(s, offset, value, attrs); | 195 | return false; |
196 | } | ||
197 | |||
198 | -bool armv7m_nvic_can_take_pending_exception(void *opaque) | ||
199 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
200 | { | ||
201 | - NVICState *s = opaque; | ||
202 | - | ||
203 | return nvic_exec_prio(s) > nvic_pending_prio(s); | ||
204 | } | ||
205 | |||
206 | -int armv7m_nvic_raw_execution_priority(void *opaque) | ||
207 | +int armv7m_nvic_raw_execution_priority(NVICState *s) | ||
208 | { | ||
209 | - NVICState *s = opaque; | ||
210 | - | ||
211 | return s->exception_prio; | ||
212 | } | ||
213 | |||
214 | @@ -XXX,XX +XXX,XX @@ static void nvic_irq_update(NVICState *s) | ||
215 | * if @secure is true and @irq does not specify one of the fixed set | ||
216 | * of architecturally banked exceptions. | ||
217 | */ | ||
218 | -static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure) | ||
219 | +static void armv7m_nvic_clear_pending(NVICState *s, int irq, bool secure) | ||
220 | { | ||
221 | - NVICState *s = (NVICState *)opaque; | ||
222 | VecInfo *vec; | ||
223 | |||
224 | assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | ||
225 | @@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, | ||
226 | } | ||
227 | } | ||
228 | |||
229 | -void armv7m_nvic_set_pending(void *opaque, int irq, bool secure) | ||
230 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure) | ||
231 | { | ||
232 | - do_armv7m_nvic_set_pending(opaque, irq, secure, false); | ||
233 | + do_armv7m_nvic_set_pending(s, irq, secure, false); | ||
234 | } | ||
235 | |||
236 | -void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) | ||
237 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure) | ||
238 | { | ||
239 | - do_armv7m_nvic_set_pending(opaque, irq, secure, true); | ||
240 | + do_armv7m_nvic_set_pending(s, irq, secure, true); | ||
241 | } | ||
242 | |||
243 | -void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
244 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) | ||
245 | { | ||
246 | /* | ||
247 | * Pend an exception during lazy FP stacking. This differs | ||
248 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
249 | * whether we should escalate depends on the saved context | ||
250 | * in the FPCCR register, not on the current state of the CPU/NVIC. | ||
251 | */ | ||
252 | - NVICState *s = (NVICState *)opaque; | ||
253 | bool banked = exc_is_banked(irq); | ||
254 | VecInfo *vec; | ||
255 | bool targets_secure; | ||
256 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | ||
257 | } | ||
258 | |||
259 | /* Make pending IRQ active. */ | ||
260 | -void armv7m_nvic_acknowledge_irq(void *opaque) | ||
261 | +void armv7m_nvic_acknowledge_irq(NVICState *s) | ||
262 | { | ||
263 | - NVICState *s = (NVICState *)opaque; | ||
264 | CPUARMState *env = &s->cpu->env; | ||
265 | const int pending = s->vectpending; | ||
266 | const int running = nvic_exec_prio(s); | ||
267 | @@ -XXX,XX +XXX,XX @@ static bool vectpending_targets_secure(NVICState *s) | ||
268 | exc_targets_secure(s, s->vectpending); | ||
269 | } | ||
270 | |||
271 | -void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
272 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, | ||
273 | int *pirq, bool *ptargets_secure) | ||
274 | { | ||
275 | - NVICState *s = (NVICState *)opaque; | ||
276 | const int pending = s->vectpending; | ||
277 | bool targets_secure; | ||
278 | |||
279 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_get_pending_irq_info(void *opaque, | ||
280 | *pirq = pending; | ||
281 | } | ||
282 | |||
283 | -int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
284 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure) | ||
285 | { | ||
286 | - NVICState *s = (NVICState *)opaque; | ||
287 | VecInfo *vec = NULL; | ||
288 | int ret = 0; | ||
289 | |||
290 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | ||
291 | return ret; | ||
292 | } | ||
293 | |||
294 | -bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
295 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure) | ||
296 | { | ||
297 | /* | ||
298 | * Return whether an exception is "ready", i.e. it is enabled and is | ||
299 | @@ -XXX,XX +XXX,XX @@ bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
300 | * for non-banked exceptions secure is always false; for banked exceptions | ||
301 | * it indicates which of the exceptions is required. | ||
302 | */ | ||
303 | - NVICState *s = (NVICState *)opaque; | ||
304 | bool banked = exc_is_banked(irq); | ||
305 | VecInfo *vec; | ||
306 | int running = nvic_exec_prio(s); | ||
307 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
308 | index XXXXXXX..XXXXXXX 100644 | ||
309 | --- a/target/arm/cpu.c | ||
310 | +++ b/target/arm/cpu.c | ||
311 | @@ -XXX,XX +XXX,XX @@ | ||
312 | #if !defined(CONFIG_USER_ONLY) | ||
313 | #include "hw/loader.h" | ||
314 | #include "hw/boards.h" | ||
315 | +#include "hw/intc/armv7m_nvic.h" | ||
316 | #endif | ||
317 | #include "sysemu/tcg.h" | ||
318 | #include "sysemu/qtest.h" | ||
319 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
320 | index XXXXXXX..XXXXXXX 100644 | ||
321 | --- a/target/arm/m_helper.c | ||
322 | +++ b/target/arm/m_helper.c | ||
323 | @@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, | ||
324 | * that we will need later in order to do lazy FP reg stacking. | ||
325 | */ | ||
326 | bool is_secure = env->v7m.secure; | ||
327 | - void *nvic = env->nvic; | ||
328 | + NVICState *nvic = env->nvic; | ||
329 | /* | ||
330 | * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits | ||
331 | * are banked and we want to update the bit in the bank for the | ||
84 | -- | 332 | -- |
85 | 2.7.4 | 333 | 2.34.1 |
86 | 334 | ||
87 | 335 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | zero-initialize ADMADescr 'dscr' in sdhci_do_adma() to avoid: | 3 | While dozens of files include "cpu.h", only 3 files require |
4 | 4 | these NVIC helper declarations. | |
5 | hw/sd/sdhci.c: In function ‘sdhci_do_adma’: | 5 | |
6 | hw/sd/sdhci.c:714:29: error: ‘dscr.addr’ may be used uninitialized in this function [-Werror=maybe-uninitialized] | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | trace_sdhci_adma("link", s->admasysaddr); | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | ^ | 8 | Message-id: 20230206223502.25122-12-philmd@linaro.org |
9 | |||
10 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Acked-by: Alistair Francis <alistair.francis@xilinx.com> | ||
12 | Message-id: 20180115182436.2066-9-f4bug@amsat.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 10 | --- |
15 | hw/sd/sdhci.c | 89 ++++++++++++++++++------------------------------------ | 11 | include/hw/intc/armv7m_nvic.h | 123 ++++++++++++++++++++++++++++++++++ |
16 | hw/sd/trace-events | 14 +++++++++ | 12 | target/arm/cpu.h | 123 ---------------------------------- |
17 | 2 files changed, 44 insertions(+), 59 deletions(-) | 13 | target/arm/cpu.c | 4 +- |
18 | 14 | target/arm/cpu_tcg.c | 3 + | |
19 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 15 | target/arm/m_helper.c | 3 + |
20 | index XXXXXXX..XXXXXXX 100644 | 16 | 5 files changed, 132 insertions(+), 124 deletions(-) |
21 | --- a/hw/sd/sdhci.c | 17 | |
22 | +++ b/hw/sd/sdhci.c | 18 | diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h |
23 | @@ -XXX,XX +XXX,XX @@ | 19 | index XXXXXXX..XXXXXXX 100644 |
24 | #include "sdhci-internal.h" | 20 | --- a/include/hw/intc/armv7m_nvic.h |
25 | #include "qapi/error.h" | 21 | +++ b/include/hw/intc/armv7m_nvic.h |
26 | #include "qemu/log.h" | 22 | @@ -XXX,XX +XXX,XX @@ struct NVICState { |
27 | - | 23 | qemu_irq sysresetreq; |
28 | -/* host controller debug messages */ | 24 | }; |
29 | -#ifndef SDHC_DEBUG | 25 | |
30 | -#define SDHC_DEBUG 0 | 26 | +/* Interface between CPU and Interrupt controller. */ |
27 | +/** | ||
28 | + * armv7m_nvic_set_pending: mark the specified exception as pending | ||
29 | + * @s: the NVIC | ||
30 | + * @irq: the exception number to mark pending | ||
31 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
32 | + * version of a banked exception, true for the secure version of a banked | ||
33 | + * exception. | ||
34 | + * | ||
35 | + * Marks the specified exception as pending. Note that we will assert() | ||
36 | + * if @secure is true and @irq does not specify one of the fixed set | ||
37 | + * of architecturally banked exceptions. | ||
38 | + */ | ||
39 | +void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
40 | +/** | ||
41 | + * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
42 | + * @s: the NVIC | ||
43 | + * @irq: the exception number to mark pending | ||
44 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
45 | + * version of a banked exception, true for the secure version of a banked | ||
46 | + * exception. | ||
47 | + * | ||
48 | + * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
49 | + * exceptions (exceptions generated in the course of trying to take | ||
50 | + * a different exception). | ||
51 | + */ | ||
52 | +void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
53 | +/** | ||
54 | + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
55 | + * @s: the NVIC | ||
56 | + * @irq: the exception number to mark pending | ||
57 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
58 | + * version of a banked exception, true for the secure version of a banked | ||
59 | + * exception. | ||
60 | + * | ||
61 | + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
62 | + * generated in the course of lazy stacking of FP registers. | ||
63 | + */ | ||
64 | +void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
65 | +/** | ||
66 | + * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
67 | + * exception, and whether it targets Secure state | ||
68 | + * @s: the NVIC | ||
69 | + * @pirq: set to pending exception number | ||
70 | + * @ptargets_secure: set to whether pending exception targets Secure | ||
71 | + * | ||
72 | + * This function writes the number of the highest priority pending | ||
73 | + * exception (the one which would be made active by | ||
74 | + * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
75 | + * to true if the current highest priority pending exception should | ||
76 | + * be taken to Secure state, false for NS. | ||
77 | + */ | ||
78 | +void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
79 | + bool *ptargets_secure); | ||
80 | +/** | ||
81 | + * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
82 | + * @s: the NVIC | ||
83 | + * | ||
84 | + * Move the current highest priority pending exception from the pending | ||
85 | + * state to the active state, and update v7m.exception to indicate that | ||
86 | + * it is the exception currently being handled. | ||
87 | + */ | ||
88 | +void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
89 | +/** | ||
90 | + * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
91 | + * @s: the NVIC | ||
92 | + * @irq: the exception number to complete | ||
93 | + * @secure: true if this exception was secure | ||
94 | + * | ||
95 | + * Returns: -1 if the irq was not active | ||
96 | + * 1 if completing this irq brought us back to base (no active irqs) | ||
97 | + * 0 if there is still an irq active after this one was completed | ||
98 | + * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
99 | + */ | ||
100 | +int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
101 | +/** | ||
102 | + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
103 | + * @s: the NVIC | ||
104 | + * @irq: the exception number to mark pending | ||
105 | + * @secure: false for non-banked exceptions or for the nonsecure | ||
106 | + * version of a banked exception, true for the secure version of a banked | ||
107 | + * exception. | ||
108 | + * | ||
109 | + * Return whether an exception is "ready", i.e. whether the exception is | ||
110 | + * enabled and is configured at a priority which would allow it to | ||
111 | + * interrupt the current execution priority. This controls whether the | ||
112 | + * RDY bit for it in the FPCCR is set. | ||
113 | + */ | ||
114 | +bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
115 | +/** | ||
116 | + * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
117 | + * @s: the NVIC | ||
118 | + * | ||
119 | + * Returns: the raw execution priority as defined by the v8M architecture. | ||
120 | + * This is the execution priority minus the effects of AIRCR.PRIS, | ||
121 | + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
122 | + * (v8M ARM ARM I_PKLD.) | ||
123 | + */ | ||
124 | +int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
125 | +/** | ||
126 | + * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
127 | + * priority is negative for the specified security state. | ||
128 | + * @s: the NVIC | ||
129 | + * @secure: the security state to test | ||
130 | + * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
131 | + */ | ||
132 | +#ifndef CONFIG_USER_ONLY | ||
133 | +bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
134 | +#else | ||
135 | +static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
136 | +{ | ||
137 | + return false; | ||
138 | +} | ||
139 | +#endif | ||
140 | +#ifndef CONFIG_USER_ONLY | ||
141 | +bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
142 | +#else | ||
143 | +static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
144 | +{ | ||
145 | + return true; | ||
146 | +} | ||
147 | +#endif | ||
148 | + | ||
149 | #endif | ||
150 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/target/arm/cpu.h | ||
153 | +++ b/target/arm/cpu.h | ||
154 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
155 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
156 | uint32_t cur_el, bool secure); | ||
157 | |||
158 | -/* Interface between CPU and Interrupt controller. */ | ||
159 | -#ifndef CONFIG_USER_ONLY | ||
160 | -bool armv7m_nvic_can_take_pending_exception(NVICState *s); | ||
161 | -#else | ||
162 | -static inline bool armv7m_nvic_can_take_pending_exception(NVICState *s) | ||
163 | -{ | ||
164 | - return true; | ||
165 | -} | ||
166 | -#endif | ||
167 | -/** | ||
168 | - * armv7m_nvic_set_pending: mark the specified exception as pending | ||
169 | - * @s: the NVIC | ||
170 | - * @irq: the exception number to mark pending | ||
171 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
172 | - * version of a banked exception, true for the secure version of a banked | ||
173 | - * exception. | ||
174 | - * | ||
175 | - * Marks the specified exception as pending. Note that we will assert() | ||
176 | - * if @secure is true and @irq does not specify one of the fixed set | ||
177 | - * of architecturally banked exceptions. | ||
178 | - */ | ||
179 | -void armv7m_nvic_set_pending(NVICState *s, int irq, bool secure); | ||
180 | -/** | ||
181 | - * armv7m_nvic_set_pending_derived: mark this derived exception as pending | ||
182 | - * @s: the NVIC | ||
183 | - * @irq: the exception number to mark pending | ||
184 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
185 | - * version of a banked exception, true for the secure version of a banked | ||
186 | - * exception. | ||
187 | - * | ||
188 | - * Similar to armv7m_nvic_set_pending(), but specifically for derived | ||
189 | - * exceptions (exceptions generated in the course of trying to take | ||
190 | - * a different exception). | ||
191 | - */ | ||
192 | -void armv7m_nvic_set_pending_derived(NVICState *s, int irq, bool secure); | ||
193 | -/** | ||
194 | - * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | ||
195 | - * @s: the NVIC | ||
196 | - * @irq: the exception number to mark pending | ||
197 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
198 | - * version of a banked exception, true for the secure version of a banked | ||
199 | - * exception. | ||
200 | - * | ||
201 | - * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | ||
202 | - * generated in the course of lazy stacking of FP registers. | ||
203 | - */ | ||
204 | -void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure); | ||
205 | -/** | ||
206 | - * armv7m_nvic_get_pending_irq_info: return highest priority pending | ||
207 | - * exception, and whether it targets Secure state | ||
208 | - * @s: the NVIC | ||
209 | - * @pirq: set to pending exception number | ||
210 | - * @ptargets_secure: set to whether pending exception targets Secure | ||
211 | - * | ||
212 | - * This function writes the number of the highest priority pending | ||
213 | - * exception (the one which would be made active by | ||
214 | - * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure | ||
215 | - * to true if the current highest priority pending exception should | ||
216 | - * be taken to Secure state, false for NS. | ||
217 | - */ | ||
218 | -void armv7m_nvic_get_pending_irq_info(NVICState *s, int *pirq, | ||
219 | - bool *ptargets_secure); | ||
220 | -/** | ||
221 | - * armv7m_nvic_acknowledge_irq: make highest priority pending exception active | ||
222 | - * @s: the NVIC | ||
223 | - * | ||
224 | - * Move the current highest priority pending exception from the pending | ||
225 | - * state to the active state, and update v7m.exception to indicate that | ||
226 | - * it is the exception currently being handled. | ||
227 | - */ | ||
228 | -void armv7m_nvic_acknowledge_irq(NVICState *s); | ||
229 | -/** | ||
230 | - * armv7m_nvic_complete_irq: complete specified interrupt or exception | ||
231 | - * @s: the NVIC | ||
232 | - * @irq: the exception number to complete | ||
233 | - * @secure: true if this exception was secure | ||
234 | - * | ||
235 | - * Returns: -1 if the irq was not active | ||
236 | - * 1 if completing this irq brought us back to base (no active irqs) | ||
237 | - * 0 if there is still an irq active after this one was completed | ||
238 | - * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | ||
239 | - */ | ||
240 | -int armv7m_nvic_complete_irq(NVICState *s, int irq, bool secure); | ||
241 | -/** | ||
242 | - * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | ||
243 | - * @s: the NVIC | ||
244 | - * @irq: the exception number to mark pending | ||
245 | - * @secure: false for non-banked exceptions or for the nonsecure | ||
246 | - * version of a banked exception, true for the secure version of a banked | ||
247 | - * exception. | ||
248 | - * | ||
249 | - * Return whether an exception is "ready", i.e. whether the exception is | ||
250 | - * enabled and is configured at a priority which would allow it to | ||
251 | - * interrupt the current execution priority. This controls whether the | ||
252 | - * RDY bit for it in the FPCCR is set. | ||
253 | - */ | ||
254 | -bool armv7m_nvic_get_ready_status(NVICState *s, int irq, bool secure); | ||
255 | -/** | ||
256 | - * armv7m_nvic_raw_execution_priority: return the raw execution priority | ||
257 | - * @s: the NVIC | ||
258 | - * | ||
259 | - * Returns: the raw execution priority as defined by the v8M architecture. | ||
260 | - * This is the execution priority minus the effects of AIRCR.PRIS, | ||
261 | - * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. | ||
262 | - * (v8M ARM ARM I_PKLD.) | ||
263 | - */ | ||
264 | -int armv7m_nvic_raw_execution_priority(NVICState *s); | ||
265 | -/** | ||
266 | - * armv7m_nvic_neg_prio_requested: return true if the requested execution | ||
267 | - * priority is negative for the specified security state. | ||
268 | - * @s: the NVIC | ||
269 | - * @secure: the security state to test | ||
270 | - * This corresponds to the pseudocode IsReqExecPriNeg(). | ||
271 | - */ | ||
272 | -#ifndef CONFIG_USER_ONLY | ||
273 | -bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure); | ||
274 | -#else | ||
275 | -static inline bool armv7m_nvic_neg_prio_requested(NVICState *s, bool secure) | ||
276 | -{ | ||
277 | - return false; | ||
278 | -} | ||
31 | -#endif | 279 | -#endif |
32 | - | 280 | - |
33 | -#define DPRINT_L1(fmt, args...) \ | 281 | /* Interface for defining coprocessor registers. |
34 | - do { \ | 282 | * Registers are defined in tables of arm_cp_reginfo structs |
35 | - if (SDHC_DEBUG) { \ | 283 | * which are passed to define_arm_cp_regs(). |
36 | - fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ | 284 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
37 | - } \ | 285 | index XXXXXXX..XXXXXXX 100644 |
38 | - } while (0) | 286 | --- a/target/arm/cpu.c |
39 | -#define DPRINT_L2(fmt, args...) \ | 287 | +++ b/target/arm/cpu.c |
40 | - do { \ | ||
41 | - if (SDHC_DEBUG > 1) { \ | ||
42 | - fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ | ||
43 | - } \ | ||
44 | - } while (0) | ||
45 | -#define ERRPRINT(fmt, args...) \ | ||
46 | - do { \ | ||
47 | - if (SDHC_DEBUG) { \ | ||
48 | - fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \ | ||
49 | - } \ | ||
50 | - } while (0) | ||
51 | +#include "trace.h" | ||
52 | |||
53 | #define TYPE_SDHCI_BUS "sdhci-bus" | ||
54 | #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) | ||
55 | @@ -XXX,XX +XXX,XX @@ static void sdhci_raise_insertion_irq(void *opaque) | ||
56 | static void sdhci_set_inserted(DeviceState *dev, bool level) | ||
57 | { | ||
58 | SDHCIState *s = (SDHCIState *)dev; | ||
59 | - DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); | ||
60 | |||
61 | + trace_sdhci_set_inserted(level ? "insert" : "eject"); | ||
62 | if ((s->norintsts & SDHC_NIS_REMOVE) && level) { | ||
63 | /* Give target some time to notice card ejection */ | ||
64 | timer_mod(s->insert_timer, | ||
65 | @@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s) | ||
66 | s->acmd12errsts = 0; | ||
67 | request.cmd = s->cmdreg >> 8; | ||
68 | request.arg = s->argument; | ||
69 | - DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg); | ||
70 | + | ||
71 | + trace_sdhci_send_command(request.cmd, request.arg); | ||
72 | rlen = sdbus_do_command(&s->sdbus, &request, response); | ||
73 | |||
74 | if (s->cmdreg & SDHC_CMD_RESPONSE) { | ||
75 | @@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s) | ||
76 | s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | | ||
77 | (response[2] << 8) | response[3]; | ||
78 | s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; | ||
79 | - DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]); | ||
80 | + trace_sdhci_response4(s->rspreg[0]); | ||
81 | } else if (rlen == 16) { | ||
82 | s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | | ||
83 | (response[13] << 8) | response[14]; | ||
84 | @@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s) | ||
85 | (response[5] << 8) | response[6]; | ||
86 | s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | | ||
87 | response[2]; | ||
88 | - DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.." | ||
89 | - "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n", | ||
90 | - s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); | ||
91 | + trace_sdhci_response16(s->rspreg[3], s->rspreg[2], | ||
92 | + s->rspreg[1], s->rspreg[0]); | ||
93 | } else { | ||
94 | - ERRPRINT("Timeout waiting for command response\n"); | ||
95 | + trace_sdhci_error("timeout waiting for command response"); | ||
96 | if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { | ||
97 | s->errintsts |= SDHC_EIS_CMDTIMEOUT; | ||
98 | s->norintsts |= SDHC_NIS_ERR; | ||
99 | @@ -XXX,XX +XXX,XX @@ static void sdhci_end_transfer(SDHCIState *s) | ||
100 | |||
101 | request.cmd = 0x0C; | ||
102 | request.arg = 0; | ||
103 | - DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg); | ||
104 | + trace_sdhci_end_transfer(request.cmd, request.arg); | ||
105 | sdbus_do_command(&s->sdbus, &request, response); | ||
106 | /* Auto CMD12 response goes to the upper Response register */ | ||
107 | s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | | ||
108 | @@ -XXX,XX +XXX,XX @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) | ||
109 | |||
110 | /* first check that a valid data exists in host controller input buffer */ | ||
111 | if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { | ||
112 | - ERRPRINT("Trying to read from empty buffer\n"); | ||
113 | + trace_sdhci_error("read from empty buffer"); | ||
114 | return 0; | ||
115 | } | ||
116 | |||
117 | @@ -XXX,XX +XXX,XX @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) | ||
118 | s->data_count++; | ||
119 | /* check if we've read all valid data (blksize bytes) from buffer */ | ||
120 | if ((s->data_count) >= (s->blksize & 0x0fff)) { | ||
121 | - DPRINT_L2("All %u bytes of data have been read from input buffer\n", | ||
122 | - s->data_count); | ||
123 | + trace_sdhci_read_dataport(s->data_count); | ||
124 | s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ | ||
125 | s->data_count = 0; /* next buff read must start at position [0] */ | ||
126 | |||
127 | @@ -XXX,XX +XXX,XX @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) | ||
128 | |||
129 | /* Check that there is free space left in a buffer */ | ||
130 | if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { | ||
131 | - ERRPRINT("Can't write to data buffer: buffer full\n"); | ||
132 | + trace_sdhci_error("Can't write to data buffer: buffer full"); | ||
133 | return; | ||
134 | } | ||
135 | |||
136 | @@ -XXX,XX +XXX,XX @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) | ||
137 | s->data_count++; | ||
138 | value >>= 8; | ||
139 | if (s->data_count >= (s->blksize & 0x0fff)) { | ||
140 | - DPRINT_L2("write buffer filled with %u bytes of data\n", | ||
141 | - s->data_count); | ||
142 | + trace_sdhci_write_dataport(s->data_count); | ||
143 | s->data_count = 0; | ||
144 | s->prnsts &= ~SDHC_SPACE_AVAILABLE; | ||
145 | if (s->prnsts & SDHC_DOING_WRITE) { | ||
146 | @@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s) | ||
147 | { | ||
148 | unsigned int n, begin, length; | ||
149 | const uint16_t block_size = s->blksize & 0x0fff; | ||
150 | - ADMADescr dscr; | ||
151 | + ADMADescr dscr = {}; | ||
152 | int i; | ||
153 | |||
154 | for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { | ||
155 | s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; | ||
156 | |||
157 | get_adma_description(s, &dscr); | ||
158 | - DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n", | ||
159 | - dscr.addr, dscr.length, dscr.attr); | ||
160 | + trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); | ||
161 | |||
162 | if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { | ||
163 | /* Indicate that error occurred in ST_FDS state */ | ||
164 | @@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s) | ||
165 | break; | ||
166 | case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ | ||
167 | s->admasysaddr = dscr.addr; | ||
168 | - DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n", | ||
169 | - s->admasysaddr); | ||
170 | + trace_sdhci_adma("link", s->admasysaddr); | ||
171 | break; | ||
172 | default: | ||
173 | s->admasysaddr += dscr.incr; | ||
174 | @@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s) | ||
175 | } | ||
176 | |||
177 | if (dscr.attr & SDHC_ADMA_ATTR_INT) { | ||
178 | - DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n", | ||
179 | - s->admasysaddr); | ||
180 | + trace_sdhci_adma("interrupt", s->admasysaddr); | ||
181 | if (s->norintstsen & SDHC_NISEN_DMA) { | ||
182 | s->norintsts |= SDHC_NIS_DMA; | ||
183 | } | ||
184 | @@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s) | ||
185 | /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ | ||
186 | if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && | ||
187 | (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { | ||
188 | - DPRINT_L2("ADMA transfer completed\n"); | ||
189 | + trace_sdhci_adma_transfer_completed(); | ||
190 | if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && | ||
191 | (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && | ||
192 | s->blkcnt != 0)) { | ||
193 | - ERRPRINT("SD/MMC host ADMA length mismatch\n"); | ||
194 | + trace_sdhci_error("SD/MMC host ADMA length mismatch"); | ||
195 | s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | | ||
196 | SDHC_ADMAERR_STATE_ST_TFR; | ||
197 | if (s->errintstsen & SDHC_EISEN_ADMAERR) { | ||
198 | - ERRPRINT("Set ADMA error flag\n"); | ||
199 | + trace_sdhci_error("Set ADMA error flag"); | ||
200 | s->errintsts |= SDHC_EIS_ADMAERR; | ||
201 | s->norintsts |= SDHC_NIS_ERR; | ||
202 | } | ||
203 | @@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque) | ||
204 | break; | ||
205 | case SDHC_CTRL_ADMA1_32: | ||
206 | if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { | ||
207 | - ERRPRINT("ADMA1 not supported\n"); | ||
208 | + trace_sdhci_error("ADMA1 not supported"); | ||
209 | break; | ||
210 | } | ||
211 | |||
212 | @@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque) | ||
213 | break; | ||
214 | case SDHC_CTRL_ADMA2_32: | ||
215 | if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { | ||
216 | - ERRPRINT("ADMA2 not supported\n"); | ||
217 | + trace_sdhci_error("ADMA2 not supported"); | ||
218 | break; | ||
219 | } | ||
220 | |||
221 | @@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque) | ||
222 | case SDHC_CTRL_ADMA2_64: | ||
223 | if (!(s->capareg & SDHC_CAN_DO_ADMA2) || | ||
224 | !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { | ||
225 | - ERRPRINT("64 bit ADMA not supported\n"); | ||
226 | + trace_sdhci_error("64 bit ADMA not supported"); | ||
227 | break; | ||
228 | } | ||
229 | |||
230 | sdhci_do_adma(s); | ||
231 | break; | ||
232 | default: | ||
233 | - ERRPRINT("Unsupported DMA type\n"); | ||
234 | + trace_sdhci_error("Unsupported DMA type"); | ||
235 | break; | ||
236 | } | ||
237 | } else { | ||
238 | @@ -XXX,XX +XXX,XX @@ static inline bool | ||
239 | sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) | ||
240 | { | ||
241 | if ((s->data_count & 0x3) != byte_num) { | ||
242 | - ERRPRINT("Non-sequential access to Buffer Data Port register" | ||
243 | - "is prohibited\n"); | ||
244 | + trace_sdhci_error("Non-sequential access to Buffer Data Port register" | ||
245 | + "is prohibited\n"); | ||
246 | return false; | ||
247 | } | ||
248 | return true; | ||
249 | @@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) | ||
250 | case SDHC_BDATA: | ||
251 | if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { | ||
252 | ret = sdhci_read_dataport(s, size); | ||
253 | - DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, | ||
254 | - ret, ret); | ||
255 | + trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); | ||
256 | return ret; | ||
257 | } | ||
258 | break; | ||
259 | @@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) | ||
260 | |||
261 | ret >>= (offset & 0x3) * 8; | ||
262 | ret &= (1ULL << (size * 8)) - 1; | ||
263 | - DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret); | ||
264 | + trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); | ||
265 | return ret; | ||
266 | } | ||
267 | |||
268 | @@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) | ||
269 | "not implemented\n", size, offset, value >> shift); | ||
270 | break; | ||
271 | } | ||
272 | - DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", | ||
273 | - size, (int)offset, value >> shift, value >> shift); | ||
274 | + trace_sdhci_access("wr", size << 3, offset, "<-", | ||
275 | + value >> shift, value >> shift); | ||
276 | } | ||
277 | |||
278 | static const MemoryRegionOps sdhci_mmio_ops = { | ||
279 | diff --git a/hw/sd/trace-events b/hw/sd/trace-events | ||
280 | index XXXXXXX..XXXXXXX 100644 | ||
281 | --- a/hw/sd/trace-events | ||
282 | +++ b/hw/sd/trace-events | ||
283 | @@ -XXX,XX +XXX,XX @@ | 288 | @@ -XXX,XX +XXX,XX @@ |
284 | # See docs/devel/tracing.txt for syntax documentation. | 289 | #if !defined(CONFIG_USER_ONLY) |
285 | 290 | #include "hw/loader.h" | |
286 | +# hw/sd/sdhci.c | 291 | #include "hw/boards.h" |
287 | +sdhci_set_inserted(const char *level) "card state changed: %s" | 292 | +#ifdef CONFIG_TCG |
288 | +sdhci_send_command(uint8_t cmd, uint32_t arg) "CMD%02u ARG[0x%08x]" | 293 | #include "hw/intc/armv7m_nvic.h" |
289 | +sdhci_error(const char *msg) "%s" | 294 | -#endif |
290 | +sdhci_response4(uint32_t r0) "RSPREG[31..0]=0x%08x" | 295 | +#endif /* CONFIG_TCG */ |
291 | +sdhci_response16(uint32_t r3, uint32_t r2, uint32_t r1, uint32_t r0) "RSPREG[127..96]=0x%08x, RSPREG[95..64]=0x%08x, RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x" | 296 | +#endif /* !CONFIG_USER_ONLY */ |
292 | +sdhci_end_transfer(uint8_t cmd, uint32_t arg) "Automatically issue CMD%02u 0x%08x" | 297 | #include "sysemu/tcg.h" |
293 | +sdhci_adma(const char *desc, uint32_t sysad) "%s: admasysaddr=0x%" PRIx32 | 298 | #include "sysemu/qtest.h" |
294 | +sdhci_adma_loop(uint64_t addr, uint16_t length, uint8_t attr) "addr=0x%08" PRIx64 ", len=%d, attr=0x%x" | 299 | #include "sysemu/hw_accel.h" |
295 | +sdhci_adma_transfer_completed(void) "" | 300 | diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c |
296 | +sdhci_access(const char *access, unsigned int size, uint64_t offset, const char *dir, uint64_t val, uint64_t val2) "%s%u: addr[0x%04" PRIx64 "] %s 0x%08" PRIx64 " (%" PRIu64 ")" | 301 | index XXXXXXX..XXXXXXX 100644 |
297 | +sdhci_read_dataport(uint16_t data_count) "all %u bytes of data have been read from input buffer" | 302 | --- a/target/arm/cpu_tcg.c |
298 | +sdhci_write_dataport(uint16_t data_count) "write buffer filled with %u bytes of data" | 303 | +++ b/target/arm/cpu_tcg.c |
299 | + | 304 | @@ -XXX,XX +XXX,XX @@ |
300 | # hw/sd/milkymist-memcard.c | 305 | #include "hw/boards.h" |
301 | milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" | 306 | #endif |
302 | milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" | 307 | #include "cpregs.h" |
308 | +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) | ||
309 | +#include "hw/intc/armv7m_nvic.h" | ||
310 | +#endif | ||
311 | |||
312 | |||
313 | /* Share AArch32 -cpu max features with AArch64. */ | ||
314 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c | ||
315 | index XXXXXXX..XXXXXXX 100644 | ||
316 | --- a/target/arm/m_helper.c | ||
317 | +++ b/target/arm/m_helper.c | ||
318 | @@ -XXX,XX +XXX,XX @@ | ||
319 | #include "exec/cpu_ldst.h" | ||
320 | #include "semihosting/common-semi.h" | ||
321 | #endif | ||
322 | +#if !defined(CONFIG_USER_ONLY) | ||
323 | +#include "hw/intc/armv7m_nvic.h" | ||
324 | +#endif | ||
325 | |||
326 | static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, | ||
327 | uint32_t reg, uint32_t val) | ||
303 | -- | 328 | -- |
304 | 2.7.4 | 329 | 2.34.1 |
305 | 330 | ||
306 | 331 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | From: Alex Bennée <alex.bennee@linaro.org> | |
2 | |||
3 | The two TCG tests for GICv2 and GICv3 are very heavy weight distros | ||
4 | that take a long time to boot up, especially for an --enable-debug | ||
5 | build. The total code coverage they give is: | ||
6 | |||
7 | Overall coverage rate: | ||
8 | lines......: 11.2% (59584 of 530123 lines) | ||
9 | functions..: 15.0% (7436 of 49443 functions) | ||
10 | branches...: 6.3% (19273 of 303933 branches) | ||
11 | |||
12 | We already get pretty close to that with the machine_aarch64_virt | ||
13 | tests which only does one full boot (~120s vs ~600s) of alpine. We | ||
14 | expand the kernel+initrd boot (~8s) to test both GICs and also add an | ||
15 | RNG device and a block device to generate a few IRQs and exercise the | ||
16 | storage layer. With that we get to a coverage of: | ||
17 | |||
18 | Overall coverage rate: | ||
19 | lines......: 11.0% (58121 of 530123 lines) | ||
20 | functions..: 14.9% (7343 of 49443 functions) | ||
21 | branches...: 6.0% (18269 of 303933 branches) | ||
22 | |||
23 | which I feel is close enough given the massive time saving. If we want | ||
24 | to target any more sub-systems we can use lighter weight more directed | ||
25 | tests. | ||
26 | |||
27 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
28 | Reviewed-by: Fabiano Rosas <farosas@suse.de> | ||
29 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
30 | Message-id: 20230203181632.2919715-1-alex.bennee@linaro.org | ||
31 | Cc: Peter Maydell <peter.maydell@linaro.org> | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
33 | --- | ||
34 | tests/avocado/boot_linux.py | 48 ++++---------------- | ||
35 | tests/avocado/machine_aarch64_virt.py | 63 ++++++++++++++++++++++++--- | ||
36 | 2 files changed, 65 insertions(+), 46 deletions(-) | ||
37 | |||
38 | diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/tests/avocado/boot_linux.py | ||
41 | +++ b/tests/avocado/boot_linux.py | ||
42 | @@ -XXX,XX +XXX,XX @@ def test_pc_q35_kvm(self): | ||
43 | self.launch_and_wait(set_up_ssh_connection=False) | ||
44 | |||
45 | |||
46 | -# For Aarch64 we only boot KVM tests in CI as the TCG tests are very | ||
47 | -# heavyweight. There are lighter weight distros which we use in the | ||
48 | -# machine_aarch64_virt.py tests. | ||
49 | +# For Aarch64 we only boot KVM tests in CI as booting the current | ||
50 | +# Fedora OS in TCG tests is very heavyweight. There are lighter weight | ||
51 | +# distros which we use in the machine_aarch64_virt.py tests. | ||
52 | class BootLinuxAarch64(LinuxTest): | ||
53 | """ | ||
54 | :avocado: tags=arch:aarch64 | ||
55 | :avocado: tags=machine:virt | ||
56 | - :avocado: tags=machine:gic-version=2 | ||
57 | """ | ||
58 | timeout = 720 | ||
59 | |||
60 | - def add_common_args(self): | ||
61 | - self.vm.add_args('-bios', | ||
62 | - os.path.join(BUILD_DIR, 'pc-bios', | ||
63 | - 'edk2-aarch64-code.fd')) | ||
64 | - self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
65 | - self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
66 | - | ||
67 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
68 | - def test_fedora_cloud_tcg_gicv2(self): | ||
69 | - """ | ||
70 | - :avocado: tags=accel:tcg | ||
71 | - :avocado: tags=cpu:max | ||
72 | - :avocado: tags=device:gicv2 | ||
73 | - """ | ||
74 | - self.require_accelerator("tcg") | ||
75 | - self.vm.add_args("-accel", "tcg") | ||
76 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
77 | - self.vm.add_args("-machine", "virt,gic-version=2") | ||
78 | - self.add_common_args() | ||
79 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
80 | - | ||
81 | - @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') | ||
82 | - def test_fedora_cloud_tcg_gicv3(self): | ||
83 | - """ | ||
84 | - :avocado: tags=accel:tcg | ||
85 | - :avocado: tags=cpu:max | ||
86 | - :avocado: tags=device:gicv3 | ||
87 | - """ | ||
88 | - self.require_accelerator("tcg") | ||
89 | - self.vm.add_args("-accel", "tcg") | ||
90 | - self.vm.add_args("-cpu", "max,lpa2=off") | ||
91 | - self.vm.add_args("-machine", "virt,gic-version=3") | ||
92 | - self.add_common_args() | ||
93 | - self.launch_and_wait(set_up_ssh_connection=False) | ||
94 | - | ||
95 | def test_virt_kvm(self): | ||
96 | """ | ||
97 | :avocado: tags=accel:kvm | ||
98 | @@ -XXX,XX +XXX,XX @@ def test_virt_kvm(self): | ||
99 | self.require_accelerator("kvm") | ||
100 | self.vm.add_args("-accel", "kvm") | ||
101 | self.vm.add_args("-machine", "virt,gic-version=host") | ||
102 | - self.add_common_args() | ||
103 | + self.vm.add_args('-bios', | ||
104 | + os.path.join(BUILD_DIR, 'pc-bios', | ||
105 | + 'edk2-aarch64-code.fd')) | ||
106 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
107 | + self.vm.add_args('-object', 'rng-random,id=rng0,filename=/dev/urandom') | ||
108 | self.launch_and_wait(set_up_ssh_connection=False) | ||
109 | |||
110 | |||
111 | diff --git a/tests/avocado/machine_aarch64_virt.py b/tests/avocado/machine_aarch64_virt.py | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/tests/avocado/machine_aarch64_virt.py | ||
114 | +++ b/tests/avocado/machine_aarch64_virt.py | ||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | |||
117 | import time | ||
118 | import os | ||
119 | +import logging | ||
120 | |||
121 | from avocado_qemu import QemuSystemTest | ||
122 | from avocado_qemu import wait_for_console_pattern | ||
123 | from avocado_qemu import exec_command | ||
124 | from avocado_qemu import BUILD_DIR | ||
125 | +from avocado.utils import process | ||
126 | +from avocado.utils.path import find_command | ||
127 | |||
128 | class Aarch64VirtMachine(QemuSystemTest): | ||
129 | KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 ' | ||
130 | @@ -XXX,XX +XXX,XX @@ def test_alpine_virt_tcg_gic_max(self): | ||
131 | self.wait_for_console_pattern('Welcome to Alpine Linux 3.16') | ||
132 | |||
133 | |||
134 | - def test_aarch64_virt(self): | ||
135 | + def common_aarch64_virt(self, machine): | ||
136 | """ | ||
137 | - :avocado: tags=arch:aarch64 | ||
138 | - :avocado: tags=machine:virt | ||
139 | - :avocado: tags=accel:tcg | ||
140 | - :avocado: tags=cpu:max | ||
141 | + Common code to launch basic virt machine with kernel+initrd | ||
142 | + and a scratch disk. | ||
143 | """ | ||
144 | + logger = logging.getLogger('aarch64_virt') | ||
145 | + | ||
146 | kernel_url = ('https://fileserver.linaro.org/s/' | ||
147 | 'z6B2ARM7DQT3HWN/download') | ||
148 | - | ||
149 | kernel_hash = 'ed11daab50c151dde0e1e9c9cb8b2d9bd3215347' | ||
150 | kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ def test_aarch64_virt(self): | ||
153 | 'console=ttyAMA0') | ||
154 | self.require_accelerator("tcg") | ||
155 | self.vm.add_args('-cpu', 'max,pauth-impdef=on', | ||
156 | + '-machine', machine, | ||
157 | '-accel', 'tcg', | ||
158 | '-kernel', kernel_path, | ||
159 | '-append', kernel_command_line) | ||
160 | + | ||
161 | + # A RNG offers an easy way to generate a few IRQs | ||
162 | + self.vm.add_args('-device', 'virtio-rng-pci,rng=rng0') | ||
163 | + self.vm.add_args('-object', | ||
164 | + 'rng-random,id=rng0,filename=/dev/urandom') | ||
165 | + | ||
166 | + # Also add a scratch block device | ||
167 | + logger.info('creating scratch qcow2 image') | ||
168 | + image_path = os.path.join(self.workdir, 'scratch.qcow2') | ||
169 | + qemu_img = os.path.join(BUILD_DIR, 'qemu-img') | ||
170 | + if not os.path.exists(qemu_img): | ||
171 | + qemu_img = find_command('qemu-img', False) | ||
172 | + if qemu_img is False: | ||
173 | + self.cancel('Could not find "qemu-img", which is required to ' | ||
174 | + 'create the temporary qcow2 image') | ||
175 | + cmd = '%s create -f qcow2 %s 8M' % (qemu_img, image_path) | ||
176 | + process.run(cmd) | ||
177 | + | ||
178 | + # Add the device | ||
179 | + self.vm.add_args('-blockdev', | ||
180 | + f"driver=qcow2,file.driver=file,file.filename={image_path},node-name=scratch") | ||
181 | + self.vm.add_args('-device', | ||
182 | + 'virtio-blk-device,drive=scratch') | ||
183 | + | ||
184 | self.vm.launch() | ||
185 | self.wait_for_console_pattern('Welcome to Buildroot') | ||
186 | time.sleep(0.1) | ||
187 | exec_command(self, 'root') | ||
188 | time.sleep(0.1) | ||
189 | + exec_command(self, 'dd if=/dev/hwrng of=/dev/vda bs=512 count=4') | ||
190 | + time.sleep(0.1) | ||
191 | + exec_command(self, 'md5sum /dev/vda') | ||
192 | + time.sleep(0.1) | ||
193 | + exec_command(self, 'cat /proc/interrupts') | ||
194 | + time.sleep(0.1) | ||
195 | exec_command(self, 'cat /proc/self/maps') | ||
196 | time.sleep(0.1) | ||
197 | + | ||
198 | + def test_aarch64_virt_gicv3(self): | ||
199 | + """ | ||
200 | + :avocado: tags=arch:aarch64 | ||
201 | + :avocado: tags=machine:virt | ||
202 | + :avocado: tags=accel:tcg | ||
203 | + :avocado: tags=cpu:max | ||
204 | + """ | ||
205 | + self.common_aarch64_virt("virt,gic_version=3") | ||
206 | + | ||
207 | + def test_aarch64_virt_gicv2(self): | ||
208 | + """ | ||
209 | + :avocado: tags=arch:aarch64 | ||
210 | + :avocado: tags=machine:virt | ||
211 | + :avocado: tags=accel:tcg | ||
212 | + :avocado: tags=cpu:max | ||
213 | + """ | ||
214 | + self.common_aarch64_virt("virt,gic-version=2") | ||
215 | -- | ||
216 | 2.34.1 | ||
217 | |||
218 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Mostafa Saleh <smostafa@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Add common/sysbus/pci/sdbus comments to have clearer code blocks separation. | 3 | GBPA register can be used to globally abort all |
4 | transactions. | ||
4 | 5 | ||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 6 | It is described in the SMMU manual in "6.3.14 SMMU_GBPA". |
6 | Message-id: 20180115182436.2066-4-f4bug@amsat.org | 7 | ABORT reset value is IMPLEMENTATION DEFINED, it is chosen to |
8 | be zero(Do not abort incoming transactions). | ||
9 | |||
10 | Other fields have default values of Use Incoming. | ||
11 | |||
12 | If UPDATE is not set, the write is ignored. This is the only permitted | ||
13 | behavior in SMMUv3.2 and later.(6.3.14.1 Update procedure) | ||
14 | |||
15 | As this patch adds a new state to the SMMU (GBPA), it is added | ||
16 | in a new subsection for forward migration compatibility. | ||
17 | GBPA is only migrated if its value is different from the reset value. | ||
18 | It does this to be backward migration compatible if SW didn't write | ||
19 | the register. | ||
20 | |||
21 | Signed-off-by: Mostafa Saleh <smostafa@google.com> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
24 | Message-id: 20230214094009.2445653-1-smostafa@google.com | ||
25 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | 27 | --- |
10 | include/hw/sd/sdhci.h | 4 +++- | 28 | hw/arm/smmuv3-internal.h | 7 +++++++ |
11 | hw/sd/sdhci.c | 25 +++++++++++++++++-------- | 29 | include/hw/arm/smmuv3.h | 1 + |
12 | 2 files changed, 20 insertions(+), 9 deletions(-) | 30 | hw/arm/smmuv3.c | 43 +++++++++++++++++++++++++++++++++++++++- |
31 | 3 files changed, 50 insertions(+), 1 deletion(-) | ||
13 | 32 | ||
14 | diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h | 33 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h |
15 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/sd/sdhci.h | 35 | --- a/hw/arm/smmuv3-internal.h |
17 | +++ b/include/hw/sd/sdhci.h | 36 | +++ b/hw/arm/smmuv3-internal.h |
18 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | 37 | @@ -XXX,XX +XXX,XX @@ REG32(CR0ACK, 0x24) |
19 | uint32_t buf_maxsz; | 38 | REG32(CR1, 0x28) |
20 | uint16_t data_count; /* current element in FIFO buffer */ | 39 | REG32(CR2, 0x2c) |
21 | uint8_t stopped_state;/* Current SDHC state */ | 40 | REG32(STATUSR, 0x40) |
22 | - bool pending_insert_quirk;/* Quirk for Raspberry Pi card insert int */ | 41 | +REG32(GBPA, 0x44) |
23 | bool pending_insert_state; | 42 | + FIELD(GBPA, ABORT, 20, 1) |
24 | /* Buffer Data Port Register - virtual access point to R and W buffers */ | 43 | + FIELD(GBPA, UPDATE, 31, 1) |
25 | /* Software Reset Register - always reads as 0 */ | ||
26 | /* Force Event Auto CMD12 Error Interrupt Reg - write only */ | ||
27 | /* Force Event Error Interrupt Register- write only */ | ||
28 | /* RO Host Controller Version Register always reads as 0x2401 */ | ||
29 | + | 44 | + |
30 | + /* Configurable properties */ | 45 | +/* Use incoming. */ |
31 | + bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ | 46 | +#define SMMU_GBPA_RESET_VAL 0x1000 |
32 | } SDHCIState; | 47 | + |
33 | 48 | REG32(IRQ_CTRL, 0x50) | |
34 | #define TYPE_PCI_SDHCI "sdhci-pci" | 49 | FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1) |
35 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 50 | FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1) |
51 | diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h | ||
36 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/hw/sd/sdhci.c | 53 | --- a/include/hw/arm/smmuv3.h |
38 | +++ b/hw/sd/sdhci.c | 54 | +++ b/include/hw/arm/smmuv3.h |
39 | @@ -XXX,XX +XXX,XX @@ | 55 | @@ -XXX,XX +XXX,XX @@ struct SMMUv3State { |
40 | */ | 56 | uint32_t cr[3]; |
41 | 57 | uint32_t cr0ack; | |
42 | #include "qemu/osdep.h" | 58 | uint32_t statusr; |
43 | +#include "qapi/error.h" | 59 | + uint32_t gbpa; |
44 | #include "hw/hw.h" | 60 | uint32_t irq_ctrl; |
45 | #include "sysemu/block-backend.h" | 61 | uint32_t gerror; |
46 | #include "sysemu/blockdev.h" | 62 | uint32_t gerrorn; |
47 | @@ -XXX,XX +XXX,XX @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s) | 63 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c |
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/hw/arm/smmuv3.c | ||
66 | +++ b/hw/arm/smmuv3.c | ||
67 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_init_regs(SMMUv3State *s) | ||
68 | s->gerror = 0; | ||
69 | s->gerrorn = 0; | ||
70 | s->statusr = 0; | ||
71 | + s->gbpa = SMMU_GBPA_RESET_VAL; | ||
72 | } | ||
73 | |||
74 | static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, | ||
75 | @@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, | ||
76 | qemu_mutex_lock(&s->mutex); | ||
77 | |||
78 | if (!smmu_enabled(s)) { | ||
79 | - status = SMMU_TRANS_DISABLE; | ||
80 | + if (FIELD_EX32(s->gbpa, GBPA, ABORT)) { | ||
81 | + status = SMMU_TRANS_ABORT; | ||
82 | + } else { | ||
83 | + status = SMMU_TRANS_DISABLE; | ||
84 | + } | ||
85 | goto epilogue; | ||
48 | } | 86 | } |
49 | } | 87 | |
50 | 88 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, | |
51 | +/* --- qdev common --- */ | 89 | case A_GERROR_IRQ_CFG2: |
52 | + | 90 | s->gerror_irq_cfg2 = data; |
53 | +#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ | 91 | return MEMTX_OK; |
54 | + /* Capabilities registers provide information on supported features | 92 | + case A_GBPA: |
55 | + * of this specific host controller implementation */ \ | 93 | + /* |
56 | + DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ | 94 | + * If UPDATE is not set, the write is ignored. This is the only |
57 | + DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0) | 95 | + * permitted behavior in SMMUv3.2 and later. |
58 | + | 96 | + */ |
59 | static void sdhci_initfn(SDHCIState *s) | 97 | + if (data & R_GBPA_UPDATE_MASK) { |
60 | { | 98 | + /* Ignore update bit as write is synchronous. */ |
61 | qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), | 99 | + s->gbpa = data & ~R_GBPA_UPDATE_MASK; |
62 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription sdhci_vmstate = { | 100 | + } |
101 | + return MEMTX_OK; | ||
102 | case A_STRTAB_BASE: /* 64b */ | ||
103 | s->strtab_base = deposit64(s->strtab_base, 0, 32, data); | ||
104 | return MEMTX_OK; | ||
105 | @@ -XXX,XX +XXX,XX @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, | ||
106 | case A_STATUSR: | ||
107 | *data = s->statusr; | ||
108 | return MEMTX_OK; | ||
109 | + case A_GBPA: | ||
110 | + *data = s->gbpa; | ||
111 | + return MEMTX_OK; | ||
112 | case A_IRQ_CTRL: | ||
113 | case A_IRQ_CTRL_ACK: | ||
114 | *data = s->irq_ctrl; | ||
115 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3_queue = { | ||
63 | }, | 116 | }, |
64 | }; | 117 | }; |
65 | 118 | ||
66 | -/* Capabilities registers provide information on supported features of this | 119 | +static bool smmuv3_gbpa_needed(void *opaque) |
67 | - * specific host controller implementation */ | 120 | +{ |
68 | +/* --- qdev PCI --- */ | 121 | + SMMUv3State *s = opaque; |
69 | + | 122 | + |
70 | static Property sdhci_pci_properties[] = { | 123 | + /* Only migrate GBPA if it has different reset value. */ |
71 | - DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, | 124 | + return s->gbpa != SMMU_GBPA_RESET_VAL; |
72 | - SDHC_CAPAB_REG_DEFAULT), | 125 | +} |
73 | - DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), | 126 | + |
74 | + DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), | 127 | +static const VMStateDescription vmstate_gbpa = { |
75 | DEFINE_PROP_END_OF_LIST(), | 128 | + .name = "smmuv3/gbpa", |
129 | + .version_id = 1, | ||
130 | + .minimum_version_id = 1, | ||
131 | + .needed = smmuv3_gbpa_needed, | ||
132 | + .fields = (VMStateField[]) { | ||
133 | + VMSTATE_UINT32(gbpa, SMMUv3State), | ||
134 | + VMSTATE_END_OF_LIST() | ||
135 | + } | ||
136 | +}; | ||
137 | + | ||
138 | static const VMStateDescription vmstate_smmuv3 = { | ||
139 | .name = "smmuv3", | ||
140 | .version_id = 1, | ||
141 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_smmuv3 = { | ||
142 | |||
143 | VMSTATE_END_OF_LIST(), | ||
144 | }, | ||
145 | + .subsections = (const VMStateDescription * []) { | ||
146 | + &vmstate_gbpa, | ||
147 | + NULL | ||
148 | + } | ||
76 | }; | 149 | }; |
77 | 150 | ||
78 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo sdhci_pci_info = { | 151 | static void smmuv3_instance_init(Object *obj) |
79 | }, | ||
80 | }; | ||
81 | |||
82 | +/* --- qdev SysBus --- */ | ||
83 | + | ||
84 | static Property sdhci_sysbus_properties[] = { | ||
85 | - DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, | ||
86 | - SDHC_CAPAB_REG_DEFAULT), | ||
87 | - DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), | ||
88 | + DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), | ||
89 | DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, | ||
90 | false), | ||
91 | DEFINE_PROP_END_OF_LIST(), | ||
92 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo sdhci_sysbus_info = { | ||
93 | .class_init = sdhci_sysbus_class_init, | ||
94 | }; | ||
95 | |||
96 | +/* --- qdev bus master --- */ | ||
97 | + | ||
98 | static void sdhci_bus_class_init(ObjectClass *klass, void *data) | ||
99 | { | ||
100 | SDBusClass *sbc = SD_BUS_CLASS(klass); | ||
101 | -- | 152 | -- |
102 | 2.7.4 | 153 | 2.34.1 |
103 | |||
104 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | Since commit acc0b8b05a when running the ZynqMP ZCU102 board with |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | a QEMU configured using --without-default-devices, we get: |
5 | Message-id: 20180110063337.21538-3-richard.henderson@linaro.org | 5 | |
6 | $ qemu-system-aarch64 -M xlnx-zcu102 | ||
7 | qemu-system-aarch64: missing object type 'usb_dwc3' | ||
8 | Abort trap: 6 | ||
9 | |||
10 | Fix by adding the missing Kconfig dependency. | ||
11 | |||
12 | Fixes: acc0b8b05a ("hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers") | ||
13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
14 | Message-id: 20230216092327.2203-1-philmd@linaro.org | ||
15 | Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 17 | --- |
8 | target/arm/translate-a64.c | 5 +++++ | 18 | hw/arm/Kconfig | 1 + |
9 | 1 file changed, 5 insertions(+) | 19 | 1 file changed, 1 insertion(+) |
10 | 20 | ||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 21 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig |
12 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate-a64.c | 23 | --- a/hw/arm/Kconfig |
14 | +++ b/target/arm/translate-a64.c | 24 | +++ b/hw/arm/Kconfig |
15 | @@ -XXX,XX +XXX,XX @@ static uint64_t vfp_expand_imm(int size, uint8_t imm8) | 25 | @@ -XXX,XX +XXX,XX @@ config XLNX_ZYNQMP_ARM |
16 | (extract32(imm8, 0, 6) << 3); | 26 | select XLNX_CSU_DMA |
17 | imm <<= 16; | 27 | select XLNX_ZYNQMP |
18 | break; | 28 | select XLNX_ZDMA |
19 | + case MO_16: | 29 | + select USB_DWC3 |
20 | + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | 30 | |
21 | + (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) | | 31 | config XLNX_VERSAL |
22 | + (extract32(imm8, 0, 6) << 6); | 32 | bool |
23 | + break; | ||
24 | default: | ||
25 | g_assert_not_reached(); | ||
26 | } | ||
27 | -- | 33 | -- |
28 | 2.7.4 | 34 | 2.34.1 |
29 | 35 | ||
30 | 36 | diff view generated by jsdifflib |
1 | Since omap_mmc is still using the legacy SD card API, the SD | 1 | From: Cornelia Huck <cohuck@redhat.com> |
---|---|---|---|
2 | card created by sd_init() is not plugged into any bus. This | ||
3 | means that the controller has to reset it manually. | ||
4 | 2 | ||
5 | Failing to do this mostly didn't affect the guest since the | 3 | Just use current_accel_name() directly. |
6 | guest typically does a programmed SD card reset as part of | ||
7 | its SD controller driver initialization, but would mean that | ||
8 | migration fails because it's only in sd_reset() that we | ||
9 | set up the wpgrps_size field. | ||
10 | 4 | ||
5 | Signed-off-by: Cornelia Huck <cohuck@redhat.com> | ||
6 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
13 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Message-id: 1515506513-31961-5-git-send-email-peter.maydell@linaro.org | ||
15 | --- | 9 | --- |
16 | hw/sd/omap_mmc.c | 14 ++++++++++---- | 10 | hw/arm/virt.c | 6 +++--- |
17 | 1 file changed, 10 insertions(+), 4 deletions(-) | 11 | 1 file changed, 3 insertions(+), 3 deletions(-) |
18 | 12 | ||
19 | diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c | 13 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/sd/omap_mmc.c | 15 | --- a/hw/arm/virt.c |
22 | +++ b/hw/sd/omap_mmc.c | 16 | +++ b/hw/arm/virt.c |
23 | @@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host) | 17 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) |
24 | host->cdet_enable = 0; | 18 | if (vms->secure && (kvm_enabled() || hvf_enabled())) { |
25 | qemu_set_irq(host->coverswitch, host->cdet_state); | 19 | error_report("mach-virt: %s does not support providing " |
26 | host->clkdiv = 0; | 20 | "Security extensions (TrustZone) to the guest CPU", |
27 | + | 21 | - kvm_enabled() ? "KVM" : "HVF"); |
28 | + /* Since we're still using the legacy SD API the card is not plugged | 22 | + current_accel_name()); |
29 | + * into any bus, and we must reset it manually. When omap_mmc is | ||
30 | + * QOMified this must move into the QOM reset function. | ||
31 | + */ | ||
32 | + device_reset(DEVICE(host->card)); | ||
33 | } | ||
34 | |||
35 | static uint64_t omap_mmc_read(void *opaque, hwaddr offset, | ||
36 | @@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap_mmc_init(hwaddr base, | ||
37 | s->lines = 1; /* TODO: needs to be settable per-board */ | ||
38 | s->rev = 1; | ||
39 | |||
40 | - omap_mmc_reset(s); | ||
41 | - | ||
42 | memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800); | ||
43 | memory_region_add_subregion(sysmem, base, &s->iomem); | ||
44 | |||
45 | @@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap_mmc_init(hwaddr base, | ||
46 | exit(1); | 23 | exit(1); |
47 | } | 24 | } |
48 | 25 | ||
49 | + omap_mmc_reset(s); | 26 | if (vms->virt && (kvm_enabled() || hvf_enabled())) { |
50 | + | 27 | error_report("mach-virt: %s does not support providing " |
51 | return s; | 28 | "Virtualization extensions to the guest CPU", |
52 | } | 29 | - kvm_enabled() ? "KVM" : "HVF"); |
53 | 30 | + current_accel_name()); | |
54 | @@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, | 31 | exit(1); |
55 | s->lines = 4; | 32 | } |
56 | s->rev = 2; | 33 | |
57 | 34 | if (vms->mte && (kvm_enabled() || hvf_enabled())) { | |
58 | - omap_mmc_reset(s); | 35 | error_report("mach-virt: %s does not support providing " |
59 | - | 36 | "MTE to the guest CPU", |
60 | memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", | 37 | - kvm_enabled() ? "KVM" : "HVF"); |
61 | omap_l4_region_size(ta, 0)); | 38 | + current_accel_name()); |
62 | omap_l4_attach(ta, 0, &s->iomem); | 39 | exit(1); |
63 | @@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, | 40 | } |
64 | s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0); | ||
65 | sd_set_cb(s->card, NULL, s->cdet); | ||
66 | |||
67 | + omap_mmc_reset(s); | ||
68 | + | ||
69 | return s; | ||
70 | } | ||
71 | 41 | ||
72 | -- | 42 | -- |
73 | 2.7.4 | 43 | 2.34.1 |
74 | |||
75 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
1 | 2 | ||
3 | Havard is no longer working on the Nuvoton systems for a while | ||
4 | and won't be able to do any work on it in the future. So I'll | ||
5 | take over maintaining the Nuvoton system from him. | ||
6 | |||
7 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
8 | Acked-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
9 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
10 | Message-id: 20230208235433.3989937-2-wuhaotsh@google.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | MAINTAINERS | 2 +- | ||
14 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
15 | |||
16 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/MAINTAINERS | ||
19 | +++ b/MAINTAINERS | ||
20 | @@ -XXX,XX +XXX,XX @@ F: include/hw/net/mv88w8618_eth.h | ||
21 | F: docs/system/arm/musicpal.rst | ||
22 | |||
23 | Nuvoton NPCM7xx | ||
24 | -M: Havard Skinnemoen <hskinnemoen@google.com> | ||
25 | M: Tyrone Ting <kfting@nuvoton.com> | ||
26 | +M: Hao Wu <wuhaotsh@google.com> | ||
27 | L: qemu-arm@nongnu.org | ||
28 | S: Supported | ||
29 | F: hw/*/npcm7xx* | ||
30 | -- | ||
31 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Hao Wu <wuhaotsh@google.com> | ||
1 | 2 | ||
3 | Nuvoton's PSPI is a general purpose SPI module which enables | ||
4 | connections to SPI-based peripheral devices. | ||
5 | |||
6 | Signed-off-by: Hao Wu <wuhaotsh@google.com> | ||
7 | Reviewed-by: Chris Rauer <crauer@google.com> | ||
8 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> | ||
9 | Message-id: 20230208235433.3989937-3-wuhaotsh@google.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | MAINTAINERS | 6 +- | ||
13 | include/hw/ssi/npcm_pspi.h | 53 +++++++++ | ||
14 | hw/ssi/npcm_pspi.c | 221 +++++++++++++++++++++++++++++++++++++ | ||
15 | hw/ssi/meson.build | 2 +- | ||
16 | hw/ssi/trace-events | 5 + | ||
17 | 5 files changed, 283 insertions(+), 4 deletions(-) | ||
18 | create mode 100644 include/hw/ssi/npcm_pspi.h | ||
19 | create mode 100644 hw/ssi/npcm_pspi.c | ||
20 | |||
21 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/MAINTAINERS | ||
24 | +++ b/MAINTAINERS | ||
25 | @@ -XXX,XX +XXX,XX @@ M: Tyrone Ting <kfting@nuvoton.com> | ||
26 | M: Hao Wu <wuhaotsh@google.com> | ||
27 | L: qemu-arm@nongnu.org | ||
28 | S: Supported | ||
29 | -F: hw/*/npcm7xx* | ||
30 | -F: include/hw/*/npcm7xx* | ||
31 | -F: tests/qtest/npcm7xx* | ||
32 | +F: hw/*/npcm* | ||
33 | +F: include/hw/*/npcm* | ||
34 | +F: tests/qtest/npcm* | ||
35 | F: pc-bios/npcm7xx_bootrom.bin | ||
36 | F: roms/vbootrom | ||
37 | F: docs/system/arm/nuvoton.rst | ||
38 | diff --git a/include/hw/ssi/npcm_pspi.h b/include/hw/ssi/npcm_pspi.h | ||
39 | new file mode 100644 | ||
40 | index XXXXXXX..XXXXXXX | ||
41 | --- /dev/null | ||
42 | +++ b/include/hw/ssi/npcm_pspi.h | ||
43 | @@ -XXX,XX +XXX,XX @@ | ||
44 | +/* | ||
45 | + * Nuvoton Peripheral SPI Module | ||
46 | + * | ||
47 | + * Copyright 2023 Google LLC | ||
48 | + * | ||
49 | + * This program is free software; you can redistribute it and/or modify it | ||
50 | + * under the terms of the GNU General Public License as published by the | ||
51 | + * Free Software Foundation; either version 2 of the License, or | ||
52 | + * (at your option) any later version. | ||
53 | + * | ||
54 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
55 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
56 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
57 | + * for more details. | ||
58 | + */ | ||
59 | +#ifndef NPCM_PSPI_H | ||
60 | +#define NPCM_PSPI_H | ||
61 | + | ||
62 | +#include "hw/ssi/ssi.h" | ||
63 | +#include "hw/sysbus.h" | ||
64 | + | ||
65 | +/* | ||
66 | + * Number of registers in our device state structure. Don't change this without | ||
67 | + * incrementing the version_id in the vmstate. | ||
68 | + */ | ||
69 | +#define NPCM_PSPI_NR_REGS 3 | ||
70 | + | ||
71 | +/** | ||
72 | + * NPCMPSPIState - Device state for one Flash Interface Unit. | ||
73 | + * @parent: System bus device. | ||
74 | + * @mmio: Memory region for register access. | ||
75 | + * @spi: The SPI bus mastered by this controller. | ||
76 | + * @regs: Register contents. | ||
77 | + * @irq: The interrupt request queue for this module. | ||
78 | + * | ||
79 | + * Each PSPI has a shared bank of registers, and controls up to four chip | ||
80 | + * selects. Each chip select has a dedicated memory region which may be used to | ||
81 | + * read and write the flash connected to that chip select as if it were memory. | ||
82 | + */ | ||
83 | +typedef struct NPCMPSPIState { | ||
84 | + SysBusDevice parent; | ||
85 | + | ||
86 | + MemoryRegion mmio; | ||
87 | + | ||
88 | + SSIBus *spi; | ||
89 | + uint16_t regs[NPCM_PSPI_NR_REGS]; | ||
90 | + qemu_irq irq; | ||
91 | +} NPCMPSPIState; | ||
92 | + | ||
93 | +#define TYPE_NPCM_PSPI "npcm-pspi" | ||
94 | +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPSPIState, NPCM_PSPI) | ||
95 | + | ||
96 | +#endif /* NPCM_PSPI_H */ | ||
97 | diff --git a/hw/ssi/npcm_pspi.c b/hw/ssi/npcm_pspi.c | ||
98 | new file mode 100644 | ||
99 | index XXXXXXX..XXXXXXX | ||
100 | --- /dev/null | ||
101 | +++ b/hw/ssi/npcm_pspi.c | ||
102 | @@ -XXX,XX +XXX,XX @@ | ||
103 | +/* | ||
104 | + * Nuvoton NPCM Peripheral SPI Module (PSPI) | ||
105 | + * | ||
106 | + * Copyright 2023 Google LLC | ||
107 | + * | ||
108 | + * This program is free software; you can redistribute it and/or modify it | ||
109 | + * under the terms of the GNU General Public License as published by the | ||
110 | + * Free Software Foundation; either version 2 of the License, or | ||
111 | + * (at your option) any later version. | ||
112 | + * | ||
113 | + * This program is distributed in the hope that it will be useful, but WITHOUT | ||
114 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
115 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
116 | + * for more details. | ||
117 | + */ | ||
118 | + | ||
119 | +#include "qemu/osdep.h" | ||
120 | + | ||
121 | +#include "hw/irq.h" | ||
122 | +#include "hw/registerfields.h" | ||
123 | +#include "hw/ssi/npcm_pspi.h" | ||
124 | +#include "migration/vmstate.h" | ||
125 | +#include "qapi/error.h" | ||
126 | +#include "qemu/error-report.h" | ||
127 | +#include "qemu/log.h" | ||
128 | +#include "qemu/module.h" | ||
129 | +#include "qemu/units.h" | ||
130 | + | ||
131 | +#include "trace.h" | ||
132 | + | ||
133 | +REG16(PSPI_DATA, 0x0) | ||
134 | +REG16(PSPI_CTL1, 0x2) | ||
135 | + FIELD(PSPI_CTL1, SPIEN, 0, 1) | ||
136 | + FIELD(PSPI_CTL1, MOD, 2, 1) | ||
137 | + FIELD(PSPI_CTL1, EIR, 5, 1) | ||
138 | + FIELD(PSPI_CTL1, EIW, 6, 1) | ||
139 | + FIELD(PSPI_CTL1, SCM, 7, 1) | ||
140 | + FIELD(PSPI_CTL1, SCIDL, 8, 1) | ||
141 | + FIELD(PSPI_CTL1, SCDV, 9, 7) | ||
142 | +REG16(PSPI_STAT, 0x4) | ||
143 | + FIELD(PSPI_STAT, BSY, 0, 1) | ||
144 | + FIELD(PSPI_STAT, RBF, 1, 1) | ||
145 | + | ||
146 | +static void npcm_pspi_update_irq(NPCMPSPIState *s) | ||
147 | +{ | ||
148 | + int level = 0; | ||
149 | + | ||
150 | + /* Only fire IRQ when the module is enabled. */ | ||
151 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, SPIEN)) { | ||
152 | + /* Update interrupt as BSY is cleared. */ | ||
153 | + if ((!FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, BSY)) && | ||
154 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIW)) { | ||
155 | + level = 1; | ||
156 | + } | ||
157 | + | ||
158 | + /* Update interrupt as RBF is set. */ | ||
159 | + if (FIELD_EX16(s->regs[R_PSPI_STAT], PSPI_STAT, RBF) && | ||
160 | + FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, EIR)) { | ||
161 | + level = 1; | ||
162 | + } | ||
163 | + } | ||
164 | + qemu_set_irq(s->irq, level); | ||
165 | +} | ||
166 | + | ||
167 | +static uint16_t npcm_pspi_read_data(NPCMPSPIState *s) | ||
168 | +{ | ||
169 | + uint16_t value = s->regs[R_PSPI_DATA]; | ||
170 | + | ||
171 | + /* Clear stat bits as the value are read out. */ | ||
172 | + s->regs[R_PSPI_STAT] = 0; | ||
173 | + | ||
174 | + return value; | ||
175 | +} | ||
176 | + | ||
177 | +static void npcm_pspi_write_data(NPCMPSPIState *s, uint16_t data) | ||
178 | +{ | ||
179 | + uint16_t value = 0; | ||
180 | + | ||
181 | + if (FIELD_EX16(s->regs[R_PSPI_CTL1], PSPI_CTL1, MOD)) { | ||
182 | + value = ssi_transfer(s->spi, extract16(data, 8, 8)) << 8; | ||
183 | + } | ||
184 | + value |= ssi_transfer(s->spi, extract16(data, 0, 8)); | ||
185 | + s->regs[R_PSPI_DATA] = value; | ||
186 | + | ||
187 | + /* Mark data as available */ | ||
188 | + s->regs[R_PSPI_STAT] = R_PSPI_STAT_BSY_MASK | R_PSPI_STAT_RBF_MASK; | ||
189 | +} | ||
190 | + | ||
191 | +/* Control register read handler. */ | ||
192 | +static uint64_t npcm_pspi_ctrl_read(void *opaque, hwaddr addr, | ||
193 | + unsigned int size) | ||
194 | +{ | ||
195 | + NPCMPSPIState *s = opaque; | ||
196 | + uint16_t value; | ||
197 | + | ||
198 | + switch (addr) { | ||
199 | + case A_PSPI_DATA: | ||
200 | + value = npcm_pspi_read_data(s); | ||
201 | + break; | ||
202 | + | ||
203 | + case A_PSPI_CTL1: | ||
204 | + value = s->regs[R_PSPI_CTL1]; | ||
205 | + break; | ||
206 | + | ||
207 | + case A_PSPI_STAT: | ||
208 | + value = s->regs[R_PSPI_STAT]; | ||
209 | + break; | ||
210 | + | ||
211 | + default: | ||
212 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
213 | + "%s: write to invalid offset 0x%" PRIx64 "\n", | ||
214 | + DEVICE(s)->canonical_path, addr); | ||
215 | + return 0; | ||
216 | + } | ||
217 | + trace_npcm_pspi_ctrl_read(DEVICE(s)->canonical_path, addr, value); | ||
218 | + npcm_pspi_update_irq(s); | ||
219 | + | ||
220 | + return value; | ||
221 | +} | ||
222 | + | ||
223 | +/* Control register write handler. */ | ||
224 | +static void npcm_pspi_ctrl_write(void *opaque, hwaddr addr, uint64_t v, | ||
225 | + unsigned int size) | ||
226 | +{ | ||
227 | + NPCMPSPIState *s = opaque; | ||
228 | + uint16_t value = v; | ||
229 | + | ||
230 | + trace_npcm_pspi_ctrl_write(DEVICE(s)->canonical_path, addr, value); | ||
231 | + | ||
232 | + switch (addr) { | ||
233 | + case A_PSPI_DATA: | ||
234 | + npcm_pspi_write_data(s, value); | ||
235 | + break; | ||
236 | + | ||
237 | + case A_PSPI_CTL1: | ||
238 | + s->regs[R_PSPI_CTL1] = value; | ||
239 | + break; | ||
240 | + | ||
241 | + case A_PSPI_STAT: | ||
242 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
243 | + "%s: write to read-only register PSPI_STAT: 0x%08" | ||
244 | + PRIx64 "\n", DEVICE(s)->canonical_path, v); | ||
245 | + break; | ||
246 | + | ||
247 | + default: | ||
248 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
249 | + "%s: write to invalid offset 0x%" PRIx64 "\n", | ||
250 | + DEVICE(s)->canonical_path, addr); | ||
251 | + return; | ||
252 | + } | ||
253 | + npcm_pspi_update_irq(s); | ||
254 | +} | ||
255 | + | ||
256 | +static const MemoryRegionOps npcm_pspi_ctrl_ops = { | ||
257 | + .read = npcm_pspi_ctrl_read, | ||
258 | + .write = npcm_pspi_ctrl_write, | ||
259 | + .endianness = DEVICE_LITTLE_ENDIAN, | ||
260 | + .valid = { | ||
261 | + .min_access_size = 1, | ||
262 | + .max_access_size = 2, | ||
263 | + .unaligned = false, | ||
264 | + }, | ||
265 | + .impl = { | ||
266 | + .min_access_size = 2, | ||
267 | + .max_access_size = 2, | ||
268 | + .unaligned = false, | ||
269 | + }, | ||
270 | +}; | ||
271 | + | ||
272 | +static void npcm_pspi_enter_reset(Object *obj, ResetType type) | ||
273 | +{ | ||
274 | + NPCMPSPIState *s = NPCM_PSPI(obj); | ||
275 | + | ||
276 | + trace_npcm_pspi_enter_reset(DEVICE(obj)->canonical_path, type); | ||
277 | + memset(s->regs, 0, sizeof(s->regs)); | ||
278 | +} | ||
279 | + | ||
280 | +static void npcm_pspi_realize(DeviceState *dev, Error **errp) | ||
281 | +{ | ||
282 | + NPCMPSPIState *s = NPCM_PSPI(dev); | ||
283 | + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | ||
284 | + Object *obj = OBJECT(dev); | ||
285 | + | ||
286 | + s->spi = ssi_create_bus(dev, "pspi"); | ||
287 | + memory_region_init_io(&s->mmio, obj, &npcm_pspi_ctrl_ops, s, | ||
288 | + "mmio", 4 * KiB); | ||
289 | + sysbus_init_mmio(sbd, &s->mmio); | ||
290 | + sysbus_init_irq(sbd, &s->irq); | ||
291 | +} | ||
292 | + | ||
293 | +static const VMStateDescription vmstate_npcm_pspi = { | ||
294 | + .name = "npcm-pspi", | ||
295 | + .version_id = 0, | ||
296 | + .minimum_version_id = 0, | ||
297 | + .fields = (VMStateField[]) { | ||
298 | + VMSTATE_UINT16_ARRAY(regs, NPCMPSPIState, NPCM_PSPI_NR_REGS), | ||
299 | + VMSTATE_END_OF_LIST(), | ||
300 | + }, | ||
301 | +}; | ||
302 | + | ||
303 | + | ||
304 | +static void npcm_pspi_class_init(ObjectClass *klass, void *data) | ||
305 | +{ | ||
306 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
307 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
308 | + | ||
309 | + dc->desc = "NPCM Peripheral SPI Module"; | ||
310 | + dc->realize = npcm_pspi_realize; | ||
311 | + dc->vmsd = &vmstate_npcm_pspi; | ||
312 | + rc->phases.enter = npcm_pspi_enter_reset; | ||
313 | +} | ||
314 | + | ||
315 | +static const TypeInfo npcm_pspi_types[] = { | ||
316 | + { | ||
317 | + .name = TYPE_NPCM_PSPI, | ||
318 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
319 | + .instance_size = sizeof(NPCMPSPIState), | ||
320 | + .class_init = npcm_pspi_class_init, | ||
321 | + }, | ||
322 | +}; | ||
323 | +DEFINE_TYPES(npcm_pspi_types); | ||
324 | diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build | ||
325 | index XXXXXXX..XXXXXXX 100644 | ||
326 | --- a/hw/ssi/meson.build | ||
327 | +++ b/hw/ssi/meson.build | ||
328 | @@ -XXX,XX +XXX,XX @@ | ||
329 | softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_smc.c')) | ||
330 | softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('mss-spi.c')) | ||
331 | -softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c')) | ||
332 | +softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_fiu.c', 'npcm_pspi.c')) | ||
333 | softmmu_ss.add(when: 'CONFIG_PL022', if_true: files('pl022.c')) | ||
334 | softmmu_ss.add(when: 'CONFIG_SIFIVE_SPI', if_true: files('sifive_spi.c')) | ||
335 | softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) | ||
336 | diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events | ||
337 | index XXXXXXX..XXXXXXX 100644 | ||
338 | --- a/hw/ssi/trace-events | ||
339 | +++ b/hw/ssi/trace-events | ||
340 | @@ -XXX,XX +XXX,XX @@ npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s offset: | ||
341 | npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
342 | npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsigned int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%" PRIx64 | ||
343 | |||
344 | +# npcm_pspi.c | ||
345 | +npcm_pspi_enter_reset(const char *id, int reset_type) "%s reset type: %d" | ||
346 | +npcm_pspi_ctrl_read(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 | ||
347 | +npcm_pspi_ctrl_write(const char *id, uint64_t addr, uint16_t data) "%s offset: 0x%03" PRIx64 " value: 0x%04" PRIx16 | ||
348 | + | ||
349 | # ibex_spi_host.c | ||
350 | |||
351 | ibex_spi_host_reset(const char *msg) "%s" | ||
352 | -- | ||
353 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Hao Wu <wuhaotsh@google.com> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Signed-off-by: Hao Wu <wuhaotsh@google.com> |
4 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 4 | Reviewed-by: Titus Rwantare <titusr@google.com> |
5 | Message-id: 20180115182436.2066-6-f4bug@amsat.org | 5 | Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> |
6 | Message-id: 20230208235433.3989937-4-wuhaotsh@google.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 8 | --- |
8 | hw/sd/sdhci.c | 30 +++++++++++++++++++++--------- | 9 | docs/system/arm/nuvoton.rst | 2 +- |
9 | 1 file changed, 21 insertions(+), 9 deletions(-) | 10 | include/hw/arm/npcm7xx.h | 2 ++ |
11 | hw/arm/npcm7xx.c | 25 +++++++++++++++++++++++-- | ||
12 | 3 files changed, 26 insertions(+), 3 deletions(-) | ||
10 | 13 | ||
11 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 14 | diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst |
12 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/sd/sdhci.c | 16 | --- a/docs/system/arm/nuvoton.rst |
14 | +++ b/hw/sd/sdhci.c | 17 | +++ b/docs/system/arm/nuvoton.rst |
15 | @@ -XXX,XX +XXX,XX @@ static void sdhci_uninitfn(SDHCIState *s) | 18 | @@ -XXX,XX +XXX,XX @@ Supported devices |
16 | s->fifo_buffer = NULL; | 19 | * SMBus controller (SMBF) |
17 | } | 20 | * Ethernet controller (EMC) |
18 | 21 | * Tachometer | |
19 | +static void sdhci_common_realize(SDHCIState *s, Error **errp) | 22 | + * Peripheral SPI controller (PSPI) |
20 | +{ | 23 | |
21 | + s->buf_maxsz = sdhci_get_fifolen(s); | 24 | Missing devices |
22 | + s->fifo_buffer = g_malloc0(s->buf_maxsz); | 25 | --------------- |
26 | @@ -XXX,XX +XXX,XX @@ Missing devices | ||
27 | |||
28 | * Ethernet controller (GMAC) | ||
29 | * USB device (USBD) | ||
30 | - * Peripheral SPI controller (PSPI) | ||
31 | * SD/MMC host | ||
32 | * PECI interface | ||
33 | * PCI and PCIe root complex and bridges | ||
34 | diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/include/hw/arm/npcm7xx.h | ||
37 | +++ b/include/hw/arm/npcm7xx.h | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | #include "hw/nvram/npcm7xx_otp.h" | ||
40 | #include "hw/timer/npcm7xx_timer.h" | ||
41 | #include "hw/ssi/npcm7xx_fiu.h" | ||
42 | +#include "hw/ssi/npcm_pspi.h" | ||
43 | #include "hw/usb/hcd-ehci.h" | ||
44 | #include "hw/usb/hcd-ohci.h" | ||
45 | #include "target/arm/cpu.h" | ||
46 | @@ -XXX,XX +XXX,XX @@ struct NPCM7xxState { | ||
47 | NPCM7xxFIUState fiu[2]; | ||
48 | NPCM7xxEMCState emc[2]; | ||
49 | NPCM7xxSDHCIState mmc; | ||
50 | + NPCMPSPIState pspi[2]; | ||
51 | }; | ||
52 | |||
53 | #define TYPE_NPCM7XX "npcm7xx" | ||
54 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/hw/arm/npcm7xx.c | ||
57 | +++ b/hw/arm/npcm7xx.c | ||
58 | @@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt { | ||
59 | NPCM7XX_EMC1RX_IRQ = 15, | ||
60 | NPCM7XX_EMC1TX_IRQ, | ||
61 | NPCM7XX_MMC_IRQ = 26, | ||
62 | + NPCM7XX_PSPI2_IRQ = 28, | ||
63 | + NPCM7XX_PSPI1_IRQ = 31, | ||
64 | NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ | ||
65 | NPCM7XX_TIMER1_IRQ, | ||
66 | NPCM7XX_TIMER2_IRQ, | ||
67 | @@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_emc_addr[] = { | ||
68 | 0xf0826000, | ||
69 | }; | ||
70 | |||
71 | +/* Register base address for each PSPI Module */ | ||
72 | +static const hwaddr npcm7xx_pspi_addr[] = { | ||
73 | + 0xf0200000, | ||
74 | + 0xf0201000, | ||
75 | +}; | ||
23 | + | 76 | + |
24 | + memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", | 77 | static const struct { |
25 | + SDHC_REGISTERS_MAP_SIZE); | 78 | hwaddr regs_addr; |
26 | +} | 79 | uint32_t unconnected_pins; |
27 | + | 80 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj) |
28 | static bool sdhci_pending_insert_vmstate_needed(void *opaque) | 81 | object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC); |
29 | { | 82 | } |
30 | SDHCIState *s = opaque; | 83 | |
31 | @@ -XXX,XX +XXX,XX @@ static Property sdhci_pci_properties[] = { | 84 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { |
32 | static void sdhci_pci_realize(PCIDevice *dev, Error **errp) | 85 | + object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI); |
33 | { | ||
34 | SDHCIState *s = PCI_SDHCI(dev); | ||
35 | + | ||
36 | + sdhci_initfn(s); | ||
37 | + sdhci_common_realize(s, errp); | ||
38 | + if (errp && *errp) { | ||
39 | + return; | ||
40 | + } | 86 | + } |
41 | + | 87 | + |
42 | dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ | 88 | object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); |
43 | dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ | ||
44 | - sdhci_initfn(s); | ||
45 | - s->buf_maxsz = sdhci_get_fifolen(s); | ||
46 | - s->fifo_buffer = g_malloc0(s->buf_maxsz); | ||
47 | s->irq = pci_allocate_irq(dev); | ||
48 | - memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", | ||
49 | - SDHC_REGISTERS_MAP_SIZE); | ||
50 | pci_register_bar(dev, 0, 0, &s->iomem); | ||
51 | } | 89 | } |
52 | 90 | ||
53 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) | 91 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) |
54 | SDHCIState *s = SYSBUS_SDHCI(dev); | 92 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, |
55 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | 93 | npcm7xx_irq(s, NPCM7XX_MMC_IRQ)); |
56 | 94 | ||
57 | - s->buf_maxsz = sdhci_get_fifolen(s); | 95 | + /* PSPI */ |
58 | - s->fifo_buffer = g_malloc0(s->buf_maxsz); | 96 | + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pspi_addr) != ARRAY_SIZE(s->pspi)); |
59 | + sdhci_common_realize(s, errp); | 97 | + for (i = 0; i < ARRAY_SIZE(s->pspi); i++) { |
60 | + if (errp && *errp) { | 98 | + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pspi[i]); |
61 | + return; | 99 | + int irq = (i == 0) ? NPCM7XX_PSPI1_IRQ : NPCM7XX_PSPI2_IRQ; |
100 | + | ||
101 | + sysbus_realize(sbd, &error_abort); | ||
102 | + sysbus_mmio_map(sbd, 0, npcm7xx_pspi_addr[i]); | ||
103 | + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); | ||
62 | + } | 104 | + } |
63 | + | 105 | + |
64 | sysbus_init_irq(sbd, &s->irq); | 106 | create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); |
65 | - memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", | 107 | create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); |
66 | - SDHC_REGISTERS_MAP_SIZE); | 108 | create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); |
67 | sysbus_init_mmio(sbd, &s->iomem); | 109 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) |
68 | } | 110 | create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB); |
69 | 111 | create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB); | |
112 | create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB); | ||
113 | - create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB); | ||
114 | - create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB); | ||
115 | create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB); | ||
116 | create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB); | ||
117 | create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB); | ||
70 | -- | 118 | -- |
71 | 2.7.4 | 119 | 2.34.1 |
72 | |||
73 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
1 | 2 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | ||
4 | all upper bits set. Ensure the IOMMU region covers all 64 bits. | ||
5 | |||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Message-id: 20230214171921.1917916-2-jean-philippe@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | include/hw/arm/smmu-common.h | 2 -- | ||
13 | hw/arm/smmu-common.c | 2 +- | ||
14 | 2 files changed, 1 insertion(+), 3 deletions(-) | ||
15 | |||
16 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/arm/smmu-common.h | ||
19 | +++ b/include/hw/arm/smmu-common.h | ||
20 | @@ -XXX,XX +XXX,XX @@ | ||
21 | #define SMMU_PCI_DEVFN_MAX 256 | ||
22 | #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) | ||
23 | |||
24 | -#define SMMU_MAX_VA_BITS 48 | ||
25 | - | ||
26 | /* | ||
27 | * Page table walk error types | ||
28 | */ | ||
29 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/hw/arm/smmu-common.c | ||
32 | +++ b/hw/arm/smmu-common.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static AddressSpace *smmu_find_add_as(PCIBus *bus, void *opaque, int devfn) | ||
34 | |||
35 | memory_region_init_iommu(&sdev->iommu, sizeof(sdev->iommu), | ||
36 | s->mrtypename, | ||
37 | - OBJECT(s), name, 1ULL << SMMU_MAX_VA_BITS); | ||
38 | + OBJECT(s), name, UINT64_MAX); | ||
39 | address_space_init(&sdev->as, | ||
40 | MEMORY_REGION(&sdev->iommu), name); | ||
41 | trace_smmu_add_mr(name); | ||
42 | -- | ||
43 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
1 | 2 | ||
3 | Addresses targeting the second translation table (TTB1) in the SMMU have | ||
4 | all upper bits set (except for the top byte when TBI is enabled). Fix | ||
5 | the TTB1 check. | ||
6 | |||
7 | Reported-by: Ola Hugosson <ola.hugosson@arm.com> | ||
8 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> | ||
11 | Message-id: 20230214171921.1917916-3-jean-philippe@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | hw/arm/smmu-common.c | 2 +- | ||
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
16 | |||
17 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/smmu-common.c | ||
20 | +++ b/hw/arm/smmu-common.c | ||
21 | @@ -XXX,XX +XXX,XX @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova) | ||
22 | /* there is a ttbr0 region and we are in it (high bits all zero) */ | ||
23 | return &cfg->tt[0]; | ||
24 | } else if (cfg->tt[1].tsz && | ||
25 | - !extract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte)) { | ||
26 | + sextract64(iova, 64 - cfg->tt[1].tsz, cfg->tt[1].tsz - tbi_byte) == -1) { | ||
27 | /* there is a ttbr1 region and we are in it (high bits all one) */ | ||
28 | return &cfg->tt[1]; | ||
29 | } else if (!cfg->tt[0].tsz) { | ||
30 | -- | ||
31 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 3 | make it clearer from the name that this is a tcg-only function. |
4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | |
5 | Message-id: 20180110063337.21538-2-richard.henderson@linaro.org | 5 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/translate-a64.c | 44 ++++++++++++++++++++++++++++---------------- | 12 | target/arm/helper.c | 4 ++-- |
9 | 1 file changed, 28 insertions(+), 16 deletions(-) | 13 | 1 file changed, 2 insertions(+), 2 deletions(-) |
10 | 14 | ||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate-a64.c | 17 | --- a/target/arm/helper.c |
14 | +++ b/target/arm/translate-a64.c | 18 | +++ b/target/arm/helper.c |
15 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn) | 19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
16 | } | 20 | * trapped to the hypervisor in KVM. |
17 | } | 21 | */ |
18 | 22 | #ifdef CONFIG_TCG | |
19 | +/* The imm8 encodes the sign bit, enough bits to represent an exponent in | 23 | -static void handle_semihosting(CPUState *cs) |
20 | + * the range 01....1xx to 10....0xx, and the most significant 4 bits of | 24 | +static void tcg_handle_semihosting(CPUState *cs) |
21 | + * the mantissa; see VFPExpandImm() in the v8 ARM ARM. | 25 | { |
22 | + */ | 26 | ARMCPU *cpu = ARM_CPU(cs); |
23 | +static uint64_t vfp_expand_imm(int size, uint8_t imm8) | 27 | CPUARMState *env = &cpu->env; |
24 | +{ | 28 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) |
25 | + uint64_t imm; | 29 | */ |
26 | + | 30 | #ifdef CONFIG_TCG |
27 | + switch (size) { | 31 | if (cs->exception_index == EXCP_SEMIHOST) { |
28 | + case MO_64: | 32 | - handle_semihosting(cs); |
29 | + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | 33 | + tcg_handle_semihosting(cs); |
30 | + (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | | ||
31 | + extract32(imm8, 0, 6); | ||
32 | + imm <<= 48; | ||
33 | + break; | ||
34 | + case MO_32: | ||
35 | + imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | ||
36 | + (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | | ||
37 | + (extract32(imm8, 0, 6) << 3); | ||
38 | + imm <<= 16; | ||
39 | + break; | ||
40 | + default: | ||
41 | + g_assert_not_reached(); | ||
42 | + } | ||
43 | + return imm; | ||
44 | +} | ||
45 | + | ||
46 | /* Floating point immediate | ||
47 | * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0 | ||
48 | * +---+---+---+-----------+------+---+------------+-------+------+------+ | ||
49 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn) | ||
50 | return; | 34 | return; |
51 | } | 35 | } |
52 | 36 | #endif | |
53 | - /* The imm8 encodes the sign bit, enough bits to represent | ||
54 | - * an exponent in the range 01....1xx to 10....0xx, | ||
55 | - * and the most significant 4 bits of the mantissa; see | ||
56 | - * VFPExpandImm() in the v8 ARM ARM. | ||
57 | - */ | ||
58 | - if (is_double) { | ||
59 | - imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | ||
60 | - (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) | | ||
61 | - extract32(imm8, 0, 6); | ||
62 | - imm <<= 48; | ||
63 | - } else { | ||
64 | - imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) | | ||
65 | - (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) | | ||
66 | - (extract32(imm8, 0, 6) << 3); | ||
67 | - imm <<= 16; | ||
68 | - } | ||
69 | + imm = vfp_expand_imm(MO_32 + is_double, imm8); | ||
70 | |||
71 | tcg_res = tcg_const_i64(imm); | ||
72 | write_fp_dreg(s, rd, tcg_res); | ||
73 | -- | 37 | -- |
74 | 2.7.4 | 38 | 2.34.1 |
75 | 39 | ||
76 | 40 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | for "all" builds (tcg + kvm), we want to avoid doing |
4 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 4 | the psci check if tcg is built-in, but not enabled. |
5 | Message-id: 20180115182436.2066-8-f4bug@amsat.org | 5 | |
6 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | hw/sd/sdhci.c | 7 ++++--- | 12 | target/arm/helper.c | 3 ++- |
9 | 1 file changed, 4 insertions(+), 3 deletions(-) | 13 | 1 file changed, 2 insertions(+), 1 deletion(-) |
10 | 14 | ||
11 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 15 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
12 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/sd/sdhci.c | 17 | --- a/target/arm/helper.c |
14 | +++ b/hw/sd/sdhci.c | 18 | +++ b/target/arm/helper.c |
15 | @@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) | 19 | @@ -XXX,XX +XXX,XX @@ |
16 | ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); | 20 | #include "hw/irq.h" |
17 | break; | 21 | #include "sysemu/cpu-timers.h" |
18 | default: | 22 | #include "sysemu/kvm.h" |
19 | - ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset); | 23 | +#include "sysemu/tcg.h" |
20 | + qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " | 24 | #include "qapi/qapi-commands-machine-target.h" |
21 | + "not implemented\n", size, offset); | 25 | #include "qapi/error.h" |
22 | break; | 26 | #include "qemu/guest-random.h" |
27 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | ||
28 | env->exception.syndrome); | ||
23 | } | 29 | } |
24 | 30 | ||
25 | @@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) | 31 | - if (arm_is_psci_call(cpu, cs->exception_index)) { |
26 | sdhci_update_irq(s); | 32 | + if (tcg_enabled() && arm_is_psci_call(cpu, cs->exception_index)) { |
27 | break; | 33 | arm_handle_psci_call(cpu); |
28 | default: | 34 | qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); |
29 | - ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", | 35 | return; |
30 | - size, (int)offset, value >> shift, value >> shift); | ||
31 | + qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " | ||
32 | + "not implemented\n", size, offset, value >> shift); | ||
33 | break; | ||
34 | } | ||
35 | DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", | ||
36 | -- | 36 | -- |
37 | 2.7.4 | 37 | 2.34.1 |
38 | 38 | ||
39 | 39 | diff view generated by jsdifflib |
1 | For PMSAv7, the v7A/R Arm ARM defines that setting AP to 0b111 | 1 | From: Claudio Fontana <cfontana@suse.de> |
---|---|---|---|
2 | is an UNPREDICTABLE reserved combination. However, for v7M | ||
3 | this value is documented as having the same behaviour as 0b110: | ||
4 | read-only for both privileged and unprivileged. Accept this | ||
5 | value on an M profile core rather than treating it as a guest | ||
6 | error and a no-access page. | ||
7 | 2 | ||
8 | Reported-by: Andy Gross <andy.gross@linaro.org> | 3 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
6 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Message-id: 1512742402-31669-1-git-send-email-peter.maydell@linaro.org | ||
12 | --- | 8 | --- |
13 | target/arm/helper.c | 14 ++++++++++++++ | 9 | target/arm/helper.c | 12 +++++++----- |
14 | 1 file changed, 14 insertions(+) | 10 | 1 file changed, 7 insertions(+), 5 deletions(-) |
15 | 11 | ||
16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 12 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
17 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/helper.c | 14 | --- a/target/arm/helper.c |
19 | +++ b/target/arm/helper.c | 15 | +++ b/target/arm/helper.c |
20 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, | 16 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
21 | case 6: | 17 | unsigned int cur_el = arm_current_el(env); |
22 | *prot |= PAGE_READ | PAGE_EXEC; | 18 | int rt; |
23 | break; | 19 | |
24 | + case 7: | 20 | - /* |
25 | + /* for v7M, same as 6; for R profile a reserved value */ | 21 | - * Note that new_el can never be 0. If cur_el is 0, then |
26 | + if (arm_feature(env, ARM_FEATURE_M)) { | 22 | - * el0_a64 is is_a64(), else el0_a64 is ignored. |
27 | + *prot |= PAGE_READ | PAGE_EXEC; | 23 | - */ |
28 | + break; | 24 | - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); |
29 | + } | 25 | + if (tcg_enabled()) { |
30 | + /* fall through */ | 26 | + /* |
31 | default: | 27 | + * Note that new_el can never be 0. If cur_el is 0, then |
32 | qemu_log_mask(LOG_GUEST_ERROR, | 28 | + * el0_a64 is is_a64(), else el0_a64 is ignored. |
33 | "DRACR[%d]: Bad value for AP bits: 0x%" | 29 | + */ |
34 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, | 30 | + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); |
35 | case 6: | 31 | + } |
36 | *prot |= PAGE_READ | PAGE_EXEC; | 32 | |
37 | break; | 33 | if (cur_el < new_el) { |
38 | + case 7: | 34 | /* |
39 | + /* for v7M, same as 6; for R profile a reserved value */ | ||
40 | + if (arm_feature(env, ARM_FEATURE_M)) { | ||
41 | + *prot |= PAGE_READ | PAGE_EXEC; | ||
42 | + break; | ||
43 | + } | ||
44 | + /* fall through */ | ||
45 | default: | ||
46 | qemu_log_mask(LOG_GUEST_ERROR, | ||
47 | "DRACR[%d]: Bad value for AP bits: 0x%" | ||
48 | -- | 35 | -- |
49 | 2.7.4 | 36 | 2.34.1 |
50 | 37 | ||
51 | 38 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Add a 'dma' property allowing machine creation to provide the address-space | 3 | Move this earlier to make the next patch diff cleaner. While here |
4 | SDHCI DMA operates on. | 4 | update the comment slightly to not give the impression that the |
5 | misalignment affects only TCG. | ||
5 | 6 | ||
6 | [based on a patch from Alistair Francis <alistair.francis@xilinx.com> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | from qemu/xilinx tag xilinx-v2016.1] | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
9 | Message-id: 20180115182436.2066-15-f4bug@amsat.org | 10 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 12 | --- |
12 | include/hw/sd/sdhci.h | 1 + | 13 | target/arm/machine.c | 18 +++++++++--------- |
13 | hw/sd/sdhci.c | 18 +++++++++++++++++- | 14 | 1 file changed, 9 insertions(+), 9 deletions(-) |
14 | 2 files changed, 18 insertions(+), 1 deletion(-) | ||
15 | 15 | ||
16 | diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h | 16 | diff --git a/target/arm/machine.c b/target/arm/machine.c |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/sd/sdhci.h | 18 | --- a/target/arm/machine.c |
19 | +++ b/include/hw/sd/sdhci.h | 19 | +++ b/target/arm/machine.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | 20 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
21 | SDBus sdbus; | 21 | } |
22 | MemoryRegion iomem; | 22 | } |
23 | AddressSpace *dma_as; | 23 | |
24 | + MemoryRegion *dma_mr; | 24 | + /* |
25 | 25 | + * Misaligned thumb pc is architecturally impossible. Fail the | |
26 | QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ | 26 | + * incoming migration. For TCG it would trigger the assert in |
27 | QEMUTimer *transfer_timer; | 27 | + * thumb_tr_translate_insn(). |
28 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 28 | + */ |
29 | index XXXXXXX..XXXXXXX 100644 | 29 | + if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { |
30 | --- a/hw/sd/sdhci.c | 30 | + return -1; |
31 | +++ b/hw/sd/sdhci.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static Property sdhci_sysbus_properties[] = { | ||
33 | DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), | ||
34 | DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, | ||
35 | false), | ||
36 | + DEFINE_PROP_LINK("dma", SDHCIState, | ||
37 | + dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), | ||
38 | DEFINE_PROP_END_OF_LIST(), | ||
39 | }; | ||
40 | |||
41 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_init(Object *obj) | ||
42 | static void sdhci_sysbus_finalize(Object *obj) | ||
43 | { | ||
44 | SDHCIState *s = SYSBUS_SDHCI(obj); | ||
45 | + | ||
46 | + if (s->dma_mr) { | ||
47 | + object_unparent(OBJECT(s->dma_mr)); | ||
48 | + } | 31 | + } |
49 | + | 32 | + |
50 | sdhci_uninitfn(s); | 33 | hw_breakpoint_update_all(cpu); |
51 | } | 34 | hw_watchpoint_update_all(cpu); |
52 | 35 | ||
53 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) | 36 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
54 | return; | 37 | } |
55 | } | 38 | } |
56 | 39 | ||
57 | - s->dma_as = &address_space_memory; | 40 | - /* |
58 | + if (s->dma_mr) { | 41 | - * Misaligned thumb pc is architecturally impossible. |
59 | + address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); | 42 | - * We have an assert in thumb_tr_translate_insn to verify this. |
60 | + } else { | 43 | - * Fail an incoming migrate to avoid this assert. |
61 | + /* use system_memory() if property "dma" not set */ | 44 | - */ |
62 | + s->dma_as = &address_space_memory; | 45 | - if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { |
63 | + } | 46 | - return -1; |
64 | 47 | - } | |
65 | sysbus_init_irq(sbd, &s->irq); | 48 | - |
66 | sysbus_init_mmio(sbd, &s->iomem); | 49 | if (!kvm_enabled()) { |
67 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp) | 50 | pmu_op_finish(&cpu->env); |
68 | SDHCIState *s = SYSBUS_SDHCI(dev); | 51 | } |
69 | |||
70 | sdhci_common_unrealize(s, &error_abort); | ||
71 | + | ||
72 | + if (s->dma_mr) { | ||
73 | + address_space_destroy(s->dma_as); | ||
74 | + } | ||
75 | } | ||
76 | |||
77 | static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) | ||
78 | -- | 52 | -- |
79 | 2.7.4 | 53 | 2.34.1 |
80 | 54 | ||
81 | 55 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Now both inherited classes appear as DEVICE_CATEGORY_STORAGE. | 3 | Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have |
4 | 4 | a cpregs.h header which is more suitable for this code. | |
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | |
6 | Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> | 6 | Code moved verbatim. |
7 | Message-id: 20180115182436.2066-5-f4bug@amsat.org | 7 | |
8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 13 | --- |
10 | hw/sd/sdhci.c | 18 +++++++++++++----- | 14 | target/arm/cpregs.h | 98 +++++++++++++++++++++++++++++++++++++++++++++ |
11 | 1 file changed, 13 insertions(+), 5 deletions(-) | 15 | target/arm/cpu.h | 91 ----------------------------------------- |
12 | 16 | 2 files changed, 98 insertions(+), 91 deletions(-) | |
13 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 17 | |
18 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/sd/sdhci.c | 20 | --- a/target/arm/cpregs.h |
16 | +++ b/hw/sd/sdhci.c | 21 | +++ b/target/arm/cpregs.h |
17 | @@ -XXX,XX +XXX,XX @@ const VMStateDescription sdhci_vmstate = { | 22 | @@ -XXX,XX +XXX,XX @@ enum { |
18 | }, | 23 | ARM_CP_SME = 1 << 19, |
19 | }; | 24 | }; |
20 | 25 | ||
21 | +static void sdhci_common_class_init(ObjectClass *klass, void *data) | 26 | +/* |
27 | + * Interface for defining coprocessor registers. | ||
28 | + * Registers are defined in tables of arm_cp_reginfo structs | ||
29 | + * which are passed to define_arm_cp_regs(). | ||
30 | + */ | ||
31 | + | ||
32 | +/* | ||
33 | + * When looking up a coprocessor register we look for it | ||
34 | + * via an integer which encodes all of: | ||
35 | + * coprocessor number | ||
36 | + * Crn, Crm, opc1, opc2 fields | ||
37 | + * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
38 | + * or via MRRC/MCRR?) | ||
39 | + * non-secure/secure bank (AArch32 only) | ||
40 | + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
41 | + * (In this case crn and opc2 should be zero.) | ||
42 | + * For AArch64, there is no 32/64 bit size distinction; | ||
43 | + * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
44 | + * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
45 | + * to be easy to convert to and from the KVM encodings, and also | ||
46 | + * so that the hashtable can contain both AArch32 and AArch64 | ||
47 | + * registers (to allow for interprocessing where we might run | ||
48 | + * 32 bit code on a 64 bit core). | ||
49 | + */ | ||
50 | +/* | ||
51 | + * This bit is private to our hashtable cpreg; in KVM register | ||
52 | + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
53 | + * in the upper bits of the 64 bit ID. | ||
54 | + */ | ||
55 | +#define CP_REG_AA64_SHIFT 28 | ||
56 | +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
57 | + | ||
58 | +/* | ||
59 | + * To enable banking of coprocessor registers depending on ns-bit we | ||
60 | + * add a bit to distinguish between secure and non-secure cpregs in the | ||
61 | + * hashtable. | ||
62 | + */ | ||
63 | +#define CP_REG_NS_SHIFT 29 | ||
64 | +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
65 | + | ||
66 | +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
67 | + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
68 | + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
69 | + | ||
70 | +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
71 | + (CP_REG_AA64_MASK | \ | ||
72 | + ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
73 | + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
74 | + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
75 | + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
76 | + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
77 | + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
78 | + | ||
79 | +/* | ||
80 | + * Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
81 | + * version used as a key for the coprocessor register hashtable | ||
82 | + */ | ||
83 | +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
22 | +{ | 84 | +{ |
23 | + DeviceClass *dc = DEVICE_CLASS(klass); | 85 | + uint32_t cpregid = kvmid; |
24 | + | 86 | + if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { |
25 | + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | 87 | + cpregid |= CP_REG_AA64_MASK; |
26 | + dc->vmsd = &sdhci_vmstate; | 88 | + } else { |
27 | + dc->reset = sdhci_poweron_reset; | 89 | + if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { |
90 | + cpregid |= (1 << 15); | ||
91 | + } | ||
92 | + | ||
93 | + /* | ||
94 | + * KVM is always non-secure so add the NS flag on AArch32 register | ||
95 | + * entries. | ||
96 | + */ | ||
97 | + cpregid |= 1 << CP_REG_NS_SHIFT; | ||
98 | + } | ||
99 | + return cpregid; | ||
28 | +} | 100 | +} |
29 | + | 101 | + |
30 | /* --- qdev PCI --- */ | 102 | +/* |
31 | 103 | + * Convert a truncated 32 bit hashtable key into the full | |
32 | static Property sdhci_pci_properties[] = { | 104 | + * 64 bit KVM register ID. |
33 | @@ -XXX,XX +XXX,XX @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data) | 105 | + */ |
34 | k->vendor_id = PCI_VENDOR_ID_REDHAT; | 106 | +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) |
35 | k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; | 107 | +{ |
36 | k->class_id = PCI_CLASS_SYSTEM_SDHCI; | 108 | + uint64_t kvmid; |
37 | - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); | 109 | + |
38 | - dc->vmsd = &sdhci_vmstate; | 110 | + if (cpregid & CP_REG_AA64_MASK) { |
39 | dc->props = sdhci_pci_properties; | 111 | + kvmid = cpregid & ~CP_REG_AA64_MASK; |
40 | - dc->reset = sdhci_poweron_reset; | 112 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; |
41 | + | 113 | + } else { |
42 | + sdhci_common_class_init(klass, data); | 114 | + kvmid = cpregid & ~(1 << 15); |
43 | } | 115 | + if (cpregid & (1 << 15)) { |
44 | 116 | + kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | |
45 | static const TypeInfo sdhci_pci_info = { | 117 | + } else { |
46 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) | 118 | + kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; |
119 | + } | ||
120 | + } | ||
121 | + return kvmid; | ||
122 | +} | ||
123 | + | ||
124 | /* | ||
125 | * Valid values for ARMCPRegInfo state field, indicating which of | ||
126 | * the AArch32 and AArch64 execution states this register is visible in. | ||
127 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
128 | index XXXXXXX..XXXXXXX 100644 | ||
129 | --- a/target/arm/cpu.h | ||
130 | +++ b/target/arm/cpu.h | ||
131 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_list(void); | ||
132 | uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | ||
133 | uint32_t cur_el, bool secure); | ||
134 | |||
135 | -/* Interface for defining coprocessor registers. | ||
136 | - * Registers are defined in tables of arm_cp_reginfo structs | ||
137 | - * which are passed to define_arm_cp_regs(). | ||
138 | - */ | ||
139 | - | ||
140 | -/* When looking up a coprocessor register we look for it | ||
141 | - * via an integer which encodes all of: | ||
142 | - * coprocessor number | ||
143 | - * Crn, Crm, opc1, opc2 fields | ||
144 | - * 32 or 64 bit register (ie is it accessed via MRC/MCR | ||
145 | - * or via MRRC/MCRR?) | ||
146 | - * non-secure/secure bank (AArch32 only) | ||
147 | - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. | ||
148 | - * (In this case crn and opc2 should be zero.) | ||
149 | - * For AArch64, there is no 32/64 bit size distinction; | ||
150 | - * instead all registers have a 2 bit op0, 3 bit op1 and op2, | ||
151 | - * and 4 bit CRn and CRm. The encoding patterns are chosen | ||
152 | - * to be easy to convert to and from the KVM encodings, and also | ||
153 | - * so that the hashtable can contain both AArch32 and AArch64 | ||
154 | - * registers (to allow for interprocessing where we might run | ||
155 | - * 32 bit code on a 64 bit core). | ||
156 | - */ | ||
157 | -/* This bit is private to our hashtable cpreg; in KVM register | ||
158 | - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 | ||
159 | - * in the upper bits of the 64 bit ID. | ||
160 | - */ | ||
161 | -#define CP_REG_AA64_SHIFT 28 | ||
162 | -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) | ||
163 | - | ||
164 | -/* To enable banking of coprocessor registers depending on ns-bit we | ||
165 | - * add a bit to distinguish between secure and non-secure cpregs in the | ||
166 | - * hashtable. | ||
167 | - */ | ||
168 | -#define CP_REG_NS_SHIFT 29 | ||
169 | -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) | ||
170 | - | ||
171 | -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ | ||
172 | - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ | ||
173 | - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) | ||
174 | - | ||
175 | -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ | ||
176 | - (CP_REG_AA64_MASK | \ | ||
177 | - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ | ||
178 | - ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ | ||
179 | - ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ | ||
180 | - ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ | ||
181 | - ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ | ||
182 | - ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) | ||
183 | - | ||
184 | -/* Convert a full 64 bit KVM register ID to the truncated 32 bit | ||
185 | - * version used as a key for the coprocessor register hashtable | ||
186 | - */ | ||
187 | -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) | ||
188 | -{ | ||
189 | - uint32_t cpregid = kvmid; | ||
190 | - if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { | ||
191 | - cpregid |= CP_REG_AA64_MASK; | ||
192 | - } else { | ||
193 | - if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) { | ||
194 | - cpregid |= (1 << 15); | ||
195 | - } | ||
196 | - | ||
197 | - /* KVM is always non-secure so add the NS flag on AArch32 register | ||
198 | - * entries. | ||
199 | - */ | ||
200 | - cpregid |= 1 << CP_REG_NS_SHIFT; | ||
201 | - } | ||
202 | - return cpregid; | ||
203 | -} | ||
204 | - | ||
205 | -/* Convert a truncated 32 bit hashtable key into the full | ||
206 | - * 64 bit KVM register ID. | ||
207 | - */ | ||
208 | -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | ||
209 | -{ | ||
210 | - uint64_t kvmid; | ||
211 | - | ||
212 | - if (cpregid & CP_REG_AA64_MASK) { | ||
213 | - kvmid = cpregid & ~CP_REG_AA64_MASK; | ||
214 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64; | ||
215 | - } else { | ||
216 | - kvmid = cpregid & ~(1 << 15); | ||
217 | - if (cpregid & (1 << 15)) { | ||
218 | - kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; | ||
219 | - } else { | ||
220 | - kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; | ||
221 | - } | ||
222 | - } | ||
223 | - return kvmid; | ||
224 | -} | ||
225 | - | ||
226 | /* Return the highest implemented Exception Level */ | ||
227 | static inline int arm_highest_el(CPUARMState *env) | ||
47 | { | 228 | { |
48 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
49 | |||
50 | - dc->vmsd = &sdhci_vmstate; | ||
51 | dc->props = sdhci_sysbus_properties; | ||
52 | dc->realize = sdhci_sysbus_realize; | ||
53 | - dc->reset = sdhci_poweron_reset; | ||
54 | + | ||
55 | + sdhci_common_class_init(klass, data); | ||
56 | } | ||
57 | |||
58 | static const TypeInfo sdhci_sysbus_info = { | ||
59 | -- | 229 | -- |
60 | 2.7.4 | 230 | 2.34.1 |
61 | 231 | ||
62 | 232 | diff view generated by jsdifflib |
1 | Since milkymist-memcard is still using the legacy SD card API, | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | the SD card created by sd_init() is not plugged into any bus. | ||
3 | This means that the controller has to reset it manually. | ||
4 | 2 | ||
5 | Failing to do this mostly didn't affect the guest since the | 3 | If a test was tagged with the "accel" tag and the specified |
6 | guest typically does a programmed SD card reset as part of | 4 | accelerator it not present in the qemu binary, cancel the test. |
7 | its SD controller driver initialization, but meant that | ||
8 | migration failed because it's only in sd_reset() that we | ||
9 | set up the wpgrps_size field. | ||
10 | 5 | ||
11 | Cc: qemu-stable@nongnu.org | 6 | We can now write tests without explicit calls to require_accelerator, |
7 | just the tag is enough. | ||
8 | |||
9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
14 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
15 | Message-id: 1515506513-31961-3-git-send-email-peter.maydell@linaro.org | ||
16 | --- | 13 | --- |
17 | hw/sd/milkymist-memcard.c | 4 ++++ | 14 | tests/avocado/avocado_qemu/__init__.py | 4 ++++ |
18 | 1 file changed, 4 insertions(+) | 15 | 1 file changed, 4 insertions(+) |
19 | 16 | ||
20 | diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c | 17 | diff --git a/tests/avocado/avocado_qemu/__init__.py b/tests/avocado/avocado_qemu/__init__.py |
21 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/sd/milkymist-memcard.c | 19 | --- a/tests/avocado/avocado_qemu/__init__.py |
23 | +++ b/hw/sd/milkymist-memcard.c | 20 | +++ b/tests/avocado/avocado_qemu/__init__.py |
24 | @@ -XXX,XX +XXX,XX @@ static void milkymist_memcard_reset(DeviceState *d) | 21 | @@ -XXX,XX +XXX,XX @@ def setUp(self): |
25 | for (i = 0; i < R_MAX; i++) { | 22 | |
26 | s->regs[i] = 0; | 23 | super().setUp('qemu-system-') |
27 | } | 24 | |
28 | + /* Since we're still using the legacy SD API the card is not plugged | 25 | + accel_required = self._get_unique_tag_val('accel') |
29 | + * into any bus, and we must reset it manually. | 26 | + if accel_required: |
30 | + */ | 27 | + self.require_accelerator(accel_required) |
31 | + device_reset(DEVICE(s->card)); | 28 | + |
32 | } | 29 | self.machine = self.params.get('machine', |
33 | 30 | default=self._get_unique_tag_val('machine')) | |
34 | static int milkymist_memcard_init(SysBusDevice *dev) | 31 | |
35 | -- | 32 | -- |
36 | 2.7.4 | 33 | 2.34.1 |
37 | 34 | ||
38 | 35 | diff view generated by jsdifflib |
1 | Since pl181 is still using the legacy SD card API, the SD | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | card created by sd_init() is not plugged into any bus. This | ||
3 | means that the controller has to reset it manually. | ||
4 | 2 | ||
5 | Failing to do this mostly didn't affect the guest since the | 3 | This allows the test to be skipped when TCG is not present in the QEMU |
6 | guest typically does a programmed SD card reset as part of | 4 | binary. |
7 | its SD controller driver initialization, but meant that | ||
8 | migration failed because it's only in sd_reset() that we | ||
9 | set up the wpgrps_size field. | ||
10 | 5 | ||
11 | Cc: qemu-stable@nongnu.org | 6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
12 | Fixes: https://bugs.launchpad.net/qemu/+bug/1739378 | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
15 | Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
16 | Message-id: 1515506513-31961-2-git-send-email-peter.maydell@linaro.org | ||
17 | --- | 10 | --- |
18 | hw/sd/pl181.c | 4 ++++ | 11 | tests/avocado/boot_linux_console.py | 1 + |
19 | 1 file changed, 4 insertions(+) | 12 | tests/avocado/reverse_debugging.py | 8 ++++++++ |
13 | 2 files changed, 9 insertions(+) | ||
20 | 14 | ||
21 | diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c | 15 | diff --git a/tests/avocado/boot_linux_console.py b/tests/avocado/boot_linux_console.py |
22 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/sd/pl181.c | 17 | --- a/tests/avocado/boot_linux_console.py |
24 | +++ b/hw/sd/pl181.c | 18 | +++ b/tests/avocado/boot_linux_console.py |
25 | @@ -XXX,XX +XXX,XX @@ static void pl181_reset(DeviceState *d) | 19 | @@ -XXX,XX +XXX,XX @@ def test_arm_orangepi_uboot_netbsd9(self): |
26 | 20 | ||
27 | /* We can assume our GPIO outputs have been wired up now */ | 21 | def test_aarch64_raspi3_atf(self): |
28 | sd_set_cb(s->card, s->cardstatus[0], s->cardstatus[1]); | 22 | """ |
29 | + /* Since we're still using the legacy SD API the card is not plugged | 23 | + :avocado: tags=accel:tcg |
30 | + * into any bus, and we must reset it manually. | 24 | :avocado: tags=arch:aarch64 |
31 | + */ | 25 | :avocado: tags=machine:raspi3b |
32 | + device_reset(DEVICE(s->card)); | 26 | :avocado: tags=cpu:cortex-a53 |
33 | } | 27 | diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py |
34 | 28 | index XXXXXXX..XXXXXXX 100644 | |
35 | static void pl181_init(Object *obj) | 29 | --- a/tests/avocado/reverse_debugging.py |
30 | +++ b/tests/avocado/reverse_debugging.py | ||
31 | @@ -XXX,XX +XXX,XX @@ def reverse_debugging(self, shift=7, args=None): | ||
32 | vm.shutdown() | ||
33 | |||
34 | class ReverseDebugging_X86_64(ReverseDebugging): | ||
35 | + """ | ||
36 | + :avocado: tags=accel:tcg | ||
37 | + """ | ||
38 | + | ||
39 | REG_PC = 0x10 | ||
40 | REG_CS = 0x12 | ||
41 | def get_pc(self, g): | ||
42 | @@ -XXX,XX +XXX,XX @@ def test_x86_64_pc(self): | ||
43 | self.reverse_debugging() | ||
44 | |||
45 | class ReverseDebugging_AArch64(ReverseDebugging): | ||
46 | + """ | ||
47 | + :avocado: tags=accel:tcg | ||
48 | + """ | ||
49 | + | ||
50 | REG_PC = 32 | ||
51 | |||
52 | # unidentified gitlab timeout problem | ||
36 | -- | 53 | -- |
37 | 2.7.4 | 54 | 2.34.1 |
38 | 55 | ||
39 | 56 | diff view generated by jsdifflib |
1 | Add virt-2.12 machine type. | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a | ||
4 | KVM-only build the 'max' cpu. | ||
5 | |||
6 | Note that we cannot use 'host' here because the qtests can run without | ||
7 | any other accelerator (than qtest) and 'host' depends on KVM being | ||
8 | enabled. | ||
9 | |||
10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
11 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | --- | 14 | --- |
5 | hw/arm/virt.c | 19 +++++++++++++++++-- | 15 | hw/arm/virt.c | 4 ++++ |
6 | 1 file changed, 17 insertions(+), 2 deletions(-) | 16 | 1 file changed, 4 insertions(+) |
7 | 17 | ||
8 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
9 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
10 | --- a/hw/arm/virt.c | 20 | --- a/hw/arm/virt.c |
11 | +++ b/hw/arm/virt.c | 21 | +++ b/hw/arm/virt.c |
12 | @@ -XXX,XX +XXX,XX @@ static void machvirt_machine_init(void) | 22 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) |
13 | } | 23 | mc->minimum_page_bits = 12; |
14 | type_init(machvirt_machine_init); | 24 | mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; |
15 | 25 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; | |
16 | -static void virt_2_11_instance_init(Object *obj) | 26 | +#ifdef CONFIG_TCG |
17 | +static void virt_2_12_instance_init(Object *obj) | 27 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); |
18 | { | 28 | +#else |
19 | VirtMachineState *vms = VIRT_MACHINE(obj); | 29 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("max"); |
20 | VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms); | 30 | +#endif |
21 | @@ -XXX,XX +XXX,XX @@ static void virt_2_11_instance_init(Object *obj) | 31 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; |
22 | vms->irqmap = a15irqmap; | 32 | mc->kvm_type = virt_kvm_type; |
23 | } | 33 | assert(!mc->get_hotplug_handler); |
24 | |||
25 | +static void virt_machine_2_12_options(MachineClass *mc) | ||
26 | +{ | ||
27 | +} | ||
28 | +DEFINE_VIRT_MACHINE_AS_LATEST(2, 12) | ||
29 | + | ||
30 | +#define VIRT_COMPAT_2_11 \ | ||
31 | + HW_COMPAT_2_11 | ||
32 | + | ||
33 | +static void virt_2_11_instance_init(Object *obj) | ||
34 | +{ | ||
35 | + virt_2_12_instance_init(obj); | ||
36 | +} | ||
37 | + | ||
38 | static void virt_machine_2_11_options(MachineClass *mc) | ||
39 | { | ||
40 | + virt_machine_2_12_options(mc); | ||
41 | + SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11); | ||
42 | } | ||
43 | -DEFINE_VIRT_MACHINE_AS_LATEST(2, 11) | ||
44 | +DEFINE_VIRT_MACHINE(2, 11) | ||
45 | |||
46 | #define VIRT_COMPAT_2_10 \ | ||
47 | HW_COMPAT_2_10 | ||
48 | -- | 34 | -- |
49 | 2.7.4 | 35 | 2.34.1 |
50 | |||
51 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
---|---|---|---|
2 | 2 | ||
3 | While SysBus devices can use the get_system_memory() address space, | 3 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
4 | PCI devices should use the bus master address space for DMA. | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | 5 | Acked-by: Thomas Huth <thuth@redhat.com> | |
6 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20180115182436.2066-14-f4bug@amsat.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 7 | --- |
12 | include/hw/sd/sdhci.h | 1 + | 8 | tests/qtest/arm-cpu-features.c | 28 ++++++++++++++++++---------- |
13 | hw/sd/sdhci.c | 29 +++++++++++++++-------------- | 9 | 1 file changed, 18 insertions(+), 10 deletions(-) |
14 | 2 files changed, 16 insertions(+), 14 deletions(-) | ||
15 | 10 | ||
16 | diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h | 11 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c |
17 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/sd/sdhci.h | 13 | --- a/tests/qtest/arm-cpu-features.c |
19 | +++ b/include/hw/sd/sdhci.h | 14 | +++ b/tests/qtest/arm-cpu-features.c |
20 | @@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState { | 15 | @@ -XXX,XX +XXX,XX @@ |
21 | /*< public >*/ | 16 | #define SVE_MAX_VQ 16 |
22 | SDBus sdbus; | 17 | |
23 | MemoryRegion iomem; | 18 | #define MACHINE "-machine virt,gic-version=max -accel tcg " |
24 | + AddressSpace *dma_as; | 19 | -#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg " |
25 | 20 | +#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm " | |
26 | QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ | 21 | #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ |
27 | QEMUTimer *transfer_timer; | 22 | " 'arguments': { 'type': 'full', " |
28 | diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c | 23 | #define QUERY_TAIL "}}" |
29 | index XXXXXXX..XXXXXXX 100644 | 24 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) |
30 | --- a/hw/sd/sdhci.c | 25 | { |
31 | +++ b/hw/sd/sdhci.c | 26 | g_test_init(&argc, &argv, NULL); |
32 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) | 27 | |
33 | s->blkcnt--; | 28 | - qtest_add_data_func("/arm/query-cpu-model-expansion", |
34 | } | 29 | - NULL, test_query_cpu_model_expansion); |
35 | } | 30 | + if (qtest_has_accel("tcg")) { |
36 | - dma_memory_write(&address_space_memory, s->sdmasysad, | 31 | + qtest_add_data_func("/arm/query-cpu-model-expansion", |
37 | + dma_memory_write(s->dma_as, s->sdmasysad, | 32 | + NULL, test_query_cpu_model_expansion); |
38 | &s->fifo_buffer[begin], s->data_count - begin); | 33 | + } |
39 | s->sdmasysad += s->data_count - begin; | 34 | + |
40 | if (s->data_count == block_size) { | 35 | + if (!g_str_equal(qtest_get_arch(), "aarch64")) { |
41 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) | 36 | + goto out; |
42 | s->data_count = block_size; | 37 | + } |
43 | boundary_count -= block_size - begin; | 38 | |
44 | } | 39 | /* |
45 | - dma_memory_read(&address_space_memory, s->sdmasysad, | 40 | * For now we only run KVM specific tests with AArch64 QEMU in |
46 | + dma_memory_read(s->dma_as, s->sdmasysad, | 41 | * order avoid attempting to run an AArch32 QEMU with KVM on |
47 | &s->fifo_buffer[begin], s->data_count - begin); | 42 | * AArch64 hosts. That won't work and isn't easy to detect. |
48 | s->sdmasysad += s->data_count - begin; | 43 | */ |
49 | if (s->data_count == block_size) { | 44 | - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) { |
50 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s) | 45 | + if (qtest_has_accel("kvm")) { |
51 | for (n = 0; n < datacnt; n++) { | 46 | /* |
52 | s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); | 47 | * This tests target the 'host' CPU type, so register it only if |
53 | } | 48 | * KVM is available. |
54 | - dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer, | 49 | */ |
55 | - datacnt); | 50 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", |
56 | + dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); | 51 | NULL, test_query_cpu_model_expansion_kvm); |
57 | } else { | 52 | - } |
58 | - dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer, | 53 | |
59 | - datacnt); | 54 | - if (g_str_equal(qtest_get_arch(), "aarch64")) { |
60 | + dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); | 55 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", |
61 | for (n = 0; n < datacnt; n++) { | 56 | - NULL, sve_tests_sve_max_vq_8); |
62 | sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); | 57 | - qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", |
63 | } | 58 | - NULL, sve_tests_sve_off); |
64 | @@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) | 59 | qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", |
65 | hwaddr entry_addr = (hwaddr)s->admasysaddr; | 60 | NULL, sve_tests_sve_off_kvm); |
66 | switch (SDHC_DMA_TYPE(s->hostctl)) { | ||
67 | case SDHC_CTRL_ADMA2_32: | ||
68 | - dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2, | ||
69 | + dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, | ||
70 | sizeof(adma2)); | ||
71 | adma2 = le64_to_cpu(adma2); | ||
72 | /* The spec does not specify endianness of descriptor table. | ||
73 | @@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) | ||
74 | dscr->incr = 8; | ||
75 | break; | ||
76 | case SDHC_CTRL_ADMA1_32: | ||
77 | - dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1, | ||
78 | + dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, | ||
79 | sizeof(adma1)); | ||
80 | adma1 = le32_to_cpu(adma1); | ||
81 | dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); | ||
82 | @@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) | ||
83 | } | ||
84 | break; | ||
85 | case SDHC_CTRL_ADMA2_64: | ||
86 | - dma_memory_read(&address_space_memory, entry_addr, | ||
87 | + dma_memory_read(s->dma_as, entry_addr, | ||
88 | (uint8_t *)(&dscr->attr), 1); | ||
89 | - dma_memory_read(&address_space_memory, entry_addr + 2, | ||
90 | + dma_memory_read(s->dma_as, entry_addr + 2, | ||
91 | (uint8_t *)(&dscr->length), 2); | ||
92 | dscr->length = le16_to_cpu(dscr->length); | ||
93 | - dma_memory_read(&address_space_memory, entry_addr + 4, | ||
94 | + dma_memory_read(s->dma_as, entry_addr + 4, | ||
95 | (uint8_t *)(&dscr->addr), 8); | ||
96 | dscr->attr = le64_to_cpu(dscr->attr); | ||
97 | dscr->attr &= 0xfffffff8; | ||
98 | @@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s) | ||
99 | s->data_count = block_size; | ||
100 | length -= block_size - begin; | ||
101 | } | ||
102 | - dma_memory_write(&address_space_memory, dscr.addr, | ||
103 | + dma_memory_write(s->dma_as, dscr.addr, | ||
104 | &s->fifo_buffer[begin], | ||
105 | s->data_count - begin); | ||
106 | dscr.addr += s->data_count - begin; | ||
107 | @@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s) | ||
108 | s->data_count = block_size; | ||
109 | length -= block_size - begin; | ||
110 | } | ||
111 | - dma_memory_read(&address_space_memory, dscr.addr, | ||
112 | + dma_memory_read(s->dma_as, dscr.addr, | ||
113 | &s->fifo_buffer[begin], | ||
114 | s->data_count - begin); | ||
115 | dscr.addr += s->data_count - begin; | ||
116 | @@ -XXX,XX +XXX,XX @@ static void sdhci_pci_realize(PCIDevice *dev, Error **errp) | ||
117 | dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ | ||
118 | dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ | ||
119 | s->irq = pci_allocate_irq(dev); | ||
120 | - pci_register_bar(dev, 0, 0, &s->iomem); | ||
121 | + s->dma_as = pci_get_address_space(dev); | ||
122 | + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem); | ||
123 | } | ||
124 | |||
125 | static void sdhci_pci_exit(PCIDevice *dev) | ||
126 | @@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) | ||
127 | return; | ||
128 | } | 61 | } |
129 | 62 | ||
130 | + s->dma_as = &address_space_memory; | 63 | + if (qtest_has_accel("tcg")) { |
64 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8", | ||
65 | + NULL, sve_tests_sve_max_vq_8); | ||
66 | + qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", | ||
67 | + NULL, sve_tests_sve_off); | ||
68 | + } | ||
131 | + | 69 | + |
132 | sysbus_init_irq(sbd, &s->irq); | 70 | +out: |
133 | sysbus_init_mmio(sbd, &s->iomem); | 71 | return g_test_run(); |
134 | } | 72 | } |
135 | -- | 73 | -- |
136 | 2.7.4 | 74 | 2.34.1 |
137 | |||
138 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Fabiano Rosas <farosas@suse.de> | ||
1 | 2 | ||
3 | These tests set -accel tcg, so restrict them to when TCG is present. | ||
4 | |||
5 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
6 | Acked-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | tests/qtest/meson.build | 4 ++-- | ||
11 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
12 | |||
13 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/tests/qtest/meson.build | ||
16 | +++ b/tests/qtest/meson.build | ||
17 | @@ -XXX,XX +XXX,XX @@ qtests_arm = \ | ||
18 | # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional | ||
19 | qtests_aarch64 = \ | ||
20 | (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \ | ||
21 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \ | ||
22 | - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \ | ||
23 | + (config_all.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \ | ||
24 | + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \ | ||
25 | (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \ | ||
26 | (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ | ||
27 | ['arm-cpu-features', | ||
28 | -- | ||
29 | 2.34.1 | diff view generated by jsdifflib |