1
More arm patches (mostly the SDHCI ones from Philippe)
1
Hi; here's the first target-arm pullreq for the 7.0 cycle.
2
2
3
thanks
3
thanks
4
-- PMM
4
-- PMM
5
5
6
The following changes since commit f521eeee3bd060b460c99e605472b7e03967db43:
6
The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
7
7
8
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180115' into staging (2018-01-15 13:17:47 +0000)
8
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2021-12-14 12:46:18 -0800)
9
9
10
are available in the git repository at:
10
are available in the Git repository at:
11
11
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180116
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211215
13
13
14
for you to fetch changes up to 60765b6ceeb4998a0d4220b3a53f1f185061da77:
14
for you to fetch changes up to aed176558806674d030a8305d989d4e6a5073359:
15
15
16
sdhci: add a 'dma' property to the sysbus devices (2018-01-16 13:28:21 +0000)
16
tests/acpi: add expected blob for VIOT test on virt machine (2021-12-15 10:35:26 +0000)
17
17
18
----------------------------------------------------------------
18
----------------------------------------------------------------
19
target-arm queue:
19
target-arm queue:
20
* SDHCI: cleanups and minor bug fixes
20
* ITS: error reporting cleanup
21
* target/arm: minor refactor preparatory to fp16 support
21
* aspeed: improve documentation
22
* omap_ssd, ssi-sd, pl181, milkymist-memcard: reset the SD
22
* Fix STM32F2XX USART data register readout
23
card on controller reset (fixes migration failures)
23
* allow emulated GICv3 to be disabled in non-TCG builds
24
* target/arm: Handle page table walk load failures correctly
24
* fix exception priority for singlestep, misaligned PC, bp, etc
25
* hw/arm/virt: Add virt-2.12 machine type
25
* Correct calculation of tlb range invalidate length
26
* get_phys_addr_pmsav7: Support AP=0b111 for v7M
26
* npcm7xx_emc: fix missing queue_flush
27
* hw/intc/armv7m: Support byte and halfword accesses to CFSR
27
* virt: Add VIOT ACPI table for virtio-iommu
28
* target/i386: Use assert() to sanity-check b1 in SSE decode
29
* Don't include qemu-common unnecessarily
28
30
29
----------------------------------------------------------------
31
----------------------------------------------------------------
30
Andrey Smirnov (1):
32
Alex Bennée (1):
31
sdhci: Implement write method of ACMD12ERRSTS register
33
hw/intc: clean-up error reporting for failed ITS cmd
32
34
33
Peter Maydell (8):
35
Jean-Philippe Brucker (8):
34
hw/intc/armv7m: Support byte and halfword accesses to CFSR
36
hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
35
get_phys_addr_pmsav7: Support AP=0b111 for v7M
37
hw/arm/virt: Remove device tree restriction for virtio-iommu
36
hw/arm/virt: Add virt-2.12 machine type
38
hw/arm/virt: Reject instantiation of multiple IOMMUs
37
target/arm: Handle page table walk load failures correctly
39
hw/arm/virt: Use object_property_set instead of qdev_prop_set
38
hw/sd/pl181: Reset SD card on controller reset
40
tests/acpi: allow updates of VIOT expected data files
39
hw/sd/milkymist-memcard: Reset SD card on controller reset
41
tests/acpi: add test case for VIOT
40
hw/sd/ssi-sd: Reset SD card on controller reset
42
tests/acpi: add expected blobs for VIOT test on q35 machine
41
hw/sd/omap_mmc: Reset SD card on controller reset
43
tests/acpi: add expected blob for VIOT test on virt machine
42
44
43
Philippe Mathieu-Daudé (13):
45
Joel Stanley (4):
44
sdhci: clean up includes
46
docs: aspeed: Add new boards
45
sdhci: remove dead code
47
docs: aspeed: Update OpenBMC image URL
46
sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties
48
docs: aspeed: Give an example of booting a kernel
47
sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init()
49
docs: aspeed: ADC is now modelled
48
sdhci: refactor common sysbus/pci realize() into sdhci_common_realize()
49
sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize()
50
sdhci: use qemu_log_mask(UNIMP) instead of fprintf()
51
sdhci: convert the DPRINT() calls into trace events
52
sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h"
53
sdhci: rename the SDHC_CAPAB register
54
sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only
55
sdhci: fix the PCI device, using the PCI address space for DMA
56
sdhci: add a 'dma' property to the sysbus devices
57
50
58
Richard Henderson (2):
51
Olivier Hériveaux (1):
59
target/arm: Split out vfp_expand_imm
52
Fix STM32F2XX USART data register readout
60
target/arm: Add fp16 support to vfp_expand_imm
61
53
62
hw/sd/sdhci-internal.h | 7 +-
54
Patrick Venture (1):
63
include/hw/sd/sdhci.h | 19 +++-
55
hw/net: npcm7xx_emc fix missing queue_flush
64
target/arm/internals.h | 10 ++
65
hw/arm/virt.c | 19 +++-
66
hw/intc/armv7m_nvic.c | 38 ++++---
67
hw/sd/milkymist-memcard.c | 4 +
68
hw/sd/omap_mmc.c | 14 ++-
69
hw/sd/pl181.c | 4 +
70
hw/sd/sdhci.c | 266 +++++++++++++++++++++++++++------------------
71
hw/sd/ssi-sd.c | 25 ++++-
72
target/arm/helper.c | 53 ++++++++-
73
target/arm/op_helper.c | 7 +-
74
target/arm/translate-a64.c | 49 ++++++---
75
hw/sd/trace-events | 14 +++
76
14 files changed, 362 insertions(+), 167 deletions(-)
77
56
57
Peter Maydell (6):
58
target/i386: Use assert() to sanity-check b1 in SSE decode
59
include/hw/i386: Don't include qemu-common.h in .h files
60
target/hexagon/cpu.h: don't include qemu-common.h
61
target/rx/cpu.h: Don't include qemu-common.h
62
hw/arm: Don't include qemu-common.h unnecessarily
63
target/arm: Correct calculation of tlb range invalidate length
64
65
Philippe Mathieu-Daudé (2):
66
hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c
67
hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector
68
69
Richard Henderson (10):
70
target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn
71
target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn
72
target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn
73
target/arm: Split arm_pre_translate_insn
74
target/arm: Advance pc for arch single-step exception
75
target/arm: Split compute_fsr_fsc out of arm_deliver_fault
76
target/arm: Take an exception if PC is misaligned
77
target/arm: Assert thumb pc is aligned
78
target/arm: Suppress bp for exceptions with more priority
79
tests/tcg: Add arm and aarch64 pc alignment tests
80
81
docs/system/arm/aspeed.rst | 26 ++++++++++++----
82
include/hw/i386/microvm.h | 1 -
83
include/hw/i386/x86.h | 1 -
84
target/arm/helper.h | 1 +
85
target/arm/syndrome.h | 5 +++
86
target/hexagon/cpu.h | 1 -
87
target/rx/cpu.h | 1 -
88
hw/arm/boot.c | 1 -
89
hw/arm/digic_boards.c | 1 -
90
hw/arm/highbank.c | 1 -
91
hw/arm/npcm7xx_boards.c | 1 -
92
hw/arm/sbsa-ref.c | 1 -
93
hw/arm/stm32f405_soc.c | 1 -
94
hw/arm/vexpress.c | 1 -
95
hw/arm/virt-acpi-build.c | 7 +++++
96
hw/arm/virt.c | 21 ++++++-------
97
hw/char/stm32f2xx_usart.c | 3 +-
98
hw/intc/arm_gicv3.c | 2 +-
99
hw/intc/arm_gicv3_cpuif.c | 10 +-----
100
hw/intc/arm_gicv3_cpuif_common.c | 22 +++++++++++++
101
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++--------
102
hw/net/npcm7xx_emc.c | 18 +++++------
103
hw/virtio/virtio-iommu-pci.c | 12 ++------
104
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++------------
105
linux-user/hexagon/cpu_loop.c | 1 +
106
target/arm/debug_helper.c | 23 ++++++++++++++
107
target/arm/gdbstub.c | 9 ++++--
108
target/arm/helper.c | 6 ++--
109
target/arm/machine.c | 10 ++++++
110
target/arm/tlb_helper.c | 63 ++++++++++++++++++++++++++++----------
111
target/arm/translate-a64.c | 23 ++++++++++++--
112
target/arm/translate.c | 58 ++++++++++++++++++++++++++---------
113
target/i386/tcg/translate.c | 12 ++------
114
tests/qtest/bios-tables-test.c | 38 +++++++++++++++++++++++
115
tests/tcg/aarch64/pcalign-a64.c | 37 ++++++++++++++++++++++
116
tests/tcg/arm/pcalign-a32.c | 46 ++++++++++++++++++++++++++++
117
hw/arm/Kconfig | 1 +
118
hw/intc/Kconfig | 5 +++
119
hw/intc/meson.build | 11 ++++---
120
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
121
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
122
tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
123
tests/tcg/aarch64/Makefile.target | 4 +--
124
tests/tcg/arm/Makefile.target | 4 +++
125
44 files changed, 429 insertions(+), 145 deletions(-)
126
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
127
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
128
create mode 100644 tests/tcg/arm/pcalign-a32.c
129
create mode 100644 tests/data/acpi/q35/DSDT.viot
130
create mode 100644 tests/data/acpi/q35/VIOT.viot
131
create mode 100644 tests/data/acpi/virt/VIOT
132
diff view generated by jsdifflib
New patch
1
From: Alex Bennée <alex.bennee@linaro.org>
1
2
3
While trying to debug a GIC ITS failure I saw some guest errors that
4
had poor formatting as well as leaving me confused as to what failed.
5
As most of the checks aren't possible without a valid dte split that
6
check apart and then check the other conditions in steps. This avoids
7
us relying on undefined data.
8
9
I still get a failure with the current kvm-unit-tests but at least I
10
know (partially) why now:
11
12
Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588
13
PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI
14
ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0
15
INT dev_id=2 event_id=20
16
process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0)
17
PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap
18
SUMMARY: 6 tests, 1 unexpected failures
19
20
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org
23
Cc: Shashi Mallela <shashi.mallela@linaro.org>
24
Cc: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
27
hw/intc/arm_gicv3_its.c | 39 +++++++++++++++++++++++++++------------
28
1 file changed, 27 insertions(+), 12 deletions(-)
29
30
diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/hw/intc/arm_gicv3_its.c
33
+++ b/hw/intc/arm_gicv3_its.c
34
@@ -XXX,XX +XXX,XX @@ static bool process_its_cmd(GICv3ITSState *s, uint64_t value, uint32_t offset,
35
if (res != MEMTX_OK) {
36
return result;
37
}
38
+ } else {
39
+ qemu_log_mask(LOG_GUEST_ERROR,
40
+ "%s: invalid command attributes: "
41
+ "invalid dte: %"PRIx64" for %d (MEM_TX: %d)\n",
42
+ __func__, dte, devid, res);
43
+ return result;
44
}
45
46
- if ((devid > s->dt.maxids.max_devids) || !dte_valid || !ite_valid ||
47
- !cte_valid || (eventid > max_eventid)) {
48
+
49
+ /*
50
+ * In this implementation, in case of guest errors we ignore the
51
+ * command and move onto the next command in the queue.
52
+ */
53
+ if (devid > s->dt.maxids.max_devids) {
54
qemu_log_mask(LOG_GUEST_ERROR,
55
- "%s: invalid command attributes "
56
- "devid %d or eventid %d or invalid dte %d or"
57
- "invalid cte %d or invalid ite %d\n",
58
- __func__, devid, eventid, dte_valid, cte_valid,
59
- ite_valid);
60
- /*
61
- * in this implementation, in case of error
62
- * we ignore this command and move onto the next
63
- * command in the queue
64
- */
65
+ "%s: invalid command attributes: devid %d>%d",
66
+ __func__, devid, s->dt.maxids.max_devids);
67
+
68
+ } else if (!dte_valid || !ite_valid || !cte_valid) {
69
+ qemu_log_mask(LOG_GUEST_ERROR,
70
+ "%s: invalid command attributes: "
71
+ "dte: %s, ite: %s, cte: %s\n",
72
+ __func__,
73
+ dte_valid ? "valid" : "invalid",
74
+ ite_valid ? "valid" : "invalid",
75
+ cte_valid ? "valid" : "invalid");
76
+ } else if (eventid > max_eventid) {
77
+ qemu_log_mask(LOG_GUEST_ERROR,
78
+ "%s: invalid command attributes: eventid %d > %d\n",
79
+ __func__, eventid, max_eventid);
80
} else {
81
/*
82
* Current implementation only supports rdbase == procnum
83
--
84
2.25.1
85
86
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be
4
removed in v7.0.
5
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
7
Reviewed-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20211117065752.330632-2-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/aspeed.rst | 7 ++++++-
12
1 file changed, 6 insertions(+), 1 deletion(-)
13
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@ AST2400 SoC based machines :
19
20
- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
21
- ``quanta-q71l-bmc`` OpenBMC Quanta BMC
22
+- ``supermicrox11-bmc`` Supermicro X11 BMC
23
24
AST2500 SoC based machines :
25
26
@@ -XXX,XX +XXX,XX @@ AST2500 SoC based machines :
27
- ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
28
- ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
29
- ``sonorapass-bmc`` OCP SonoraPass BMC
30
-- ``swift-bmc`` OpenPOWER Swift BMC POWER9
31
+- ``swift-bmc`` OpenPOWER Swift BMC POWER9 (to be removed in v7.0)
32
+- ``fp5280g2-bmc`` Inspur FP5280G2 BMC
33
+- ``g220a-bmc`` Bytedance G220A BMC
34
35
AST2600 SoC based machines :
36
37
- ``ast2600-evb`` Aspeed AST2600 Evaluation board (Cortex-A7)
38
- ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC
39
+- ``rainier-bmc`` IBM Rainier POWER10 BMC
40
+- ``fuji-bmc`` Facebook Fuji BMC
41
42
Supported devices
43
-----------------
44
--
45
2.25.1
46
47
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
This is the latest URL for the OpenBMC CI. The old URL still works, but
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
redirects.
5
Message-id: 20180115182436.2066-2-f4bug@amsat.org
5
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20211117065752.330632-3-joel@jms.id.au
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/sd/sdhci-internal.h | 4 ----
11
docs/system/arm/aspeed.rst | 2 +-
9
include/hw/sd/sdhci.h | 7 ++++++-
12
1 file changed, 1 insertion(+), 1 deletion(-)
10
hw/sd/sdhci.c | 1 +
11
3 files changed, 7 insertions(+), 5 deletions(-)
12
13
13
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sdhci-internal.h
16
--- a/docs/system/arm/aspeed.rst
16
+++ b/hw/sd/sdhci-internal.h
17
+++ b/docs/system/arm/aspeed.rst
17
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ The Aspeed machines can be started using the ``-kernel`` option to
18
#ifndef SDHCI_INTERNAL_H
19
load a Linux kernel or from a firmware. Images can be downloaded from
19
#define SDHCI_INTERNAL_H
20
the OpenBMC jenkins :
20
21
21
-#include "hw/sd/sdhci.h"
22
- https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder
22
-
23
+ https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
23
/* R/W SDMA System Address register 0x0 */
24
24
#define SDHC_SYSAD 0x00
25
or directly from the OpenBMC GitHub release repository :
25
26
@@ -XXX,XX +XXX,XX @@ enum {
27
sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */
28
};
29
30
-extern const VMStateDescription sdhci_vmstate;
31
-
32
#endif
33
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/include/hw/sd/sdhci.h
36
+++ b/include/hw/sd/sdhci.h
37
@@ -XXX,XX +XXX,XX @@
38
#define SDHCI_H
39
40
#include "qemu-common.h"
41
-#include "hw/block/block.h"
42
#include "hw/pci/pci.h"
43
#include "hw/sysbus.h"
44
#include "hw/sd/sd.h"
45
46
/* SD/MMC host controller state */
47
typedef struct SDHCIState {
48
+ /*< private >*/
49
union {
50
PCIDevice pcidev;
51
SysBusDevice busdev;
52
};
53
+
54
+ /*< public >*/
55
SDBus sdbus;
56
MemoryRegion iomem;
57
58
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
59
qemu_irq ro_cb;
60
qemu_irq irq;
61
62
+ /* Registers cleared on reset */
63
uint32_t sdmasysad; /* SDMA System Address register */
64
uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
65
uint16_t blkcnt; /* Blocks count for current transfer */
66
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
67
uint16_t acmd12errsts; /* Auto CMD12 error status register */
68
uint64_t admasysaddr; /* ADMA System Address Register */
69
70
+ /* Read-only registers */
71
uint32_t capareg; /* Capabilities Register */
72
uint32_t maxcurr; /* Maximum Current Capabilities Register */
73
+
74
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
75
uint32_t buf_maxsz;
76
uint16_t data_count; /* current element in FIFO buffer */
77
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/hw/sd/sdhci.c
80
+++ b/hw/sd/sdhci.c
81
@@ -XXX,XX +XXX,XX @@
82
#include "sysemu/dma.h"
83
#include "qemu/timer.h"
84
#include "qemu/bitops.h"
85
+#include "hw/sd/sdhci.h"
86
#include "sdhci-internal.h"
87
#include "qemu/log.h"
88
26
89
--
27
--
90
2.7.4
28
2.25.1
91
29
92
30
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
A common use case for the ASPEED machine is to boot a Linux kernel.
4
Provide a full example command line.
5
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Message-id: 20211117065752.330632-4-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
docs/system/arm/aspeed.rst | 15 ++++++++++++---
12
1 file changed, 12 insertions(+), 3 deletions(-)
13
14
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
15
index XXXXXXX..XXXXXXX 100644
16
--- a/docs/system/arm/aspeed.rst
17
+++ b/docs/system/arm/aspeed.rst
18
@@ -XXX,XX +XXX,XX @@ Missing devices
19
Boot options
20
------------
21
22
-The Aspeed machines can be started using the ``-kernel`` option to
23
-load a Linux kernel or from a firmware. Images can be downloaded from
24
-the OpenBMC jenkins :
25
+The Aspeed machines can be started using the ``-kernel`` and ``-dtb`` options
26
+to load a Linux kernel or from a firmware. Images can be downloaded from the
27
+OpenBMC jenkins :
28
29
https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/
30
31
@@ -XXX,XX +XXX,XX @@ or directly from the OpenBMC GitHub release repository :
32
33
https://github.com/openbmc/openbmc/releases
34
35
+To boot a kernel directly from a Linux build tree:
36
+
37
+.. code-block:: bash
38
+
39
+ $ qemu-system-arm -M ast2600-evb -nographic \
40
+ -kernel arch/arm/boot/zImage \
41
+ -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \
42
+ -initrd rootfs.cpio
43
+
44
The image should be attached as an MTD drive. Run :
45
46
.. code-block:: bash
47
--
48
2.25.1
49
50
diff view generated by jsdifflib
New patch
1
From: Joel Stanley <joel@jms.id.au>
1
2
3
Move it to the supported list.
4
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
Message-id: 20211117065752.330632-5-joel@jms.id.au
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
docs/system/arm/aspeed.rst | 2 +-
10
1 file changed, 1 insertion(+), 1 deletion(-)
11
12
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
13
index XXXXXXX..XXXXXXX 100644
14
--- a/docs/system/arm/aspeed.rst
15
+++ b/docs/system/arm/aspeed.rst
16
@@ -XXX,XX +XXX,XX @@ Supported devices
17
* Front LEDs (PCA9552 on I2C bus)
18
* LPC Peripheral Controller (a subset of subdevices are supported)
19
* Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA
20
+ * ADC
21
22
23
Missing devices
24
---------------
25
26
* Coprocessor support
27
- * ADC (out of tree implementation)
28
* PWM and Fan Controller
29
* Slave GPIO Controller
30
* Super I/O Controller
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
1
From: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
1
2
3
Fix issue where the data register may be overwritten by next character
4
reception before being read and returned.
5
6
Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/char/stm32f2xx_usart.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/char/stm32f2xx_usart.c
18
+++ b/hw/char/stm32f2xx_usart.c
19
@@ -XXX,XX +XXX,XX @@ static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
20
return retvalue;
21
case USART_DR:
22
DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
23
+ retvalue = s->usart_dr & 0x3FF;
24
s->usart_sr &= ~USART_SR_RXNE;
25
qemu_chr_fe_accept_input(&s->chr);
26
qemu_set_irq(s->irq, 0);
27
- return s->usart_dr & 0x3FF;
28
+ return retvalue;
29
case USART_BRR:
30
return s->usart_brr;
31
case USART_CR1:
32
--
33
2.25.1
34
35
diff view generated by jsdifflib
New patch
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
2
3
gicv3_set_gicv3state() is used by arm_gicv3_common.c in
4
arm_gicv3_common_realize(). Since we want to restrict
5
arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state()
6
to a new file. Add this file to the meson 'specific'
7
source set, since it needs access to "cpu.h".
8
9
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20211115223619.2599282-2-philmd@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/intc/arm_gicv3_cpuif.c | 10 +---------
15
hw/intc/arm_gicv3_cpuif_common.c | 22 ++++++++++++++++++++++
16
hw/intc/meson.build | 1 +
17
3 files changed, 24 insertions(+), 9 deletions(-)
18
create mode 100644 hw/intc/arm_gicv3_cpuif_common.c
19
20
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/arm_gicv3_cpuif.c
23
+++ b/hw/intc/arm_gicv3_cpuif.c
24
@@ -XXX,XX +XXX,XX @@
25
/*
26
- * ARM Generic Interrupt Controller v3
27
+ * ARM Generic Interrupt Controller v3 (emulation)
28
*
29
* Copyright (c) 2016 Linaro Limited
30
* Written by Peter Maydell
31
@@ -XXX,XX +XXX,XX @@
32
#include "hw/irq.h"
33
#include "cpu.h"
34
35
-void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
36
-{
37
- ARMCPU *arm_cpu = ARM_CPU(cpu);
38
- CPUARMState *env = &arm_cpu->env;
39
-
40
- env->gicv3state = (void *)s;
41
-};
42
-
43
static GICv3CPUState *icc_cs_from_env(CPUARMState *env)
44
{
45
return env->gicv3state;
46
diff --git a/hw/intc/arm_gicv3_cpuif_common.c b/hw/intc/arm_gicv3_cpuif_common.c
47
new file mode 100644
48
index XXXXXXX..XXXXXXX
49
--- /dev/null
50
+++ b/hw/intc/arm_gicv3_cpuif_common.c
51
@@ -XXX,XX +XXX,XX @@
52
+/* SPDX-License-Identifier: GPL-2.0-or-later */
53
+/*
54
+ * ARM Generic Interrupt Controller v3
55
+ *
56
+ * Copyright (c) 2016 Linaro Limited
57
+ * Written by Peter Maydell
58
+ *
59
+ * This code is licensed under the GPL, version 2 or (at your option)
60
+ * any later version.
61
+ */
62
+
63
+#include "qemu/osdep.h"
64
+#include "gicv3_internal.h"
65
+#include "cpu.h"
66
+
67
+void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s)
68
+{
69
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
70
+ CPUARMState *env = &arm_cpu->env;
71
+
72
+ env->gicv3state = (void *)s;
73
+};
74
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
75
index XXXXXXX..XXXXXXX 100644
76
--- a/hw/intc/meson.build
77
+++ b/hw/intc/meson.build
78
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
79
80
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
81
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
82
+specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
83
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
84
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
85
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
86
--
87
2.25.1
88
89
diff view generated by jsdifflib
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
2
2
3
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
3
The TYPE_ARM_GICV3 device is an emulated one. When using
4
KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device
5
(which uses in-kernel support).
6
7
When using --with-devices-FOO, it is possible to build a
8
binary with a specific set of devices. When this binary is
9
restricted to KVM accelerator, the TYPE_ARM_GICV3 device is
10
irrelevant, and it is desirable to remove it from the binary.
11
12
Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector
13
which select the files required to have the TYPE_ARM_GICV3
14
device, but also allowing to de-select this device.
15
16
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20211115223619.2599282-3-philmd@redhat.com
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20180115182436.2066-13-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
20
---
10
hw/sd/sdhci.c | 3 +++
21
hw/intc/arm_gicv3.c | 2 +-
11
1 file changed, 3 insertions(+)
22
hw/intc/Kconfig | 5 +++++
23
hw/intc/meson.build | 10 ++++++----
24
3 files changed, 12 insertions(+), 5 deletions(-)
12
25
13
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
26
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
14
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sdhci.c
28
--- a/hw/intc/arm_gicv3.c
16
+++ b/hw/sd/sdhci.c
29
+++ b/hw/intc/arm_gicv3.c
17
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
30
@@ -XXX,XX +XXX,XX @@
18
}
31
/*
19
sdhci_update_irq(s);
32
- * ARM Generic Interrupt Controller v3
20
break;
33
+ * ARM Generic Interrupt Controller v3 (emulation)
21
+ case SDHC_ACMD12ERRSTS:
34
*
22
+ MASKED_WRITE(s->acmd12errsts, mask, value);
35
* Copyright (c) 2015 Huawei.
23
+ break;
36
* Copyright (c) 2016 Linaro Limited
24
37
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
25
case SDHC_CAPAB:
38
index XXXXXXX..XXXXXXX 100644
26
case SDHC_CAPAB + 4:
39
--- a/hw/intc/Kconfig
40
+++ b/hw/intc/Kconfig
41
@@ -XXX,XX +XXX,XX @@ config APIC
42
select MSI_NONBROKEN
43
select I8259
44
45
+config ARM_GIC_TCG
46
+ bool
47
+ default y
48
+ depends on ARM_GIC && TCG
49
+
50
config ARM_GIC_KVM
51
bool
52
default y
53
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/intc/meson.build
56
+++ b/hw/intc/meson.build
57
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
58
'arm_gic.c',
59
'arm_gic_common.c',
60
'arm_gicv2m.c',
61
- 'arm_gicv3.c',
62
'arm_gicv3_common.c',
63
- 'arm_gicv3_dist.c',
64
'arm_gicv3_its_common.c',
65
- 'arm_gicv3_redist.c',
66
+))
67
+softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
68
+ 'arm_gicv3.c',
69
+ 'arm_gicv3_dist.c',
70
'arm_gicv3_its.c',
71
+ 'arm_gicv3_redist.c',
72
))
73
softmmu_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_pic.c'))
74
softmmu_ss.add(when: 'CONFIG_HEATHROW_PIC', if_true: files('heathrow_pic.c'))
75
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
76
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
77
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
78
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
79
-specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif.c'))
80
+specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c'))
81
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
82
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
83
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
27
--
84
--
28
2.7.4
85
2.25.1
29
86
30
87
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180110063337.21538-3-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
6
---
8
target/arm/translate-a64.c | 5 +++++
7
target/arm/translate-a64.c | 7 ++++---
9
1 file changed, 5 insertions(+)
8
1 file changed, 4 insertions(+), 3 deletions(-)
10
9
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
12
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
13
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t vfp_expand_imm(int size, uint8_t imm8)
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
16
(extract32(imm8, 0, 6) << 3);
15
{
17
imm <<= 16;
16
DisasContext *s = container_of(dcbase, DisasContext, base);
18
break;
17
CPUARMState *env = cpu->env_ptr;
19
+ case MO_16:
18
+ uint64_t pc = s->base.pc_next;
20
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
19
uint32_t insn;
21
+ (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
20
22
+ (extract32(imm8, 0, 6) << 6);
21
if (s->ss_active && !s->pstate_ss) {
23
+ break;
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
24
default:
23
return;
25
g_assert_not_reached();
26
}
24
}
25
26
- s->pc_curr = s->base.pc_next;
27
- insn = arm_ldl_code(env, &s->base, s->base.pc_next, s->sctlr_b);
28
+ s->pc_curr = pc;
29
+ insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
30
s->insn = insn;
31
- s->base.pc_next += 4;
32
+ s->base.pc_next = pc + 4;
33
34
s->fp_access_checked = false;
35
s->sve_access_checked = false;
27
--
36
--
28
2.7.4
37
2.25.1
29
38
30
39
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add a 'dma' property allowing machine creation to provide the address-space
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
SDHCI DMA operates on.
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
6
[based on a patch from Alistair Francis <alistair.francis@xilinx.com>
7
from qemu/xilinx tag xilinx-v2016.1]
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20180115182436.2066-15-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
6
---
12
include/hw/sd/sdhci.h | 1 +
7
target/arm/translate.c | 9 +++++----
13
hw/sd/sdhci.c | 18 +++++++++++++++++-
8
1 file changed, 5 insertions(+), 4 deletions(-)
14
2 files changed, 18 insertions(+), 1 deletion(-)
15
9
16
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
10
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/sd/sdhci.h
12
--- a/target/arm/translate.c
19
+++ b/include/hw/sd/sdhci.h
13
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
14
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
21
SDBus sdbus;
22
MemoryRegion iomem;
23
AddressSpace *dma_as;
24
+ MemoryRegion *dma_mr;
25
26
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
27
QEMUTimer *transfer_timer;
28
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/sd/sdhci.c
31
+++ b/hw/sd/sdhci.c
32
@@ -XXX,XX +XXX,XX @@ static Property sdhci_sysbus_properties[] = {
33
DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
34
DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
35
false),
36
+ DEFINE_PROP_LINK("dma", SDHCIState,
37
+ dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
38
DEFINE_PROP_END_OF_LIST(),
39
};
40
41
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_init(Object *obj)
42
static void sdhci_sysbus_finalize(Object *obj)
43
{
15
{
44
SDHCIState *s = SYSBUS_SDHCI(obj);
16
DisasContext *dc = container_of(dcbase, DisasContext, base);
45
+
17
CPUARMState *env = cpu->env_ptr;
46
+ if (s->dma_mr) {
18
+ uint32_t pc = dc->base.pc_next;
47
+ object_unparent(OBJECT(s->dma_mr));
19
unsigned int insn;
48
+ }
20
49
+
21
if (arm_pre_translate_insn(dc)) {
50
sdhci_uninitfn(s);
22
- dc->base.pc_next += 4;
51
}
23
+ dc->base.pc_next = pc + 4;
52
53
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
54
return;
24
return;
55
}
25
}
56
26
57
- s->dma_as = &address_space_memory;
27
- dc->pc_curr = dc->base.pc_next;
58
+ if (s->dma_mr) {
28
- insn = arm_ldl_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
59
+ address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");
29
+ dc->pc_curr = pc;
60
+ } else {
30
+ insn = arm_ldl_code(env, &dc->base, pc, dc->sctlr_b);
61
+ /* use system_memory() if property "dma" not set */
31
dc->insn = insn;
62
+ s->dma_as = &address_space_memory;
32
- dc->base.pc_next += 4;
63
+ }
33
+ dc->base.pc_next = pc + 4;
64
34
disas_arm_insn(dc, insn);
65
sysbus_init_irq(sbd, &s->irq);
35
66
sysbus_init_mmio(sbd, &s->iomem);
36
arm_post_translate_insn(dc);
67
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp)
68
SDHCIState *s = SYSBUS_SDHCI(dev);
69
70
sdhci_common_unrealize(s, &error_abort);
71
+
72
+ if (s->dma_mr) {
73
+ address_space_destroy(s->dma_as);
74
+ }
75
}
76
77
static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
78
--
37
--
79
2.7.4
38
2.25.1
80
39
81
40
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
zero-initialize ADMADescr 'dscr' in sdhci_do_adma() to avoid:
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
hw/sd/sdhci.c: In function ‘sdhci_do_adma’:
6
hw/sd/sdhci.c:714:29: error: ‘dscr.addr’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
7
trace_sdhci_adma("link", s->admasysaddr);
8
^
9
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
12
Message-id: 20180115182436.2066-9-f4bug@amsat.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
6
---
15
hw/sd/sdhci.c | 89 ++++++++++++++++++------------------------------------
7
target/arm/translate.c | 16 ++++++++--------
16
hw/sd/trace-events | 14 +++++++++
8
1 file changed, 8 insertions(+), 8 deletions(-)
17
2 files changed, 44 insertions(+), 59 deletions(-)
18
9
19
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
10
diff --git a/target/arm/translate.c b/target/arm/translate.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/sd/sdhci.c
12
--- a/target/arm/translate.c
22
+++ b/hw/sd/sdhci.c
13
+++ b/target/arm/translate.c
23
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
24
#include "sdhci-internal.h"
25
#include "qapi/error.h"
26
#include "qemu/log.h"
27
-
28
-/* host controller debug messages */
29
-#ifndef SDHC_DEBUG
30
-#define SDHC_DEBUG 0
31
-#endif
32
-
33
-#define DPRINT_L1(fmt, args...) \
34
- do { \
35
- if (SDHC_DEBUG) { \
36
- fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
37
- } \
38
- } while (0)
39
-#define DPRINT_L2(fmt, args...) \
40
- do { \
41
- if (SDHC_DEBUG > 1) { \
42
- fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
43
- } \
44
- } while (0)
45
-#define ERRPRINT(fmt, args...) \
46
- do { \
47
- if (SDHC_DEBUG) { \
48
- fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \
49
- } \
50
- } while (0)
51
+#include "trace.h"
52
53
#define TYPE_SDHCI_BUS "sdhci-bus"
54
#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
55
@@ -XXX,XX +XXX,XX @@ static void sdhci_raise_insertion_irq(void *opaque)
56
static void sdhci_set_inserted(DeviceState *dev, bool level)
57
{
15
{
58
SDHCIState *s = (SDHCIState *)dev;
16
DisasContext *dc = container_of(dcbase, DisasContext, base);
59
- DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject");
17
CPUARMState *env = cpu->env_ptr;
60
18
+ uint32_t pc = dc->base.pc_next;
61
+ trace_sdhci_set_inserted(level ? "insert" : "eject");
19
uint32_t insn;
62
if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
20
bool is_16bit;
63
/* Give target some time to notice card ejection */
21
64
timer_mod(s->insert_timer,
22
if (arm_pre_translate_insn(dc)) {
65
@@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s)
23
- dc->base.pc_next += 2;
66
s->acmd12errsts = 0;
24
+ dc->base.pc_next = pc + 2;
67
request.cmd = s->cmdreg >> 8;
68
request.arg = s->argument;
69
- DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg);
70
+
71
+ trace_sdhci_send_command(request.cmd, request.arg);
72
rlen = sdbus_do_command(&s->sdbus, &request, response);
73
74
if (s->cmdreg & SDHC_CMD_RESPONSE) {
75
@@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s)
76
s->rspreg[0] = (response[0] << 24) | (response[1] << 16) |
77
(response[2] << 8) | response[3];
78
s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
79
- DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]);
80
+ trace_sdhci_response4(s->rspreg[0]);
81
} else if (rlen == 16) {
82
s->rspreg[0] = (response[11] << 24) | (response[12] << 16) |
83
(response[13] << 8) | response[14];
84
@@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s)
85
(response[5] << 8) | response[6];
86
s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
87
response[2];
88
- DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
89
- "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
90
- s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]);
91
+ trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
92
+ s->rspreg[1], s->rspreg[0]);
93
} else {
94
- ERRPRINT("Timeout waiting for command response\n");
95
+ trace_sdhci_error("timeout waiting for command response");
96
if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
97
s->errintsts |= SDHC_EIS_CMDTIMEOUT;
98
s->norintsts |= SDHC_NIS_ERR;
99
@@ -XXX,XX +XXX,XX @@ static void sdhci_end_transfer(SDHCIState *s)
100
101
request.cmd = 0x0C;
102
request.arg = 0;
103
- DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg);
104
+ trace_sdhci_end_transfer(request.cmd, request.arg);
105
sdbus_do_command(&s->sdbus, &request, response);
106
/* Auto CMD12 response goes to the upper Response register */
107
s->rspreg[3] = (response[0] << 24) | (response[1] << 16) |
108
@@ -XXX,XX +XXX,XX @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
109
110
/* first check that a valid data exists in host controller input buffer */
111
if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
112
- ERRPRINT("Trying to read from empty buffer\n");
113
+ trace_sdhci_error("read from empty buffer");
114
return 0;
115
}
116
117
@@ -XXX,XX +XXX,XX @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
118
s->data_count++;
119
/* check if we've read all valid data (blksize bytes) from buffer */
120
if ((s->data_count) >= (s->blksize & 0x0fff)) {
121
- DPRINT_L2("All %u bytes of data have been read from input buffer\n",
122
- s->data_count);
123
+ trace_sdhci_read_dataport(s->data_count);
124
s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
125
s->data_count = 0; /* next buff read must start at position [0] */
126
127
@@ -XXX,XX +XXX,XX @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
128
129
/* Check that there is free space left in a buffer */
130
if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
131
- ERRPRINT("Can't write to data buffer: buffer full\n");
132
+ trace_sdhci_error("Can't write to data buffer: buffer full");
133
return;
25
return;
134
}
26
}
135
27
136
@@ -XXX,XX +XXX,XX @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
28
- dc->pc_curr = dc->base.pc_next;
137
s->data_count++;
29
- insn = arm_lduw_code(env, &dc->base, dc->base.pc_next, dc->sctlr_b);
138
value >>= 8;
30
+ dc->pc_curr = pc;
139
if (s->data_count >= (s->blksize & 0x0fff)) {
31
+ insn = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
140
- DPRINT_L2("write buffer filled with %u bytes of data\n",
32
is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
141
- s->data_count);
33
- dc->base.pc_next += 2;
142
+ trace_sdhci_write_dataport(s->data_count);
34
+ pc += 2;
143
s->data_count = 0;
35
if (!is_16bit) {
144
s->prnsts &= ~SDHC_SPACE_AVAILABLE;
36
- uint32_t insn2 = arm_lduw_code(env, &dc->base, dc->base.pc_next,
145
if (s->prnsts & SDHC_DOING_WRITE) {
37
- dc->sctlr_b);
146
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
38
-
147
{
39
+ uint32_t insn2 = arm_lduw_code(env, &dc->base, pc, dc->sctlr_b);
148
unsigned int n, begin, length;
40
insn = insn << 16 | insn2;
149
const uint16_t block_size = s->blksize & 0x0fff;
41
- dc->base.pc_next += 2;
150
- ADMADescr dscr;
42
+ pc += 2;
151
+ ADMADescr dscr = {};
152
int i;
153
154
for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
155
s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
156
157
get_adma_description(s, &dscr);
158
- DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n",
159
- dscr.addr, dscr.length, dscr.attr);
160
+ trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
161
162
if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
163
/* Indicate that error occurred in ST_FDS state */
164
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
165
break;
166
case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
167
s->admasysaddr = dscr.addr;
168
- DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n",
169
- s->admasysaddr);
170
+ trace_sdhci_adma("link", s->admasysaddr);
171
break;
172
default:
173
s->admasysaddr += dscr.incr;
174
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
175
}
176
177
if (dscr.attr & SDHC_ADMA_ATTR_INT) {
178
- DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n",
179
- s->admasysaddr);
180
+ trace_sdhci_adma("interrupt", s->admasysaddr);
181
if (s->norintstsen & SDHC_NISEN_DMA) {
182
s->norintsts |= SDHC_NIS_DMA;
183
}
184
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
185
/* ADMA transfer terminates if blkcnt == 0 or by END attribute */
186
if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
187
(s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
188
- DPRINT_L2("ADMA transfer completed\n");
189
+ trace_sdhci_adma_transfer_completed();
190
if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
191
(s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
192
s->blkcnt != 0)) {
193
- ERRPRINT("SD/MMC host ADMA length mismatch\n");
194
+ trace_sdhci_error("SD/MMC host ADMA length mismatch");
195
s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
196
SDHC_ADMAERR_STATE_ST_TFR;
197
if (s->errintstsen & SDHC_EISEN_ADMAERR) {
198
- ERRPRINT("Set ADMA error flag\n");
199
+ trace_sdhci_error("Set ADMA error flag");
200
s->errintsts |= SDHC_EIS_ADMAERR;
201
s->norintsts |= SDHC_NIS_ERR;
202
}
203
@@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque)
204
break;
205
case SDHC_CTRL_ADMA1_32:
206
if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
207
- ERRPRINT("ADMA1 not supported\n");
208
+ trace_sdhci_error("ADMA1 not supported");
209
break;
210
}
211
212
@@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque)
213
break;
214
case SDHC_CTRL_ADMA2_32:
215
if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
216
- ERRPRINT("ADMA2 not supported\n");
217
+ trace_sdhci_error("ADMA2 not supported");
218
break;
219
}
220
221
@@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque)
222
case SDHC_CTRL_ADMA2_64:
223
if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
224
!(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
225
- ERRPRINT("64 bit ADMA not supported\n");
226
+ trace_sdhci_error("64 bit ADMA not supported");
227
break;
228
}
229
230
sdhci_do_adma(s);
231
break;
232
default:
233
- ERRPRINT("Unsupported DMA type\n");
234
+ trace_sdhci_error("Unsupported DMA type");
235
break;
236
}
237
} else {
238
@@ -XXX,XX +XXX,XX @@ static inline bool
239
sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
240
{
241
if ((s->data_count & 0x3) != byte_num) {
242
- ERRPRINT("Non-sequential access to Buffer Data Port register"
243
- "is prohibited\n");
244
+ trace_sdhci_error("Non-sequential access to Buffer Data Port register"
245
+ "is prohibited\n");
246
return false;
247
}
43
}
248
return true;
44
+ dc->base.pc_next = pc;
249
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
45
dc->insn = insn;
250
case SDHC_BDATA:
46
251
if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
47
if (dc->pstate_il) {
252
ret = sdhci_read_dataport(s, size);
253
- DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset,
254
- ret, ret);
255
+ trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
256
return ret;
257
}
258
break;
259
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
260
261
ret >>= (offset & 0x3) * 8;
262
ret &= (1ULL << (size * 8)) - 1;
263
- DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret);
264
+ trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
265
return ret;
266
}
267
268
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
269
"not implemented\n", size, offset, value >> shift);
270
break;
271
}
272
- DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
273
- size, (int)offset, value >> shift, value >> shift);
274
+ trace_sdhci_access("wr", size << 3, offset, "<-",
275
+ value >> shift, value >> shift);
276
}
277
278
static const MemoryRegionOps sdhci_mmio_ops = {
279
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
280
index XXXXXXX..XXXXXXX 100644
281
--- a/hw/sd/trace-events
282
+++ b/hw/sd/trace-events
283
@@ -XXX,XX +XXX,XX @@
284
# See docs/devel/tracing.txt for syntax documentation.
285
286
+# hw/sd/sdhci.c
287
+sdhci_set_inserted(const char *level) "card state changed: %s"
288
+sdhci_send_command(uint8_t cmd, uint32_t arg) "CMD%02u ARG[0x%08x]"
289
+sdhci_error(const char *msg) "%s"
290
+sdhci_response4(uint32_t r0) "RSPREG[31..0]=0x%08x"
291
+sdhci_response16(uint32_t r3, uint32_t r2, uint32_t r1, uint32_t r0) "RSPREG[127..96]=0x%08x, RSPREG[95..64]=0x%08x, RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x"
292
+sdhci_end_transfer(uint8_t cmd, uint32_t arg) "Automatically issue CMD%02u 0x%08x"
293
+sdhci_adma(const char *desc, uint32_t sysad) "%s: admasysaddr=0x%" PRIx32
294
+sdhci_adma_loop(uint64_t addr, uint16_t length, uint8_t attr) "addr=0x%08" PRIx64 ", len=%d, attr=0x%x"
295
+sdhci_adma_transfer_completed(void) ""
296
+sdhci_access(const char *access, unsigned int size, uint64_t offset, const char *dir, uint64_t val, uint64_t val2) "%s%u: addr[0x%04" PRIx64 "] %s 0x%08" PRIx64 " (%" PRIu64 ")"
297
+sdhci_read_dataport(uint16_t data_count) "all %u bytes of data have been read from input buffer"
298
+sdhci_write_dataport(uint16_t data_count) "write buffer filled with %u bytes of data"
299
+
300
# hw/sd/milkymist-memcard.c
301
milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
302
milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
303
--
48
--
304
2.7.4
49
2.25.1
305
50
306
51
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
While SysBus devices can use the get_system_memory() address space,
3
Create arm_check_ss_active and arm_check_kernelpage.
4
PCI devices should use the bus master address space for DMA.
5
4
6
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
5
Reverse the order of the tests. While it doesn't matter in practice,
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
because only user-only has a kernel page and user-only never sets
7
ss_active, ss_active has priority over execution exceptions and it
8
is best to keep them in the proper order.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20180115182436.2066-14-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
include/hw/sd/sdhci.h | 1 +
14
target/arm/translate.c | 10 +++++++---
13
hw/sd/sdhci.c | 29 +++++++++++++++--------------
15
1 file changed, 7 insertions(+), 3 deletions(-)
14
2 files changed, 16 insertions(+), 14 deletions(-)
15
16
16
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/sd/sdhci.h
19
--- a/target/arm/translate.c
19
+++ b/include/hw/sd/sdhci.h
20
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
21
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
21
/*< public >*/
22
dc->insn_start = tcg_last_op();
22
SDBus sdbus;
23
MemoryRegion iomem;
24
+ AddressSpace *dma_as;
25
26
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
27
QEMUTimer *transfer_timer;
28
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/sd/sdhci.c
31
+++ b/hw/sd/sdhci.c
32
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
33
s->blkcnt--;
34
}
35
}
36
- dma_memory_write(&address_space_memory, s->sdmasysad,
37
+ dma_memory_write(s->dma_as, s->sdmasysad,
38
&s->fifo_buffer[begin], s->data_count - begin);
39
s->sdmasysad += s->data_count - begin;
40
if (s->data_count == block_size) {
41
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
42
s->data_count = block_size;
43
boundary_count -= block_size - begin;
44
}
45
- dma_memory_read(&address_space_memory, s->sdmasysad,
46
+ dma_memory_read(s->dma_as, s->sdmasysad,
47
&s->fifo_buffer[begin], s->data_count - begin);
48
s->sdmasysad += s->data_count - begin;
49
if (s->data_count == block_size) {
50
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s)
51
for (n = 0; n < datacnt; n++) {
52
s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
53
}
54
- dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer,
55
- datacnt);
56
+ dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
57
} else {
58
- dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer,
59
- datacnt);
60
+ dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
61
for (n = 0; n < datacnt; n++) {
62
sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
63
}
64
@@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
65
hwaddr entry_addr = (hwaddr)s->admasysaddr;
66
switch (SDHC_DMA_TYPE(s->hostctl)) {
67
case SDHC_CTRL_ADMA2_32:
68
- dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2,
69
+ dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2,
70
sizeof(adma2));
71
adma2 = le64_to_cpu(adma2);
72
/* The spec does not specify endianness of descriptor table.
73
@@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
74
dscr->incr = 8;
75
break;
76
case SDHC_CTRL_ADMA1_32:
77
- dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1,
78
+ dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1,
79
sizeof(adma1));
80
adma1 = le32_to_cpu(adma1);
81
dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
82
@@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
83
}
84
break;
85
case SDHC_CTRL_ADMA2_64:
86
- dma_memory_read(&address_space_memory, entry_addr,
87
+ dma_memory_read(s->dma_as, entry_addr,
88
(uint8_t *)(&dscr->attr), 1);
89
- dma_memory_read(&address_space_memory, entry_addr + 2,
90
+ dma_memory_read(s->dma_as, entry_addr + 2,
91
(uint8_t *)(&dscr->length), 2);
92
dscr->length = le16_to_cpu(dscr->length);
93
- dma_memory_read(&address_space_memory, entry_addr + 4,
94
+ dma_memory_read(s->dma_as, entry_addr + 4,
95
(uint8_t *)(&dscr->addr), 8);
96
dscr->attr = le64_to_cpu(dscr->attr);
97
dscr->attr &= 0xfffffff8;
98
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
99
s->data_count = block_size;
100
length -= block_size - begin;
101
}
102
- dma_memory_write(&address_space_memory, dscr.addr,
103
+ dma_memory_write(s->dma_as, dscr.addr,
104
&s->fifo_buffer[begin],
105
s->data_count - begin);
106
dscr.addr += s->data_count - begin;
107
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
108
s->data_count = block_size;
109
length -= block_size - begin;
110
}
111
- dma_memory_read(&address_space_memory, dscr.addr,
112
+ dma_memory_read(s->dma_as, dscr.addr,
113
&s->fifo_buffer[begin],
114
s->data_count - begin);
115
dscr.addr += s->data_count - begin;
116
@@ -XXX,XX +XXX,XX @@ static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
117
dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
118
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
119
s->irq = pci_allocate_irq(dev);
120
- pci_register_bar(dev, 0, 0, &s->iomem);
121
+ s->dma_as = pci_get_address_space(dev);
122
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem);
123
}
23
}
124
24
125
static void sdhci_pci_exit(PCIDevice *dev)
25
-static bool arm_pre_translate_insn(DisasContext *dc)
126
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
26
+static bool arm_check_kernelpage(DisasContext *dc)
27
{
28
#ifdef CONFIG_USER_ONLY
29
/* Intercept jump to the magic kernel page. */
30
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
31
return true;
32
}
33
#endif
34
+ return false;
35
+}
36
37
+static bool arm_check_ss_active(DisasContext *dc)
38
+{
39
if (dc->ss_active && !dc->pstate_ss) {
40
/* Singlestep state is Active-pending.
41
* If we're in this state at the start of a TB then either
42
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
43
uint32_t pc = dc->base.pc_next;
44
unsigned int insn;
45
46
- if (arm_pre_translate_insn(dc)) {
47
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
48
dc->base.pc_next = pc + 4;
127
return;
49
return;
128
}
50
}
129
51
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
130
+ s->dma_as = &address_space_memory;
52
uint32_t insn;
131
+
53
bool is_16bit;
132
sysbus_init_irq(sbd, &s->irq);
54
133
sysbus_init_mmio(sbd, &s->iomem);
55
- if (arm_pre_translate_insn(dc)) {
134
}
56
+ if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
57
dc->base.pc_next = pc + 2;
58
return;
59
}
135
--
60
--
136
2.7.4
61
2.25.1
137
62
138
63
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3
The size of the code covered by a TranslationBlock cannot be 0;
4
this is checked via assert in tb_gen_code.
2
5
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180110063337.21538-2-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
9
---
8
target/arm/translate-a64.c | 44 ++++++++++++++++++++++++++++----------------
10
target/arm/translate-a64.c | 1 +
9
1 file changed, 28 insertions(+), 16 deletions(-)
11
1 file changed, 1 insertion(+)
10
12
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
15
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
17
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
16
}
18
assert(s->base.num_insns == 1);
17
}
19
gen_swstep_exception(s, 0, 0);
18
20
s->base.is_jmp = DISAS_NORETURN;
19
+/* The imm8 encodes the sign bit, enough bits to represent an exponent in
21
+ s->base.pc_next = pc + 4;
20
+ * the range 01....1xx to 10....0xx, and the most significant 4 bits of
21
+ * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
22
+ */
23
+static uint64_t vfp_expand_imm(int size, uint8_t imm8)
24
+{
25
+ uint64_t imm;
26
+
27
+ switch (size) {
28
+ case MO_64:
29
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
30
+ (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
31
+ extract32(imm8, 0, 6);
32
+ imm <<= 48;
33
+ break;
34
+ case MO_32:
35
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
36
+ (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
37
+ (extract32(imm8, 0, 6) << 3);
38
+ imm <<= 16;
39
+ break;
40
+ default:
41
+ g_assert_not_reached();
42
+ }
43
+ return imm;
44
+}
45
+
46
/* Floating point immediate
47
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
48
* +---+---+---+-----------+------+---+------------+-------+------+------+
49
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
50
return;
22
return;
51
}
23
}
52
24
53
- /* The imm8 encodes the sign bit, enough bits to represent
54
- * an exponent in the range 01....1xx to 10....0xx,
55
- * and the most significant 4 bits of the mantissa; see
56
- * VFPExpandImm() in the v8 ARM ARM.
57
- */
58
- if (is_double) {
59
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
60
- (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
61
- extract32(imm8, 0, 6);
62
- imm <<= 48;
63
- } else {
64
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
65
- (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
66
- (extract32(imm8, 0, 6) << 3);
67
- imm <<= 16;
68
- }
69
+ imm = vfp_expand_imm(MO_32 + is_double, imm8);
70
71
tcg_res = tcg_const_i64(imm);
72
write_fp_dreg(s, rd, tcg_res);
73
--
25
--
74
2.7.4
26
2.25.1
75
27
76
28
diff view generated by jsdifflib
1
Since pl181 is still using the legacy SD card API, the SD
1
From: Richard Henderson <richard.henderson@linaro.org>
2
card created by sd_init() is not plugged into any bus. This
3
means that the controller has to reset it manually.
4
2
5
Failing to do this mostly didn't affect the guest since the
3
We will reuse this section of arm_deliver_fault for
6
guest typically does a programmed SD card reset as part of
4
raising pc alignment faults.
7
its SD controller driver initialization, but meant that
8
migration failed because it's only in sd_reset() that we
9
set up the wpgrps_size field.
10
5
11
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Fixes: https://bugs.launchpad.net/qemu/+bug/1739378
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 1515506513-31961-2-git-send-email-peter.maydell@linaro.org
17
---
9
---
18
hw/sd/pl181.c | 4 ++++
10
target/arm/tlb_helper.c | 45 +++++++++++++++++++++++++----------------
19
1 file changed, 4 insertions(+)
11
1 file changed, 28 insertions(+), 17 deletions(-)
20
12
21
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
13
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
22
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/sd/pl181.c
15
--- a/target/arm/tlb_helper.c
24
+++ b/hw/sd/pl181.c
16
+++ b/target/arm/tlb_helper.c
25
@@ -XXX,XX +XXX,XX @@ static void pl181_reset(DeviceState *d)
17
@@ -XXX,XX +XXX,XX @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
26
18
return syn;
27
/* We can assume our GPIO outputs have been wired up now */
28
sd_set_cb(s->card, s->cardstatus[0], s->cardstatus[1]);
29
+ /* Since we're still using the legacy SD API the card is not plugged
30
+ * into any bus, and we must reset it manually.
31
+ */
32
+ device_reset(DEVICE(s->card));
33
}
19
}
34
20
35
static void pl181_init(Object *obj)
21
-static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
22
- MMUAccessType access_type,
23
- int mmu_idx, ARMMMUFaultInfo *fi)
24
+static uint32_t compute_fsr_fsc(CPUARMState *env, ARMMMUFaultInfo *fi,
25
+ int target_el, int mmu_idx, uint32_t *ret_fsc)
26
{
27
- CPUARMState *env = &cpu->env;
28
- int target_el;
29
- bool same_el;
30
- uint32_t syn, exc, fsr, fsc;
31
ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
32
-
33
- target_el = exception_target_el(env);
34
- if (fi->stage2) {
35
- target_el = 2;
36
- env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
37
- if (arm_is_secure_below_el3(env) && fi->s1ns) {
38
- env->cp15.hpfar_el2 |= HPFAR_NS;
39
- }
40
- }
41
- same_el = (arm_current_el(env) == target_el);
42
+ uint32_t fsr, fsc;
43
44
if (target_el == 2 || arm_el_is_aa64(env, target_el) ||
45
arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
46
@@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
47
fsc = 0x3f;
48
}
49
50
+ *ret_fsc = fsc;
51
+ return fsr;
52
+}
53
+
54
+static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr,
55
+ MMUAccessType access_type,
56
+ int mmu_idx, ARMMMUFaultInfo *fi)
57
+{
58
+ CPUARMState *env = &cpu->env;
59
+ int target_el;
60
+ bool same_el;
61
+ uint32_t syn, exc, fsr, fsc;
62
+
63
+ target_el = exception_target_el(env);
64
+ if (fi->stage2) {
65
+ target_el = 2;
66
+ env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4;
67
+ if (arm_is_secure_below_el3(env) && fi->s1ns) {
68
+ env->cp15.hpfar_el2 |= HPFAR_NS;
69
+ }
70
+ }
71
+ same_el = (arm_current_el(env) == target_el);
72
+
73
+ fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc);
74
+
75
if (access_type == MMU_INST_FETCH) {
76
syn = syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc);
77
exc = EXCP_PREFETCH_ABORT;
36
--
78
--
37
2.7.4
79
2.25.1
38
80
39
81
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
For A64, any input to an indirect branch can cause this.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180115182436.2066-6-f4bug@amsat.org
5
For A32, many indirect branch paths force the branch to be aligned,
6
but BXWritePC does not. This includes the BX instruction but also
7
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
8
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
9
exception or force align the PC.
10
11
We choose to raise an exception because we have the infrastructure,
12
it makes the generated code for gen_bx simpler, and it has the
13
possibility of catching more guest bugs.
14
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
18
---
8
hw/sd/sdhci.c | 30 +++++++++++++++++++++---------
19
target/arm/helper.h | 1 +
9
1 file changed, 21 insertions(+), 9 deletions(-)
20
target/arm/syndrome.h | 5 ++++
10
21
linux-user/aarch64/cpu_loop.c | 46 ++++++++++++++++++++---------------
11
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
22
target/arm/tlb_helper.c | 18 ++++++++++++++
12
index XXXXXXX..XXXXXXX 100644
23
target/arm/translate-a64.c | 15 ++++++++++++
13
--- a/hw/sd/sdhci.c
24
target/arm/translate.c | 22 ++++++++++++++++-
14
+++ b/hw/sd/sdhci.c
25
6 files changed, 87 insertions(+), 20 deletions(-)
15
@@ -XXX,XX +XXX,XX @@ static void sdhci_uninitfn(SDHCIState *s)
26
16
s->fifo_buffer = NULL;
27
diff --git a/target/arm/helper.h b/target/arm/helper.h
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.h
30
+++ b/target/arm/helper.h
31
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE,
32
DEF_HELPER_2(exception_internal, void, env, i32)
33
DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)
34
DEF_HELPER_2(exception_bkpt_insn, void, env, i32)
35
+DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl)
36
DEF_HELPER_1(setend, void, env)
37
DEF_HELPER_2(wfi, void, env, i32)
38
DEF_HELPER_1(wfe, void, env)
39
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/syndrome.h
42
+++ b/target/arm/syndrome.h
43
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_illegalstate(void)
44
return (EC_ILLEGALSTATE << ARM_EL_EC_SHIFT) | ARM_EL_IL;
17
}
45
}
18
46
19
+static void sdhci_common_realize(SDHCIState *s, Error **errp)
47
+static inline uint32_t syn_pcalignment(void)
20
+{
48
+{
21
+ s->buf_maxsz = sdhci_get_fifolen(s);
49
+ return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL;
22
+ s->fifo_buffer = g_malloc0(s->buf_maxsz);
23
+
24
+ memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
25
+ SDHC_REGISTERS_MAP_SIZE);
26
+}
50
+}
27
+
51
+
28
static bool sdhci_pending_insert_vmstate_needed(void *opaque)
52
#endif /* TARGET_ARM_SYNDROME_H */
29
{
53
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
30
SDHCIState *s = opaque;
54
index XXXXXXX..XXXXXXX 100644
31
@@ -XXX,XX +XXX,XX @@ static Property sdhci_pci_properties[] = {
55
--- a/linux-user/aarch64/cpu_loop.c
32
static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
56
+++ b/linux-user/aarch64/cpu_loop.c
33
{
57
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
34
SDHCIState *s = PCI_SDHCI(dev);
58
break;
35
+
59
case EXCP_PREFETCH_ABORT:
36
+ sdhci_initfn(s);
60
case EXCP_DATA_ABORT:
37
+ sdhci_common_realize(s, errp);
61
- /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
38
+ if (errp && *errp) {
62
ec = syn_get_ec(env->exception.syndrome);
63
- assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
64
-
65
- /* Both EC have the same format for FSC, or close enough. */
66
- fsc = extract32(env->exception.syndrome, 0, 6);
67
- switch (fsc) {
68
- case 0x04 ... 0x07: /* Translation fault, level {0-3} */
69
- si_signo = TARGET_SIGSEGV;
70
- si_code = TARGET_SEGV_MAPERR;
71
+ switch (ec) {
72
+ case EC_DATAABORT:
73
+ case EC_INSNABORT:
74
+ /* Both EC have the same format for FSC, or close enough. */
75
+ fsc = extract32(env->exception.syndrome, 0, 6);
76
+ switch (fsc) {
77
+ case 0x04 ... 0x07: /* Translation fault, level {0-3} */
78
+ si_signo = TARGET_SIGSEGV;
79
+ si_code = TARGET_SEGV_MAPERR;
80
+ break;
81
+ case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
82
+ case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
83
+ si_signo = TARGET_SIGSEGV;
84
+ si_code = TARGET_SEGV_ACCERR;
85
+ break;
86
+ case 0x11: /* Synchronous Tag Check Fault */
87
+ si_signo = TARGET_SIGSEGV;
88
+ si_code = TARGET_SEGV_MTESERR;
89
+ break;
90
+ case 0x21: /* Alignment fault */
91
+ si_signo = TARGET_SIGBUS;
92
+ si_code = TARGET_BUS_ADRALN;
93
+ break;
94
+ default:
95
+ g_assert_not_reached();
96
+ }
97
break;
98
- case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
99
- case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
100
- si_signo = TARGET_SIGSEGV;
101
- si_code = TARGET_SEGV_ACCERR;
102
- break;
103
- case 0x11: /* Synchronous Tag Check Fault */
104
- si_signo = TARGET_SIGSEGV;
105
- si_code = TARGET_SEGV_MTESERR;
106
- break;
107
- case 0x21: /* Alignment fault */
108
+ case EC_PCALIGNMENT:
109
si_signo = TARGET_SIGBUS;
110
si_code = TARGET_BUS_ADRALN;
111
break;
112
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/target/arm/tlb_helper.c
115
+++ b/target/arm/tlb_helper.c
116
@@ -XXX,XX +XXX,XX @@
117
#include "cpu.h"
118
#include "internals.h"
119
#include "exec/exec-all.h"
120
+#include "exec/helper-proto.h"
121
122
static inline uint32_t merge_syn_data_abort(uint32_t template_syn,
123
unsigned int target_el,
124
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
125
arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi);
126
}
127
128
+void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc)
129
+{
130
+ ARMMMUFaultInfo fi = { .type = ARMFault_Alignment };
131
+ int target_el = exception_target_el(env);
132
+ int mmu_idx = cpu_mmu_index(env, true);
133
+ uint32_t fsc;
134
+
135
+ env->exception.vaddress = pc;
136
+
137
+ /*
138
+ * Note that the fsc is not applicable to this exception,
139
+ * since any syndrome is pcalignment not insn_abort.
140
+ */
141
+ env->exception.fsr = compute_fsr_fsc(env, &fi, target_el, mmu_idx, &fsc);
142
+ raise_exception(env, EXCP_PREFETCH_ABORT, syn_pcalignment(), target_el);
143
+}
144
+
145
#if !defined(CONFIG_USER_ONLY)
146
147
/*
148
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
149
index XXXXXXX..XXXXXXX 100644
150
--- a/target/arm/translate-a64.c
151
+++ b/target/arm/translate-a64.c
152
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
153
uint64_t pc = s->base.pc_next;
154
uint32_t insn;
155
156
+ /* Singlestep exceptions have the highest priority. */
157
if (s->ss_active && !s->pstate_ss) {
158
/* Singlestep state is Active-pending.
159
* If we're in this state at the start of a TB then either
160
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
161
return;
162
}
163
164
+ if (pc & 3) {
165
+ /*
166
+ * PC alignment fault. This has priority over the instruction abort
167
+ * that we would receive from a translation fault via arm_ldl_code.
168
+ * This should only be possible after an indirect branch, at the
169
+ * start of the TB.
170
+ */
171
+ assert(s->base.num_insns == 1);
172
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
173
+ s->base.is_jmp = DISAS_NORETURN;
174
+ s->base.pc_next = QEMU_ALIGN_UP(pc, 4);
39
+ return;
175
+ return;
40
+ }
176
+ }
41
+
177
+
42
dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
178
s->pc_curr = pc;
43
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
179
insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);
44
- sdhci_initfn(s);
180
s->insn = insn;
45
- s->buf_maxsz = sdhci_get_fifolen(s);
181
diff --git a/target/arm/translate.c b/target/arm/translate.c
46
- s->fifo_buffer = g_malloc0(s->buf_maxsz);
182
index XXXXXXX..XXXXXXX 100644
47
s->irq = pci_allocate_irq(dev);
183
--- a/target/arm/translate.c
48
- memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
184
+++ b/target/arm/translate.c
49
- SDHC_REGISTERS_MAP_SIZE);
185
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
50
pci_register_bar(dev, 0, 0, &s->iomem);
186
uint32_t pc = dc->base.pc_next;
51
}
187
unsigned int insn;
52
188
53
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
189
- if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
54
SDHCIState *s = SYSBUS_SDHCI(dev);
190
+ /* Singlestep exceptions have the highest priority. */
55
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
191
+ if (arm_check_ss_active(dc)) {
56
192
+ dc->base.pc_next = pc + 4;
57
- s->buf_maxsz = sdhci_get_fifolen(s);
58
- s->fifo_buffer = g_malloc0(s->buf_maxsz);
59
+ sdhci_common_realize(s, errp);
60
+ if (errp && *errp) {
61
+ return;
193
+ return;
62
+ }
194
+ }
63
+
195
+
64
sysbus_init_irq(sbd, &s->irq);
196
+ if (pc & 3) {
65
- memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
197
+ /*
66
- SDHC_REGISTERS_MAP_SIZE);
198
+ * PC alignment fault. This has priority over the instruction abort
67
sysbus_init_mmio(sbd, &s->iomem);
199
+ * that we would receive from a translation fault via arm_ldl_code
68
}
200
+ * (or the execution of the kernelpage entrypoint). This should only
69
201
+ * be possible after an indirect branch, at the start of the TB.
202
+ */
203
+ assert(dc->base.num_insns == 1);
204
+ gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc));
205
+ dc->base.is_jmp = DISAS_NORETURN;
206
+ dc->base.pc_next = QEMU_ALIGN_UP(pc, 4);
207
+ return;
208
+ }
209
+
210
+ if (arm_check_kernelpage(dc)) {
211
dc->base.pc_next = pc + 4;
212
return;
213
}
70
--
214
--
71
2.7.4
215
2.25.1
72
216
73
217
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
running qtests:
3
Misaligned thumb PC is architecturally impossible.
4
Assert is better than proceeding, in case we've missed
5
something somewhere.
4
6
5
$ make check-qtest-arm
7
Expand a comment about aligning the pc in gdbstub.
6
GTESTER check-qtest-arm
8
Fail an incoming migrate if a thumb pc is misaligned.
7
SDHC rd_4b @0x44 not implemented
8
SDHC wr_4b @0x40 <- 0x89abcdef not implemented
9
SDHC wr_4b @0x44 <- 0x01234567 not implemented
10
9
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20180115182436.2066-12-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
13
---
16
include/hw/sd/sdhci.h | 4 ++--
14
target/arm/gdbstub.c | 9 +++++++--
17
hw/sd/sdhci.c | 23 +++++++++++++++++++----
15
target/arm/machine.c | 10 ++++++++++
18
2 files changed, 21 insertions(+), 6 deletions(-)
16
target/arm/translate.c | 3 +++
17
3 files changed, 20 insertions(+), 2 deletions(-)
19
18
20
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
19
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/sd/sdhci.h
21
--- a/target/arm/gdbstub.c
23
+++ b/include/hw/sd/sdhci.h
22
+++ b/target/arm/gdbstub.c
24
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
23
@@ -XXX,XX +XXX,XX @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
25
uint64_t admasysaddr; /* ADMA System Address Register */
24
26
25
tmp = ldl_p(mem_buf);
27
/* Read-only registers */
26
28
- uint32_t capareg; /* Capabilities Register */
27
- /* Mask out low bit of PC to workaround gdb bugs. This will probably
29
- uint32_t maxcurr; /* Maximum Current Capabilities Register */
28
- cause problems if we ever implement the Jazelle DBX extensions. */
30
+ uint64_t capareg; /* Capabilities Register */
29
+ /*
31
+ uint64_t maxcurr; /* Maximum Current Capabilities Register */
30
+ * Mask out low bits of PC to workaround gdb bugs.
32
31
+ * This avoids an assert in thumb_tr_translate_insn, because it is
33
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
32
+ * architecturally impossible to misalign the pc.
34
uint32_t buf_maxsz;
33
+ * This will probably cause problems if we ever implement the
35
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
34
+ * Jazelle DBX extensions.
35
+ */
36
if (n == 15) {
37
tmp &= ~1;
38
}
39
diff --git a/target/arm/machine.c b/target/arm/machine.c
36
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/sd/sdhci.c
41
--- a/target/arm/machine.c
38
+++ b/hw/sd/sdhci.c
42
+++ b/target/arm/machine.c
39
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
43
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
40
ret = s->acmd12errsts;
44
return -1;
41
break;
42
case SDHC_CAPAB:
43
- ret = s->capareg;
44
+ ret = (uint32_t)s->capareg;
45
+ break;
46
+ case SDHC_CAPAB + 4:
47
+ ret = (uint32_t)(s->capareg >> 32);
48
break;
49
case SDHC_MAXCURR:
50
- ret = s->maxcurr;
51
+ ret = (uint32_t)s->maxcurr;
52
+ break;
53
+ case SDHC_MAXCURR + 4:
54
+ ret = (uint32_t)(s->maxcurr >> 32);
55
break;
56
case SDHC_ADMAERR:
57
ret = s->admaerr;
58
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
59
}
45
}
60
sdhci_update_irq(s);
46
}
61
break;
62
+
47
+
63
+ case SDHC_CAPAB:
48
+ /*
64
+ case SDHC_CAPAB + 4:
49
+ * Misaligned thumb pc is architecturally impossible.
65
+ case SDHC_MAXCURR:
50
+ * We have an assert in thumb_tr_translate_insn to verify this.
66
+ case SDHC_MAXCURR + 4:
51
+ * Fail an incoming migrate to avoid this assert.
67
+ qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
52
+ */
68
+ " <- 0x%08x read-only\n", size, offset, value >> shift);
53
+ if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) {
69
+ break;
54
+ return -1;
55
+ }
70
+
56
+
71
default:
57
if (!kvm_enabled()) {
72
qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
58
pmu_op_finish(&cpu->env);
73
"not implemented\n", size, offset, value >> shift);
59
}
74
@@ -XXX,XX +XXX,XX @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
60
diff --git a/target/arm/translate.c b/target/arm/translate.c
75
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
61
index XXXXXXX..XXXXXXX 100644
76
/* Capabilities registers provide information on supported features
62
--- a/target/arm/translate.c
77
* of this specific host controller implementation */ \
63
+++ b/target/arm/translate.c
78
- DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
64
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
79
- DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)
65
uint32_t insn;
80
+ DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
66
bool is_16bit;
81
+ DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
67
82
68
+ /* Misaligned thumb PC is architecturally impossible. */
83
static void sdhci_initfn(SDHCIState *s)
69
+ assert((dc->base.pc_next & 1) == 0);
84
{
70
+
71
if (arm_check_ss_active(dc) || arm_check_kernelpage(dc)) {
72
dc->base.pc_next = pc + 2;
73
return;
85
--
74
--
86
2.7.4
75
2.25.1
87
76
88
77
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Both single-step and pc alignment faults have priority over
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
breakpoint exceptions.
5
Message-id: 20180115182436.2066-8-f4bug@amsat.org
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
9
---
8
hw/sd/sdhci.c | 7 ++++---
10
target/arm/debug_helper.c | 23 +++++++++++++++++++++++
9
1 file changed, 4 insertions(+), 3 deletions(-)
11
1 file changed, 23 insertions(+)
10
12
11
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
13
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sdhci.c
15
--- a/target/arm/debug_helper.c
14
+++ b/hw/sd/sdhci.c
16
+++ b/target/arm/debug_helper.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
17
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs)
16
ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
18
{
17
break;
19
ARMCPU *cpu = ARM_CPU(cs);
18
default:
20
CPUARMState *env = &cpu->env;
19
- ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset);
21
+ target_ulong pc;
20
+ qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
22
int n;
21
+ "not implemented\n", size, offset);
23
22
break;
24
/*
25
@@ -XXX,XX +XXX,XX @@ bool arm_debug_check_breakpoint(CPUState *cs)
26
return false;
23
}
27
}
24
28
25
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
29
+ /*
26
sdhci_update_irq(s);
30
+ * Single-step exceptions have priority over breakpoint exceptions.
27
break;
31
+ * If single-step state is active-pending, suppress the bp.
28
default:
32
+ */
29
- ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
33
+ if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) {
30
- size, (int)offset, value >> shift, value >> shift);
34
+ return false;
31
+ qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
35
+ }
32
+ "not implemented\n", size, offset, value >> shift);
36
+
33
break;
37
+ /*
34
}
38
+ * PC alignment faults have priority over breakpoint exceptions.
35
DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
39
+ */
40
+ pc = is_a64(env) ? env->pc : env->regs[15];
41
+ if ((is_a64(env) || !env->thumb) && (pc & 3) != 0) {
42
+ return false;
43
+ }
44
+
45
+ /*
46
+ * Instruction aborts have priority over breakpoint exceptions.
47
+ * TODO: We would need to look up the page for PC and verify that
48
+ * it is present and executable.
49
+ */
50
+
51
for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
52
if (bp_wp_matches(cpu, n, false)) {
53
return true;
36
--
54
--
37
2.7.4
55
2.25.1
38
56
39
57
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Now both inherited classes appear as DEVICE_CATEGORY_STORAGE.
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20180115182436.2066-5-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
6
---
10
hw/sd/sdhci.c | 18 +++++++++++++-----
7
tests/tcg/aarch64/pcalign-a64.c | 37 +++++++++++++++++++++++++
11
1 file changed, 13 insertions(+), 5 deletions(-)
8
tests/tcg/arm/pcalign-a32.c | 46 +++++++++++++++++++++++++++++++
9
tests/tcg/aarch64/Makefile.target | 4 +--
10
tests/tcg/arm/Makefile.target | 4 +++
11
4 files changed, 89 insertions(+), 2 deletions(-)
12
create mode 100644 tests/tcg/aarch64/pcalign-a64.c
13
create mode 100644 tests/tcg/arm/pcalign-a32.c
12
14
13
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
15
diff --git a/tests/tcg/aarch64/pcalign-a64.c b/tests/tcg/aarch64/pcalign-a64.c
14
index XXXXXXX..XXXXXXX 100644
16
new file mode 100644
15
--- a/hw/sd/sdhci.c
17
index XXXXXXX..XXXXXXX
16
+++ b/hw/sd/sdhci.c
18
--- /dev/null
17
@@ -XXX,XX +XXX,XX @@ const VMStateDescription sdhci_vmstate = {
19
+++ b/tests/tcg/aarch64/pcalign-a64.c
18
},
20
@@ -XXX,XX +XXX,XX @@
19
};
21
+/* Test PC misalignment exception */
20
22
+
21
+static void sdhci_common_class_init(ObjectClass *klass, void *data)
23
+#include <assert.h>
24
+#include <signal.h>
25
+#include <stdlib.h>
26
+#include <stdio.h>
27
+
28
+static void *expected;
29
+
30
+static void sigbus(int sig, siginfo_t *info, void *vuc)
22
+{
31
+{
23
+ DeviceClass *dc = DEVICE_CLASS(klass);
32
+ assert(info->si_code == BUS_ADRALN);
24
+
33
+ assert(info->si_addr == expected);
25
+ set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
34
+ exit(EXIT_SUCCESS);
26
+ dc->vmsd = &sdhci_vmstate;
27
+ dc->reset = sdhci_poweron_reset;
28
+}
35
+}
29
+
36
+
30
/* --- qdev PCI --- */
37
+int main()
31
38
+{
32
static Property sdhci_pci_properties[] = {
39
+ void *tmp;
33
@@ -XXX,XX +XXX,XX @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
34
k->vendor_id = PCI_VENDOR_ID_REDHAT;
35
k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI;
36
k->class_id = PCI_CLASS_SYSTEM_SDHCI;
37
- set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
38
- dc->vmsd = &sdhci_vmstate;
39
dc->props = sdhci_pci_properties;
40
- dc->reset = sdhci_poweron_reset;
41
+
40
+
42
+ sdhci_common_class_init(klass, data);
41
+ struct sigaction sa = {
43
}
42
+ .sa_sigaction = sigbus,
44
43
+ .sa_flags = SA_SIGINFO
45
static const TypeInfo sdhci_pci_info = {
44
+ };
46
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
47
{
48
DeviceClass *dc = DEVICE_CLASS(klass);
49
50
- dc->vmsd = &sdhci_vmstate;
51
dc->props = sdhci_sysbus_properties;
52
dc->realize = sdhci_sysbus_realize;
53
- dc->reset = sdhci_poweron_reset;
54
+
45
+
55
+ sdhci_common_class_init(klass, data);
46
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
56
}
47
+ perror("sigaction");
57
48
+ return EXIT_FAILURE;
58
static const TypeInfo sdhci_sysbus_info = {
49
+ }
50
+
51
+ asm volatile("adr %0, 1f + 1\n\t"
52
+ "str %0, %1\n\t"
53
+ "br %0\n"
54
+ "1:"
55
+ : "=&r"(tmp), "=m"(expected));
56
+ abort();
57
+}
58
diff --git a/tests/tcg/arm/pcalign-a32.c b/tests/tcg/arm/pcalign-a32.c
59
new file mode 100644
60
index XXXXXXX..XXXXXXX
61
--- /dev/null
62
+++ b/tests/tcg/arm/pcalign-a32.c
63
@@ -XXX,XX +XXX,XX @@
64
+/* Test PC misalignment exception */
65
+
66
+#ifdef __thumb__
67
+#error "This test must be compiled for ARM"
68
+#endif
69
+
70
+#include <assert.h>
71
+#include <signal.h>
72
+#include <stdlib.h>
73
+#include <stdio.h>
74
+
75
+static void *expected;
76
+
77
+static void sigbus(int sig, siginfo_t *info, void *vuc)
78
+{
79
+ assert(info->si_code == BUS_ADRALN);
80
+ assert(info->si_addr == expected);
81
+ exit(EXIT_SUCCESS);
82
+}
83
+
84
+int main()
85
+{
86
+ void *tmp;
87
+
88
+ struct sigaction sa = {
89
+ .sa_sigaction = sigbus,
90
+ .sa_flags = SA_SIGINFO
91
+ };
92
+
93
+ if (sigaction(SIGBUS, &sa, NULL) < 0) {
94
+ perror("sigaction");
95
+ return EXIT_FAILURE;
96
+ }
97
+
98
+ asm volatile("adr %0, 1f + 2\n\t"
99
+ "str %0, %1\n\t"
100
+ "bx %0\n"
101
+ "1:"
102
+ : "=&r"(tmp), "=m"(expected));
103
+
104
+ /*
105
+ * From v8, it is CONSTRAINED UNPREDICTABLE whether BXWritePC aligns
106
+ * the address or not. If so, we can legitimately fall through.
107
+ */
108
+ return EXIT_SUCCESS;
109
+}
110
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
111
index XXXXXXX..XXXXXXX 100644
112
--- a/tests/tcg/aarch64/Makefile.target
113
+++ b/tests/tcg/aarch64/Makefile.target
114
@@ -XXX,XX +XXX,XX @@ VPATH         += $(ARM_SRC)
115
AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
116
VPATH         += $(AARCH64_SRC)
117
118
-# Float-convert Tests
119
-AARCH64_TESTS=fcvt
120
+# Base architecture tests
121
+AARCH64_TESTS=fcvt pcalign-a64
122
123
fcvt: LDFLAGS+=-lm
124
125
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
126
index XXXXXXX..XXXXXXX 100644
127
--- a/tests/tcg/arm/Makefile.target
128
+++ b/tests/tcg/arm/Makefile.target
129
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
130
    $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
131
    $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
132
133
+# PC alignment test
134
+ARM_TESTS += pcalign-a32
135
+pcalign-a32: CFLAGS+=-marm
136
+
137
ifeq ($(CONFIG_ARM_COMPATIBLE_SEMIHOSTING),y)
138
139
# Semihosting smoke test for linux-user
59
--
140
--
60
2.7.4
141
2.25.1
61
142
62
143
diff view generated by jsdifflib
New patch
1
In the SSE decode function gen_sse(), we combine a byte
2
'b' and a value 'b1' which can be [0..3], and switch on them:
3
b |= (b1 << 8);
4
switch (b) {
5
...
6
default:
7
unknown_op:
8
gen_unknown_opcode(env, s);
9
return;
10
}
1
11
12
In three cases inside this switch, we were then also checking for
13
"if (b1 >= 2) { goto unknown_op; }".
14
However, this can never happen, because the 'case' values in each place
15
are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3)
16
cases to the default already.
17
18
This check was added in commit c045af25a52e9 in 2010; the added code
19
was unnecessary then as well, and was apparently intended only to
20
ensure that we never accidentally ended up indexing off the end
21
of an sse_op_table with only 2 entries as a result of future bugs
22
in the decode logic.
23
24
Change the checks to assert() instead, and make sure they're always
25
immediately before the array access they are protecting.
26
27
Fixes: Coverity CID 1460207
28
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
30
---
31
target/i386/tcg/translate.c | 12 +++---------
32
1 file changed, 3 insertions(+), 9 deletions(-)
33
34
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/i386/tcg/translate.c
37
+++ b/target/i386/tcg/translate.c
38
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
39
case 0x171: /* shift xmm, im */
40
case 0x172:
41
case 0x173:
42
- if (b1 >= 2) {
43
- goto unknown_op;
44
- }
45
val = x86_ldub_code(env, s);
46
if (is_xmm) {
47
tcg_gen_movi_tl(s->T0, val);
48
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
49
offsetof(CPUX86State, mmx_t0.MMX_L(1)));
50
op1_offset = offsetof(CPUX86State,mmx_t0);
51
}
52
+ assert(b1 < 2);
53
sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
54
(((modrm >> 3)) & 7)][b1];
55
if (!sse_fn_epp) {
56
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
57
rm = modrm & 7;
58
reg = ((modrm >> 3) & 7) | REX_R(s);
59
mod = (modrm >> 6) & 3;
60
- if (b1 >= 2) {
61
- goto unknown_op;
62
- }
63
64
+ assert(b1 < 2);
65
sse_fn_epp = sse_op_table6[b].op[b1];
66
if (!sse_fn_epp) {
67
goto unknown_op;
68
@@ -XXX,XX +XXX,XX @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
69
rm = modrm & 7;
70
reg = ((modrm >> 3) & 7) | REX_R(s);
71
mod = (modrm >> 6) & 3;
72
- if (b1 >= 2) {
73
- goto unknown_op;
74
- }
75
76
+ assert(b1 < 2);
77
sse_fn_eppi = sse_op_table7[b].op[b1];
78
if (!sse_fn_eppi) {
79
goto unknown_op;
80
--
81
2.25.1
82
83
diff view generated by jsdifflib
New patch
1
The qemu-common.h header is not supposed to be included from any
2
other header files, only from .c files (as documented in a comment at
3
the start of it).
1
4
5
include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule.
6
In fact, the include is not required at all, so we can just drop it
7
from both files.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org
13
---
14
include/hw/i386/microvm.h | 1 -
15
include/hw/i386/x86.h | 1 -
16
2 files changed, 2 deletions(-)
17
18
diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/i386/microvm.h
21
+++ b/include/hw/i386/microvm.h
22
@@ -XXX,XX +XXX,XX @@
23
#ifndef HW_I386_MICROVM_H
24
#define HW_I386_MICROVM_H
25
26
-#include "qemu-common.h"
27
#include "exec/hwaddr.h"
28
#include "qemu/notify.h"
29
30
diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
31
index XXXXXXX..XXXXXXX 100644
32
--- a/include/hw/i386/x86.h
33
+++ b/include/hw/i386/x86.h
34
@@ -XXX,XX +XXX,XX @@
35
#ifndef HW_I386_X86_H
36
#define HW_I386_X86_H
37
38
-#include "qemu-common.h"
39
#include "exec/hwaddr.h"
40
#include "qemu/notify.h"
41
42
--
43
2.25.1
44
45
diff view generated by jsdifflib
1
The Configurable Fault Status Register for ARMv7M and v8M is
1
The qemu-common.h header is not supposed to be included from any
2
supposed to be byte and halfword accessible, but we were only
2
other header files, only from .c files (as documented in a comment at
3
implementing word accesses. Add support for the other access
3
the start of it).
4
sizes, which are used by the Zephyr RTOS.
4
5
Move the include to linux-user/hexagon/cpu_loop.c, which needs it for
6
the declaration of cpu_exec_step_atomic().
5
7
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reported-by: Andy Gross <andy.gross@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 1512742372-31517-1-git-send-email-peter.maydell@linaro.org
11
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
12
Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
10
---
13
---
11
hw/intc/armv7m_nvic.c | 38 ++++++++++++++++++++++----------------
14
target/hexagon/cpu.h | 1 -
12
1 file changed, 22 insertions(+), 16 deletions(-)
15
linux-user/hexagon/cpu_loop.c | 1 +
16
2 files changed, 1 insertion(+), 1 deletion(-)
13
17
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
20
--- a/target/hexagon/cpu.h
17
+++ b/hw/intc/armv7m_nvic.c
21
+++ b/target/hexagon/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUHexagonState CPUHexagonState;
19
val |= (1 << 8);
23
20
}
24
#include "fpu/softfloat-types.h"
21
return val;
25
22
- case 0xd28: /* Configurable Fault Status. */
26
-#include "qemu-common.h"
23
- /* The BFSR bits [15:8] are shared between security states
27
#include "exec/cpu-defs.h"
24
- * and we store them in the NS copy
28
#include "hex_regs.h"
25
- */
29
#include "mmvec/mmvec.h"
26
- val = cpu->env.v7m.cfsr[attrs.secure];
30
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
27
- val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
31
index XXXXXXX..XXXXXXX 100644
28
- return val;
32
--- a/linux-user/hexagon/cpu_loop.c
29
case 0xd2c: /* Hard Fault Status. */
33
+++ b/linux-user/hexagon/cpu_loop.c
30
return cpu->env.v7m.hfsr;
34
@@ -XXX,XX +XXX,XX @@
31
case 0xd30: /* Debug Fault Status. */
35
*/
32
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
36
33
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
37
#include "qemu/osdep.h"
34
nvic_irq_update(s);
38
+#include "qemu-common.h"
35
break;
39
#include "qemu.h"
36
- case 0xd28: /* Configurable Fault Status. */
40
#include "user-internals.h"
37
- cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */
41
#include "cpu_loop-common.h"
38
- if (attrs.secure) {
39
- /* The BFSR bits [15:8] are shared between security states
40
- * and we store them in the NS copy.
41
- */
42
- cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
43
- }
44
- break;
45
case 0xd2c: /* Hard Fault Status. */
46
cpu->env.v7m.hfsr &= ~value; /* W1C */
47
break;
48
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
49
val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
50
}
51
break;
52
+ case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
53
+ /* The BFSR bits [15:8] are shared between security states
54
+ * and we store them in the NS copy
55
+ */
56
+ val = s->cpu->env.v7m.cfsr[attrs.secure];
57
+ val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
58
+ val = extract32(val, (offset - 0xd28) * 8, size * 8);
59
+ break;
60
case 0xfe0 ... 0xfff: /* ID. */
61
if (offset & 3) {
62
val = 0;
63
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
64
}
65
nvic_irq_update(s);
66
return MEMTX_OK;
67
+ case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
68
+ /* All bits are W1C, so construct 32 bit value with 0s in
69
+ * the parts not written by the access size
70
+ */
71
+ value <<= ((offset - 0xd28) * 8);
72
+
73
+ s->cpu->env.v7m.cfsr[attrs.secure] &= ~value;
74
+ if (attrs.secure) {
75
+ /* The BFSR bits [15:8] are shared between security states
76
+ * and we store them in the NS copy.
77
+ */
78
+ s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
79
+ }
80
+ return MEMTX_OK;
81
}
82
if (size == 4) {
83
nvic_writel(s, offset, value, attrs);
84
--
42
--
85
2.7.4
43
2.25.1
86
44
87
45
diff view generated by jsdifflib
1
Since omap_mmc is still using the legacy SD card API, the SD
1
The qemu-common.h header is not supposed to be included from any
2
card created by sd_init() is not plugged into any bus. This
2
other header files, only from .c files (as documented in a comment at
3
means that the controller has to reset it manually.
3
the start of it).
4
4
5
Failing to do this mostly didn't affect the guest since the
5
Nothing actually relies on target/rx/cpu.h including it, so we can
6
guest typically does a programmed SD card reset as part of
6
just drop the include.
7
its SD controller driver initialization, but would mean that
8
migration fails because it's only in sd_reset() that we
9
set up the wpgrps_size field.
10
7
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
14
Message-id: 1515506513-31961-5-git-send-email-peter.maydell@linaro.org
12
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
13
Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org
15
---
14
---
16
hw/sd/omap_mmc.c | 14 ++++++++++----
15
target/rx/cpu.h | 1 -
17
1 file changed, 10 insertions(+), 4 deletions(-)
16
1 file changed, 1 deletion(-)
18
17
19
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
18
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
20
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/sd/omap_mmc.c
20
--- a/target/rx/cpu.h
22
+++ b/hw/sd/omap_mmc.c
21
+++ b/target/rx/cpu.h
23
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
22
@@ -XXX,XX +XXX,XX @@
24
host->cdet_enable = 0;
23
#define RX_CPU_H
25
qemu_set_irq(host->coverswitch, host->cdet_state);
24
26
host->clkdiv = 0;
25
#include "qemu/bitops.h"
27
+
26
-#include "qemu-common.h"
28
+ /* Since we're still using the legacy SD API the card is not plugged
27
#include "hw/registerfields.h"
29
+ * into any bus, and we must reset it manually. When omap_mmc is
28
#include "cpu-qom.h"
30
+ * QOMified this must move into the QOM reset function.
31
+ */
32
+ device_reset(DEVICE(host->card));
33
}
34
35
static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
36
@@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap_mmc_init(hwaddr base,
37
s->lines = 1;    /* TODO: needs to be settable per-board */
38
s->rev = 1;
39
40
- omap_mmc_reset(s);
41
-
42
memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
43
memory_region_add_subregion(sysmem, base, &s->iomem);
44
45
@@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap_mmc_init(hwaddr base,
46
exit(1);
47
}
48
49
+ omap_mmc_reset(s);
50
+
51
return s;
52
}
53
54
@@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
55
s->lines = 4;
56
s->rev = 2;
57
58
- omap_mmc_reset(s);
59
-
60
memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
61
omap_l4_region_size(ta, 0));
62
omap_l4_attach(ta, 0, &s->iomem);
63
@@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
64
s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
65
sd_set_cb(s->card, NULL, s->cdet);
66
67
+ omap_mmc_reset(s);
68
+
69
return s;
70
}
71
29
72
--
30
--
73
2.7.4
31
2.25.1
74
32
75
33
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
A lot of C files in hw/arm include qemu-common.h when they don't
2
need anything from it. Drop the include lines.
2
3
3
Add common/sysbus/pci/sdbus comments to have clearer code blocks separation.
4
omap1.c, pxa2xx.c and strongarm.c retain the include because they
5
use it for the prototype of qemu_get_timedate().
4
6
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20180115182436.2066-4-f4bug@amsat.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
11
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
12
Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org
9
---
13
---
10
include/hw/sd/sdhci.h | 4 +++-
14
hw/arm/boot.c | 1 -
11
hw/sd/sdhci.c | 25 +++++++++++++++++--------
15
hw/arm/digic_boards.c | 1 -
12
2 files changed, 20 insertions(+), 9 deletions(-)
16
hw/arm/highbank.c | 1 -
17
hw/arm/npcm7xx_boards.c | 1 -
18
hw/arm/sbsa-ref.c | 1 -
19
hw/arm/stm32f405_soc.c | 1 -
20
hw/arm/vexpress.c | 1 -
21
hw/arm/virt.c | 1 -
22
8 files changed, 8 deletions(-)
13
23
14
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
24
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
15
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/sd/sdhci.h
26
--- a/hw/arm/boot.c
17
+++ b/include/hw/sd/sdhci.h
27
+++ b/hw/arm/boot.c
18
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
19
uint32_t buf_maxsz;
20
uint16_t data_count; /* current element in FIFO buffer */
21
uint8_t stopped_state;/* Current SDHC state */
22
- bool pending_insert_quirk;/* Quirk for Raspberry Pi card insert int */
23
bool pending_insert_state;
24
/* Buffer Data Port Register - virtual access point to R and W buffers */
25
/* Software Reset Register - always reads as 0 */
26
/* Force Event Auto CMD12 Error Interrupt Reg - write only */
27
/* Force Event Error Interrupt Register- write only */
28
/* RO Host Controller Version Register always reads as 0x2401 */
29
+
30
+ /* Configurable properties */
31
+ bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
32
} SDHCIState;
33
34
#define TYPE_PCI_SDHCI "sdhci-pci"
35
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/sd/sdhci.c
38
+++ b/hw/sd/sdhci.c
39
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
40
*/
29
*/
41
30
42
#include "qemu/osdep.h"
31
#include "qemu/osdep.h"
43
+#include "qapi/error.h"
32
-#include "qemu-common.h"
44
#include "hw/hw.h"
33
#include "qemu/datadir.h"
45
#include "sysemu/block-backend.h"
34
#include "qemu/error-report.h"
35
#include "qapi/error.h"
36
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/digic_boards.c
39
+++ b/hw/arm/digic_boards.c
40
@@ -XXX,XX +XXX,XX @@
41
42
#include "qemu/osdep.h"
43
#include "qapi/error.h"
44
-#include "qemu-common.h"
45
#include "qemu/datadir.h"
46
#include "hw/boards.h"
47
#include "qemu/error-report.h"
48
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/highbank.c
51
+++ b/hw/arm/highbank.c
52
@@ -XXX,XX +XXX,XX @@
53
*/
54
55
#include "qemu/osdep.h"
56
-#include "qemu-common.h"
57
#include "qemu/datadir.h"
58
#include "qapi/error.h"
59
#include "hw/sysbus.h"
60
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/hw/arm/npcm7xx_boards.c
63
+++ b/hw/arm/npcm7xx_boards.c
64
@@ -XXX,XX +XXX,XX @@
65
#include "hw/qdev-core.h"
66
#include "hw/qdev-properties.h"
67
#include "qapi/error.h"
68
-#include "qemu-common.h"
69
#include "qemu/datadir.h"
70
#include "qemu/units.h"
46
#include "sysemu/blockdev.h"
71
#include "sysemu/blockdev.h"
47
@@ -XXX,XX +XXX,XX @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
72
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
48
}
73
index XXXXXXX..XXXXXXX 100644
49
}
74
--- a/hw/arm/sbsa-ref.c
50
75
+++ b/hw/arm/sbsa-ref.c
51
+/* --- qdev common --- */
76
@@ -XXX,XX +XXX,XX @@
52
+
77
*/
53
+#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
78
54
+ /* Capabilities registers provide information on supported features
79
#include "qemu/osdep.h"
55
+ * of this specific host controller implementation */ \
80
-#include "qemu-common.h"
56
+ DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
81
#include "qemu/datadir.h"
57
+ DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)
82
#include "qapi/error.h"
58
+
83
#include "qemu/error-report.h"
59
static void sdhci_initfn(SDHCIState *s)
84
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
60
{
85
index XXXXXXX..XXXXXXX 100644
61
qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
86
--- a/hw/arm/stm32f405_soc.c
62
@@ -XXX,XX +XXX,XX @@ const VMStateDescription sdhci_vmstate = {
87
+++ b/hw/arm/stm32f405_soc.c
63
},
88
@@ -XXX,XX +XXX,XX @@
64
};
89
65
90
#include "qemu/osdep.h"
66
-/* Capabilities registers provide information on supported features of this
91
#include "qapi/error.h"
67
- * specific host controller implementation */
92
-#include "qemu-common.h"
68
+/* --- qdev PCI --- */
93
#include "exec/address-spaces.h"
69
+
94
#include "sysemu/sysemu.h"
70
static Property sdhci_pci_properties[] = {
95
#include "hw/arm/stm32f405_soc.h"
71
- DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
96
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
72
- SDHC_CAPAB_REG_DEFAULT),
97
index XXXXXXX..XXXXXXX 100644
73
- DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
98
--- a/hw/arm/vexpress.c
74
+ DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
99
+++ b/hw/arm/vexpress.c
75
DEFINE_PROP_END_OF_LIST(),
100
@@ -XXX,XX +XXX,XX @@
76
};
101
77
102
#include "qemu/osdep.h"
78
@@ -XXX,XX +XXX,XX @@ static const TypeInfo sdhci_pci_info = {
103
#include "qapi/error.h"
79
},
104
-#include "qemu-common.h"
80
};
105
#include "qemu/datadir.h"
81
106
#include "cpu.h"
82
+/* --- qdev SysBus --- */
107
#include "hw/sysbus.h"
83
+
108
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
84
static Property sdhci_sysbus_properties[] = {
109
index XXXXXXX..XXXXXXX 100644
85
- DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
110
--- a/hw/arm/virt.c
86
- SDHC_CAPAB_REG_DEFAULT),
111
+++ b/hw/arm/virt.c
87
- DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
112
@@ -XXX,XX +XXX,XX @@
88
+ DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
113
*/
89
DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
114
90
false),
115
#include "qemu/osdep.h"
91
DEFINE_PROP_END_OF_LIST(),
116
-#include "qemu-common.h"
92
@@ -XXX,XX +XXX,XX @@ static const TypeInfo sdhci_sysbus_info = {
117
#include "qemu/datadir.h"
93
.class_init = sdhci_sysbus_class_init,
118
#include "qemu/units.h"
94
};
119
#include "qemu/option.h"
95
96
+/* --- qdev bus master --- */
97
+
98
static void sdhci_bus_class_init(ObjectClass *klass, void *data)
99
{
100
SDBusClass *sbc = SD_BUS_CLASS(klass);
101
--
120
--
102
2.7.4
121
2.25.1
103
122
104
123
diff view generated by jsdifflib
1
For PMSAv7, the v7A/R Arm ARM defines that setting AP to 0b111
1
The calculation of the length of TLB range invalidate operations
2
is an UNPREDICTABLE reserved combination. However, for v7M
2
in tlbi_aa64_range_get_length() is incorrect in two ways:
3
this value is documented as having the same behaviour as 0b110:
3
* the NUM field is 5 bits, but we read only 4 bits
4
read-only for both privileged and unprivileged. Accept this
4
* we miscalculate the page_shift value, because of an
5
value on an M profile core rather than treating it as a guest
5
off-by-one error:
6
error and a no-access page.
6
TG 0b00 is invalid
7
TG 0b01 is 4K granule size == 4096 == 2^12
8
TG 0b10 is 16K granule size == 16384 == 2^14
9
TG 0b11 is 64K granule size == 65536 == 2^16
10
so page_shift should be (TG - 1) * 2 + 12
7
11
8
Reported-by: Andy Gross <andy.gross@linaro.org>
12
Thanks to the bug report submitter Cha HyunSoo for identifying
13
both these errors.
14
15
Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE")
16
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 1512742402-31669-1-git-send-email-peter.maydell@linaro.org
21
Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org
12
---
22
---
13
target/arm/helper.c | 14 ++++++++++++++
23
target/arm/helper.c | 6 +++---
14
1 file changed, 14 insertions(+)
24
1 file changed, 3 insertions(+), 3 deletions(-)
15
25
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
26
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
28
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
29
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
30
@@ -XXX,XX +XXX,XX @@ static uint64_t tlbi_aa64_range_get_length(CPUARMState *env,
21
case 6:
31
uint64_t exponent;
22
*prot |= PAGE_READ | PAGE_EXEC;
32
uint64_t length;
23
break;
33
24
+ case 7:
34
- num = extract64(value, 39, 4);
25
+ /* for v7M, same as 6; for R profile a reserved value */
35
+ num = extract64(value, 39, 5);
26
+ if (arm_feature(env, ARM_FEATURE_M)) {
36
scale = extract64(value, 44, 2);
27
+ *prot |= PAGE_READ | PAGE_EXEC;
37
page_size_granule = extract64(value, 46, 2);
28
+ break;
38
29
+ }
39
- page_shift = page_size_granule * 2 + 12;
30
+ /* fall through */
40
-
31
default:
41
if (page_size_granule == 0) {
32
qemu_log_mask(LOG_GUEST_ERROR,
42
qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n",
33
"DRACR[%d]: Bad value for AP bits: 0x%"
43
page_size_granule);
34
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
44
return 0;
35
case 6:
45
}
36
*prot |= PAGE_READ | PAGE_EXEC;
46
37
break;
47
+ page_shift = (page_size_granule - 1) * 2 + 12;
38
+ case 7:
48
+
39
+ /* for v7M, same as 6; for R profile a reserved value */
49
exponent = (5 * scale) + 1;
40
+ if (arm_feature(env, ARM_FEATURE_M)) {
50
length = (num + 1) << (exponent + page_shift);
41
+ *prot |= PAGE_READ | PAGE_EXEC;
51
42
+ break;
43
+ }
44
+ /* fall through */
45
default:
46
qemu_log_mask(LOG_GUEST_ERROR,
47
"DRACR[%d]: Bad value for AP bits: 0x%"
48
--
52
--
49
2.7.4
53
2.25.1
50
54
51
55
diff view generated by jsdifflib
1
Instead of ignoring the response from address_space_ld*()
1
From: Patrick Venture <venture@google.com>
2
(indicating an attempt to read a page table descriptor from
3
an invalid physical address), use it to report the failure
4
correctly.
5
2
6
Since this is another couple of locations where we need to
3
The rx_active boolean change to true should always trigger a try_read
7
decide the value of the ARMMMUFaultInfo ea bit based on a
4
call that flushes the queue.
8
MemTxResult, we factor out that operation into a helper
9
function.
10
5
6
Signed-off-by: Patrick Venture <venture@google.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20211203221002.1719306-1-venture@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/internals.h | 10 ++++++++++
11
hw/net/npcm7xx_emc.c | 18 ++++++++----------
14
target/arm/helper.c | 39 ++++++++++++++++++++++++++++++++++-----
12
1 file changed, 8 insertions(+), 10 deletions(-)
15
target/arm/op_helper.c | 7 +------
16
3 files changed, 45 insertions(+), 11 deletions(-)
17
13
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
16
--- a/hw/net/npcm7xx_emc.c
21
+++ b/target/arm/internals.h
17
+++ b/hw/net/npcm7xx_emc.c
22
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
18
@@ -XXX,XX +XXX,XX @@ static void emc_halt_rx(NPCM7xxEMCState *emc, uint32_t mista_flag)
23
return fsc;
19
emc_set_mista(emc, mista_flag);
24
}
20
}
25
21
26
+static inline bool arm_extabort_type(MemTxResult result)
22
+static void emc_enable_rx_and_flush(NPCM7xxEMCState *emc)
27
+{
23
+{
28
+ /* The EA bit in syndromes and fault status registers is an
24
+ emc->rx_active = true;
29
+ * IMPDEF classification of external aborts. ARM implementations
25
+ qemu_flush_queued_packets(qemu_get_queue(emc->nic));
30
+ * usually use this to indicate AXI bus Decode error (0) or
31
+ * Slave error (1); in QEMU we follow that.
32
+ */
33
+ return result != MEMTX_DECODE_ERROR;
34
+}
26
+}
35
+
27
+
36
/* Do a page table walk and add page to TLB if possible */
28
static void emc_set_next_tx_descriptor(NPCM7xxEMCState *emc,
37
bool arm_tlb_fill(CPUState *cpu, vaddr address,
29
const NPCM7xxEMCTxDesc *tx_desc,
38
MMUAccessType access_type, int mmu_idx,
30
uint32_t desc_addr)
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ static ssize_t emc_receive(NetClientState *nc, const uint8_t *buf, size_t len1)
40
index XXXXXXX..XXXXXXX 100644
32
return len;
41
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
44
ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
45
&txattrs, &s2prot, &s2size, fi, NULL);
46
if (ret) {
47
+ assert(fi->type != ARMFault_None);
48
fi->s2addr = addr;
49
fi->stage2 = true;
50
fi->s1ptw = true;
51
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
52
ARMCPU *cpu = ARM_CPU(cs);
53
CPUARMState *env = &cpu->env;
54
MemTxAttrs attrs = {};
55
+ MemTxResult result = MEMTX_OK;
56
AddressSpace *as;
57
+ uint32_t data;
58
59
attrs.secure = is_secure;
60
as = arm_addressspace(cs, attrs);
61
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
62
return 0;
63
}
64
if (regime_translation_big_endian(env, mmu_idx)) {
65
- return address_space_ldl_be(as, addr, attrs, NULL);
66
+ data = address_space_ldl_be(as, addr, attrs, &result);
67
} else {
68
- return address_space_ldl_le(as, addr, attrs, NULL);
69
+ data = address_space_ldl_le(as, addr, attrs, &result);
70
}
71
+ if (result == MEMTX_OK) {
72
+ return data;
73
+ }
74
+ fi->type = ARMFault_SyncExternalOnWalk;
75
+ fi->ea = arm_extabort_type(result);
76
+ return 0;
77
}
33
}
78
34
79
static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
35
-static void emc_try_receive_next_packet(NPCM7xxEMCState *emc)
80
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
36
-{
81
ARMCPU *cpu = ARM_CPU(cs);
37
- if (emc_can_receive(qemu_get_queue(emc->nic))) {
82
CPUARMState *env = &cpu->env;
38
- qemu_flush_queued_packets(qemu_get_queue(emc->nic));
83
MemTxAttrs attrs = {};
39
- }
84
+ MemTxResult result = MEMTX_OK;
40
-}
85
AddressSpace *as;
41
-
86
+ uint32_t data;
42
static uint64_t npcm7xx_emc_read(void *opaque, hwaddr offset, unsigned size)
87
43
{
88
attrs.secure = is_secure;
44
NPCM7xxEMCState *emc = opaque;
89
as = arm_addressspace(cs, attrs);
45
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
90
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
46
emc->regs[REG_MGSTA] |= REG_MGSTA_RXHA;
91
return 0;
92
}
93
if (regime_translation_big_endian(env, mmu_idx)) {
94
- return address_space_ldq_be(as, addr, attrs, NULL);
95
+ data = address_space_ldq_be(as, addr, attrs, &result);
96
} else {
97
- return address_space_ldq_le(as, addr, attrs, NULL);
98
+ data = address_space_ldq_le(as, addr, attrs, &result);
99
+ }
100
+ if (result == MEMTX_OK) {
101
+ return data;
102
}
103
+ fi->type = ARMFault_SyncExternalOnWalk;
104
+ fi->ea = arm_extabort_type(result);
105
+ return 0;
106
}
107
108
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
109
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
110
}
111
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
112
mmu_idx, fi);
113
+ if (fi->type != ARMFault_None) {
114
+ goto do_fault;
115
+ }
116
type = (desc & 3);
117
domain = (desc >> 5) & 0x0f;
118
if (regime_el(env, mmu_idx) == 1) {
119
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
120
}
47
}
121
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
48
if (value & REG_MCMDR_RXON) {
122
mmu_idx, fi);
49
- emc->rx_active = true;
123
+ if (fi->type != ARMFault_None) {
50
+ emc_enable_rx_and_flush(emc);
124
+ goto do_fault;
51
} else {
125
+ }
52
emc_halt_rx(emc, 0);
126
switch (desc & 3) {
127
case 0: /* Page translation fault. */
128
fi->type = ARMFault_Translation;
129
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
130
}
131
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
132
mmu_idx, fi);
133
+ if (fi->type != ARMFault_None) {
134
+ goto do_fault;
135
+ }
136
type = (desc & 3);
137
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
138
/* Section translation fault, or attempt to use the encoding
139
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
140
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
141
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
142
mmu_idx, fi);
143
+ if (fi->type != ARMFault_None) {
144
+ goto do_fault;
145
+ }
146
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
147
switch (desc & 3) {
148
case 0: /* Page translation fault. */
149
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
150
descaddr &= ~7ULL;
151
nstable = extract32(tableattrs, 4, 1);
152
descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi);
153
- if (fi->s1ptw) {
154
+ if (fi->type != ARMFault_None) {
155
goto do_fault;
156
}
53
}
157
54
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_emc_write(void *opaque, hwaddr offset,
158
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
55
break;
159
index XXXXXXX..XXXXXXX 100644
56
case REG_RSDR:
160
--- a/target/arm/op_helper.c
57
if (emc->regs[REG_MCMDR] & REG_MCMDR_RXON) {
161
+++ b/target/arm/op_helper.c
58
- emc->rx_active = true;
162
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
59
- emc_try_receive_next_packet(emc);
163
/* now we have a real cpu fault */
60
+ emc_enable_rx_and_flush(emc);
164
cpu_restore_state(cs, retaddr);
61
}
165
62
break;
166
- /* The EA bit in syndromes and fault status registers is an
63
case REG_MIIDA:
167
- * IMPDEF classification of external aborts. ARM implementations
168
- * usually use this to indicate AXI bus Decode error (0) or
169
- * Slave error (1); in QEMU we follow that.
170
- */
171
- fi.ea = (response != MEMTX_DECODE_ERROR);
172
+ fi.ea = arm_extabort_type(response);
173
fi.type = ARMFault_SyncExternal;
174
deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
175
}
176
--
64
--
177
2.7.4
65
2.25.1
178
66
179
67
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
When a virtio-iommu is instantiated, describe it using the ACPI VIOT
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
table.
5
Message-id: 20180115182436.2066-11-f4bug@amsat.org
5
6
Acked-by: Igor Mammedov <imammedo@redhat.com>
7
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
9
Message-id: 20211210170415.583179-2-jean-philippe@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
hw/sd/sdhci-internal.h | 2 +-
12
hw/arm/virt-acpi-build.c | 7 +++++++
9
hw/sd/sdhci.c | 2 +-
13
hw/arm/Kconfig | 1 +
10
2 files changed, 2 insertions(+), 2 deletions(-)
14
2 files changed, 8 insertions(+)
11
15
12
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
16
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/sdhci-internal.h
18
--- a/hw/arm/virt-acpi-build.c
15
+++ b/hw/sd/sdhci-internal.h
19
+++ b/hw/arm/virt-acpi-build.c
16
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
17
#define SDHC_ACMD12ERRSTS 0x3C
21
#include "kvm_arm.h"
18
22
#include "migration/vmstate.h"
19
/* HWInit Capabilities Register 0x05E80080 */
23
#include "hw/acpi/ghes.h"
20
-#define SDHC_CAPAREG 0x40
24
+#include "hw/acpi/viot.h"
21
+#define SDHC_CAPAB 0x40
25
22
#define SDHC_CAN_DO_DMA 0x00400000
26
#define ARM_SPI_BASE 32
23
#define SDHC_CAN_DO_ADMA2 0x00080000
27
24
#define SDHC_CAN_DO_ADMA1 0x00100000
28
@@ -XXX,XX +XXX,XX @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
25
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
29
}
30
#endif
31
32
+ if (vms->iommu == VIRT_IOMMU_VIRTIO) {
33
+ acpi_add_table(table_offsets, tables_blob);
34
+ build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
35
+ vms->oem_id, vms->oem_table_id);
36
+ }
37
+
38
/* XSDT is pointed to by RSDP */
39
xsdt = tables_blob->len;
40
build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
41
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
26
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/sd/sdhci.c
43
--- a/hw/arm/Kconfig
28
+++ b/hw/sd/sdhci.c
44
+++ b/hw/arm/Kconfig
29
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
45
@@ -XXX,XX +XXX,XX @@ config ARM_VIRT
30
case SDHC_ACMD12ERRSTS:
46
select DIMM
31
ret = s->acmd12errsts;
47
select ACPI_HW_REDUCED
32
break;
48
select ACPI_APEI
33
- case SDHC_CAPAREG:
49
+ select ACPI_VIOT
34
+ case SDHC_CAPAB:
50
35
ret = s->capareg;
51
config CHEETAH
36
break;
52
bool
37
case SDHC_MAXCURR:
38
--
53
--
39
2.7.4
54
2.25.1
40
55
41
56
diff view generated by jsdifflib
1
Since milkymist-memcard is still using the legacy SD card API,
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
the SD card created by sd_init() is not plugged into any bus.
3
This means that the controller has to reset it manually.
4
2
5
Failing to do this mostly didn't affect the guest since the
3
virtio-iommu is now supported with ACPI VIOT as well as device tree.
6
guest typically does a programmed SD card reset as part of
4
Remove the restriction that prevents from instantiating a virtio-iommu
7
its SD controller driver initialization, but meant that
5
device under ACPI.
8
migration failed because it's only in sd_reset() that we
9
set up the wpgrps_size field.
10
6
11
Cc: qemu-stable@nongnu.org
7
Acked-by: Igor Mammedov <imammedo@redhat.com>
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Message-id: 20211210170415.583179-3-jean-philippe@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 1515506513-31961-3-git-send-email-peter.maydell@linaro.org
16
---
12
---
17
hw/sd/milkymist-memcard.c | 4 ++++
13
hw/arm/virt.c | 10 ++--------
18
1 file changed, 4 insertions(+)
14
hw/virtio/virtio-iommu-pci.c | 12 ++----------
15
2 files changed, 4 insertions(+), 18 deletions(-)
19
16
20
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/sd/milkymist-memcard.c
19
--- a/hw/arm/virt.c
23
+++ b/hw/sd/milkymist-memcard.c
20
+++ b/hw/arm/virt.c
24
@@ -XXX,XX +XXX,XX @@ static void milkymist_memcard_reset(DeviceState *d)
21
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
25
for (i = 0; i < R_MAX; i++) {
22
MachineClass *mc = MACHINE_GET_CLASS(machine);
26
s->regs[i] = 0;
23
24
if (device_is_dynamic_sysbus(mc, dev) ||
25
- (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
26
+ object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
27
+ object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
28
return HOTPLUG_HANDLER(machine);
27
}
29
}
28
+ /* Since we're still using the legacy SD API the card is not plugged
30
- if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
29
+ * into any bus, and we must reset it manually.
31
- VirtMachineState *vms = VIRT_MACHINE(machine);
30
+ */
32
-
31
+ device_reset(DEVICE(s->card));
33
- if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
34
- return HOTPLUG_HANDLER(machine);
35
- }
36
- }
37
return NULL;
32
}
38
}
33
39
34
static int milkymist_memcard_init(SysBusDevice *dev)
40
diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/virtio/virtio-iommu-pci.c
43
+++ b/hw/virtio/virtio-iommu-pci.c
44
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
45
VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
46
47
if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
48
- MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
49
-
50
- error_setg(errp,
51
- "%s machine fails to create iommu-map device tree bindings",
52
- mc->name);
53
- error_append_hint(errp,
54
- "Check your machine implements a hotplug handler "
55
- "for the virtio-iommu-pci device\n");
56
- error_append_hint(errp, "Check the guest is booted without FW or with "
57
- "-no-acpi\n");
58
+ error_setg(errp, "Check your machine implements a hotplug handler "
59
+ "for the virtio-iommu-pci device");
60
return;
61
}
62
for (int i = 0; i < s->nb_reserved_regions; i++) {
35
--
63
--
36
2.7.4
64
2.25.1
37
65
38
66
diff view generated by jsdifflib
1
Add virt-2.12 machine type.
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
We do not support instantiating multiple IOMMUs. Before adding a
4
virtio-iommu, check that no other IOMMU is present. This will detect
5
both "iommu=smmuv3" machine parameter and another virtio-iommu instance.
6
7
Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings")
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Message-id: 20211210170415.583179-4-jean-philippe@linaro.org
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
---
13
---
5
hw/arm/virt.c | 19 +++++++++++++++++--
14
hw/arm/virt.c | 5 +++++
6
1 file changed, 17 insertions(+), 2 deletions(-)
15
1 file changed, 5 insertions(+)
7
16
8
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
9
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
10
--- a/hw/arm/virt.c
19
--- a/hw/arm/virt.c
11
+++ b/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
12
@@ -XXX,XX +XXX,XX @@ static void machvirt_machine_init(void)
21
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
13
}
22
hwaddr db_start = 0, db_end = 0;
14
type_init(machvirt_machine_init);
23
char *resv_prop_str;
15
24
16
-static void virt_2_11_instance_init(Object *obj)
25
+ if (vms->iommu != VIRT_IOMMU_NONE) {
17
+static void virt_2_12_instance_init(Object *obj)
26
+ error_setg(errp, "virt machine does not support multiple IOMMUs");
18
{
27
+ return;
19
VirtMachineState *vms = VIRT_MACHINE(obj);
28
+ }
20
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
21
@@ -XXX,XX +XXX,XX @@ static void virt_2_11_instance_init(Object *obj)
22
vms->irqmap = a15irqmap;
23
}
24
25
+static void virt_machine_2_12_options(MachineClass *mc)
26
+{
27
+}
28
+DEFINE_VIRT_MACHINE_AS_LATEST(2, 12)
29
+
29
+
30
+#define VIRT_COMPAT_2_11 \
30
switch (vms->msi_controller) {
31
+ HW_COMPAT_2_11
31
case VIRT_MSI_CTRL_NONE:
32
+
32
return;
33
+static void virt_2_11_instance_init(Object *obj)
34
+{
35
+ virt_2_12_instance_init(obj);
36
+}
37
+
38
static void virt_machine_2_11_options(MachineClass *mc)
39
{
40
+ virt_machine_2_12_options(mc);
41
+ SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11);
42
}
43
-DEFINE_VIRT_MACHINE_AS_LATEST(2, 11)
44
+DEFINE_VIRT_MACHINE(2, 11)
45
46
#define VIRT_COMPAT_2_10 \
47
HW_COMPAT_2_10
48
--
33
--
49
2.7.4
34
2.25.1
50
35
51
36
diff view generated by jsdifflib
1
Since ssi-sd is still using the legacy SD card API, the SD
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
card created by sd_init() is not plugged into any bus. This
3
means that the controller has to reset it manually.
4
2
5
Failing to do this mostly didn't affect the guest since the
3
To propagate errors to the caller of the pre_plug callback, use the
6
guest typically does a programmed SD card reset as part of
4
object_poperty_set*() functions directly instead of the qdev_prop_set*()
7
its SD controller driver initialization, but meant that
5
helpers.
8
migration failed because it's only in sd_reset() that we
9
set up the wpgrps_size field.
10
6
11
In the case of sd-ssi, we have to implement an entire
7
Suggested-by: Igor Mammedov <imammedo@redhat.com>
12
reset function since there wasn't one previously, and
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
that requires a QOM cast macro that got omitted when this
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
14
device was QOMified.
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Message-id: 20211210170415.583179-5-jean-philippe@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/virt.c | 5 +++--
15
1 file changed, 3 insertions(+), 2 deletions(-)
15
16
16
Cc: qemu-stable@nongnu.org
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 1515506513-31961-4-git-send-email-peter.maydell@linaro.org
21
---
22
hw/sd/ssi-sd.c | 25 +++++++++++++++++++++++--
23
1 file changed, 23 insertions(+), 2 deletions(-)
24
25
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
26
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/sd/ssi-sd.c
19
--- a/hw/arm/virt.c
28
+++ b/hw/sd/ssi-sd.c
20
+++ b/hw/arm/virt.c
29
@@ -XXX,XX +XXX,XX @@ typedef struct {
21
@@ -XXX,XX +XXX,XX @@ static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
30
SDState *sd;
22
db_start, db_end,
31
} ssi_sd_state;
23
VIRTIO_IOMMU_RESV_MEM_T_MSI);
32
24
33
+#define TYPE_SSI_SD "ssi-sd"
25
- qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
34
+#define SSI_SD(obj) OBJECT_CHECK(ssi_sd_state, (obj), TYPE_SSI_SD)
26
- qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
35
+
27
+ object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
36
/* State word bits. */
28
+ object_property_set_str(OBJECT(dev), "reserved-regions[0]",
37
#define SSI_SDR_LOCKED 0x0001
29
+ resv_prop_str, errp);
38
#define SSI_SDR_WP_ERASE 0x0002
30
g_free(resv_prop_str);
39
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSISlave *d, Error **errp)
40
ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
41
DriveInfo *dinfo;
42
43
- s->mode = SSI_SD_CMD;
44
/* FIXME use a qdev drive property instead of drive_get_next() */
45
dinfo = drive_get_next(IF_SD);
46
s->sd = sd_init(dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, true);
47
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSISlave *d, Error **errp)
48
}
31
}
49
}
32
}
50
51
+static void ssi_sd_reset(DeviceState *dev)
52
+{
53
+ ssi_sd_state *s = SSI_SD(dev);
54
+
55
+ s->mode = SSI_SD_CMD;
56
+ s->cmd = 0;
57
+ memset(s->cmdarg, 0, sizeof(s->cmdarg));
58
+ memset(s->response, 0, sizeof(s->response));
59
+ s->arglen = 0;
60
+ s->response_pos = 0;
61
+ s->stopping = 0;
62
+
63
+ /* Since we're still using the legacy SD API the card is not plugged
64
+ * into any bus, and we must reset it manually.
65
+ */
66
+ device_reset(DEVICE(s->sd));
67
+}
68
+
69
static void ssi_sd_class_init(ObjectClass *klass, void *data)
70
{
71
DeviceClass *dc = DEVICE_CLASS(klass);
72
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_class_init(ObjectClass *klass, void *data)
73
k->transfer = ssi_sd_transfer;
74
k->cs_polarity = SSI_CS_LOW;
75
dc->vmsd = &vmstate_ssi_sd;
76
+ dc->reset = ssi_sd_reset;
77
}
78
79
static const TypeInfo ssi_sd_info = {
80
- .name = "ssi-sd",
81
+ .name = TYPE_SSI_SD,
82
.parent = TYPE_SSI_SLAVE,
83
.instance_size = sizeof(ssi_sd_state),
84
.class_init = ssi_sd_class_init,
85
--
33
--
86
2.7.4
34
2.25.1
87
35
88
36
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Create empty data files and allow updates for the upcoming VIOT tests.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180115182436.2066-10-f4bug@amsat.org
5
Acked-by: Igor Mammedov <imammedo@redhat.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
8
Message-id: 20211210170415.583179-6-jean-philippe@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/sd/sdhci-internal.h | 1 +
11
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
9
hw/sd/sdhci.c | 3 +--
12
tests/data/acpi/q35/DSDT.viot | 0
10
2 files changed, 2 insertions(+), 2 deletions(-)
13
tests/data/acpi/q35/VIOT.viot | 0
14
tests/data/acpi/virt/VIOT | 0
15
4 files changed, 3 insertions(+)
16
create mode 100644 tests/data/acpi/q35/DSDT.viot
17
create mode 100644 tests/data/acpi/q35/VIOT.viot
18
create mode 100644 tests/data/acpi/virt/VIOT
11
19
12
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
20
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
13
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/sdhci-internal.h
22
--- a/tests/qtest/bios-tables-test-allowed-diff.h
15
+++ b/hw/sd/sdhci-internal.h
23
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
16
@@ -XXX,XX +XXX,XX @@
24
@@ -1 +1,4 @@
17
#define SDHC_TRNS_ACMD12 0x0004
25
/* List of comma-separated changed AML files to ignore */
18
#define SDHC_TRNS_READ 0x0010
26
+"tests/data/acpi/virt/VIOT",
19
#define SDHC_TRNS_MULTI 0x0020
27
+"tests/data/acpi/q35/DSDT.viot",
20
+#define SDHC_TRNMOD_MASK 0x0037
28
+"tests/data/acpi/q35/VIOT.viot",
21
29
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
22
/* R/W Command Register 0x0 */
30
new file mode 100644
23
#define SDHC_CMDREG 0x0E
31
index XXXXXXX..XXXXXXX
24
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
32
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
25
index XXXXXXX..XXXXXXX 100644
33
new file mode 100644
26
--- a/hw/sd/sdhci.c
34
index XXXXXXX..XXXXXXX
27
+++ b/hw/sd/sdhci.c
35
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
28
@@ -XXX,XX +XXX,XX @@
36
new file mode 100644
29
(SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
37
index XXXXXXX..XXXXXXX
30
(SDHC_CAPAB_TOCLKFREQ))
31
32
-#define MASK_TRNMOD 0x0037
33
#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
34
35
static uint8_t sdhci_slotint(SDHCIState *s)
36
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
37
if (!(s->capareg & SDHC_CAN_DO_DMA)) {
38
value &= ~SDHC_TRNS_DMA;
39
}
40
- MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD);
41
+ MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
42
MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
43
44
/* Writing to the upper byte of CMDREG triggers SD command generation */
45
--
38
--
46
2.7.4
39
2.25.1
47
40
48
41
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Add two test cases for VIOT, one on the q35 machine and the other on
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
virt. To test complex topologies the q35 test has two PCIe buses that
5
Message-id: 20180115182436.2066-7-f4bug@amsat.org
5
bypass the IOMMU (and are therefore not described by VIOT), and two
6
buses that are translated by virtio-iommu.
7
8
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
10
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
11
Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
hw/sd/sdhci.c | 22 ++++++++++++++++++++++
14
tests/qtest/bios-tables-test.c | 38 ++++++++++++++++++++++++++++++++++
9
1 file changed, 22 insertions(+)
15
1 file changed, 38 insertions(+)
10
16
11
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
17
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sdhci.c
19
--- a/tests/qtest/bios-tables-test.c
14
+++ b/hw/sd/sdhci.c
20
+++ b/tests/qtest/bios-tables-test.c
15
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ static void test_acpi_virt_tcg(void)
16
#include "qemu/bitops.h"
22
free_test_data(&data);
17
#include "hw/sd/sdhci.h"
18
#include "sdhci-internal.h"
19
+#include "qapi/error.h"
20
#include "qemu/log.h"
21
22
/* host controller debug messages */
23
@@ -XXX,XX +XXX,XX @@ static void sdhci_common_realize(SDHCIState *s, Error **errp)
24
SDHC_REGISTERS_MAP_SIZE);
25
}
23
}
26
24
27
+static void sdhci_common_unrealize(SDHCIState *s, Error **errp)
25
+static void test_acpi_q35_viot(void)
28
+{
26
+{
29
+ /* This function is expected to be called only once for each class:
27
+ test_data data = {
30
+ * - SysBus: via DeviceClass->unrealize(),
28
+ .machine = MACHINE_Q35,
31
+ * - PCI: via PCIDeviceClass->exit().
29
+ .variant = ".viot",
32
+ * However to avoid double-free and/or use-after-free we still nullify
30
+ };
33
+ * this variable (better safe than sorry!). */
31
+
34
+ g_free(s->fifo_buffer);
32
+ /*
35
+ s->fifo_buffer = NULL;
33
+ * To keep things interesting, two buses bypass the IOMMU.
34
+ * VIOT should only describes the other two buses.
35
+ */
36
+ test_acpi_one("-machine default_bus_bypass_iommu=on "
37
+ "-device virtio-iommu-pci "
38
+ "-device pxb-pcie,bus_nr=0x10,id=pcie.100,bus=pcie.0 "
39
+ "-device pxb-pcie,bus_nr=0x20,id=pcie.200,bus=pcie.0,bypass_iommu=on "
40
+ "-device pxb-pcie,bus_nr=0x30,id=pcie.300,bus=pcie.0",
41
+ &data);
42
+ free_test_data(&data);
36
+}
43
+}
37
+
44
+
38
static bool sdhci_pending_insert_vmstate_needed(void *opaque)
45
+static void test_acpi_virt_viot(void)
39
{
46
+{
40
SDHCIState *s = opaque;
47
+ test_data data = {
41
@@ -XXX,XX +XXX,XX @@ static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
48
+ .machine = "virt",
42
static void sdhci_pci_exit(PCIDevice *dev)
49
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
43
{
50
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
44
SDHCIState *s = PCI_SDHCI(dev);
51
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
52
+ .ram_start = 0x40000000ULL,
53
+ .scan_len = 128ULL * 1024 * 1024,
54
+ };
45
+
55
+
46
+ sdhci_common_unrealize(s, &error_abort);
56
+ test_acpi_one("-cpu cortex-a57 "
47
sdhci_uninitfn(s);
57
+ "-device virtio-iommu-pci", &data);
48
}
58
+ free_test_data(&data);
49
50
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
51
sysbus_init_mmio(sbd, &s->iomem);
52
}
53
54
+static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp)
55
+{
56
+ SDHCIState *s = SYSBUS_SDHCI(dev);
57
+
58
+ sdhci_common_unrealize(s, &error_abort);
59
+}
59
+}
60
+
60
+
61
static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
61
static void test_oem_fields(test_data *data)
62
{
62
{
63
DeviceClass *dc = DEVICE_CLASS(klass);
63
int i;
64
64
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
65
dc->props = sdhci_sysbus_properties;
65
qtest_add_func("acpi/q35/kvm/xapic", test_acpi_q35_kvm_xapic);
66
dc->realize = sdhci_sysbus_realize;
66
qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
67
+ dc->unrealize = sdhci_sysbus_unrealize;
67
}
68
68
+ qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
69
sdhci_common_class_init(klass, data);
69
} else if (strcmp(arch, "aarch64") == 0) {
70
}
70
if (has_tcg) {
71
qtest_add_func("acpi/virt", test_acpi_virt_tcg);
72
@@ -XXX,XX +XXX,XX @@ int main(int argc, char *argv[])
73
qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
74
qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb);
75
qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt);
76
+ qtest_add_func("acpi/virt/viot", test_acpi_virt_viot);
77
}
78
}
79
ret = g_test_run();
71
--
80
--
72
2.7.4
81
2.25.1
73
82
74
83
diff view generated by jsdifflib
New patch
1
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
3
Add expected blobs of the VIOT and DSDT table for the VIOT test on the
4
q35 machine.
5
6
Since the test instantiates a virtio device and two PCIe expander
7
bridges, DSDT.viot has more blocks than the base DSDT.
8
9
The VIOT table generated for the q35 test is:
10
11
[000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table]
12
[004h 0004 4] Table Length : 00000070
13
[008h 0008 1] Revision : 00
14
[009h 0009 1] Checksum : 3D
15
[00Ah 0010 6] Oem ID : "BOCHS "
16
[010h 0016 8] Oem Table ID : "BXPC "
17
[018h 0024 4] Oem Revision : 00000001
18
[01Ch 0028 4] Asl Compiler ID : "BXPC"
19
[020h 0032 4] Asl Compiler Revision : 00000001
20
21
[024h 0036 2] Node count : 0003
22
[026h 0038 2] Node offset : 0030
23
[028h 0040 8] Reserved : 0000000000000000
24
25
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
26
[031h 0049 1] Reserved : 00
27
[032h 0050 2] Length : 0010
28
29
[034h 0052 2] PCI Segment : 0000
30
[036h 0054 2] PCI BDF number : 0010
31
[038h 0056 8] Reserved : 0000000000000000
32
33
[040h 0064 1] Type : 01 [PCI Range]
34
[041h 0065 1] Reserved : 00
35
[042h 0066 2] Length : 0018
36
37
[044h 0068 4] Endpoint start : 00003000
38
[048h 0072 2] PCI Segment start : 0000
39
[04Ah 0074 2] PCI Segment end : 0000
40
[04Ch 0076 2] PCI BDF start : 3000
41
[04Eh 0078 2] PCI BDF end : 30FF
42
[050h 0080 2] Output node : 0030
43
[052h 0082 6] Reserved : 000000000000
44
45
[058h 0088 1] Type : 01 [PCI Range]
46
[059h 0089 1] Reserved : 00
47
[05Ah 0090 2] Length : 0018
48
49
[05Ch 0092 4] Endpoint start : 00001000
50
[060h 0096 2] PCI Segment start : 0000
51
[062h 0098 2] PCI Segment end : 0000
52
[064h 0100 2] PCI BDF start : 1000
53
[066h 0102 2] PCI BDF end : 10FF
54
[068h 0104 2] Output node : 0030
55
[06Ah 0106 6] Reserved : 000000000000
56
57
And the DSDT diff is:
58
59
@@ -XXX,XX +XXX,XX @@
60
*
61
* Disassembling to symbolic ASL+ operators
62
*
63
- * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021
64
+ * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021
65
*
66
* Original Table Header:
67
* Signature "DSDT"
68
- * Length 0x00002061 (8289)
69
+ * Length 0x000024B6 (9398)
70
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
71
- * Checksum 0xFA
72
+ * Checksum 0xA7
73
* OEM ID "BOCHS "
74
* OEM Table ID "BXPC "
75
* OEM Revision 0x00000001 (1)
76
@@ -XXX,XX +XXX,XX @@
77
}
78
}
79
80
+ Scope (\_SB)
81
+ {
82
+ Device (PC30)
83
+ {
84
+ Name (_UID, 0x30) // _UID: Unique ID
85
+ Name (_BBN, 0x30) // _BBN: BIOS Bus Number
86
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
87
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
88
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
89
+ {
90
+ CreateDWordField (Arg3, Zero, CDW1)
91
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
92
+ {
93
+ CreateDWordField (Arg3, 0x04, CDW2)
94
+ CreateDWordField (Arg3, 0x08, CDW3)
95
+ Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */
96
+ Local0 &= 0x1F
97
+ If ((Arg1 != One))
98
+ {
99
+ CDW1 |= 0x08
100
+ }
101
+
102
+ If ((CDW3 != Local0))
103
+ {
104
+ CDW1 |= 0x10
105
+ }
106
+
107
+ CDW3 = Local0
108
+ }
109
+ Else
110
+ {
111
+ CDW1 |= 0x04
112
+ }
113
+
114
+ Return (Arg3)
115
+ }
116
+
117
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
118
+ {
119
+ Local0 = Package (0x80){}
120
+ Local1 = Zero
121
+ While ((Local1 < 0x80))
122
+ {
123
+ Local2 = (Local1 >> 0x02)
124
+ Local3 = ((Local1 + Local2) & 0x03)
125
+ If ((Local3 == Zero))
126
+ {
127
+ Local4 = Package (0x04)
128
+ {
129
+ Zero,
130
+ Zero,
131
+ LNKD,
132
+ Zero
133
+ }
134
+ }
135
+
136
+ If ((Local3 == One))
137
+ {
138
+ Local4 = Package (0x04)
139
+ {
140
+ Zero,
141
+ Zero,
142
+ LNKA,
143
+ Zero
144
+ }
145
+ }
146
+
147
+ If ((Local3 == 0x02))
148
+ {
149
+ Local4 = Package (0x04)
150
+ {
151
+ Zero,
152
+ Zero,
153
+ LNKB,
154
+ Zero
155
+ }
156
+ }
157
+
158
+ If ((Local3 == 0x03))
159
+ {
160
+ Local4 = Package (0x04)
161
+ {
162
+ Zero,
163
+ Zero,
164
+ LNKC,
165
+ Zero
166
+ }
167
+ }
168
+
169
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
170
+ Local4 [One] = (Local1 & 0x03)
171
+ Local0 [Local1] = Local4
172
+ Local1++
173
+ }
174
+
175
+ Return (Local0)
176
+ }
177
+
178
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
179
+ {
180
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
181
+ 0x0000, // Granularity
182
+ 0x0030, // Range Minimum
183
+ 0x0030, // Range Maximum
184
+ 0x0000, // Translation Offset
185
+ 0x0001, // Length
186
+ ,, )
187
+ })
188
+ }
189
+ }
190
+
191
+ Scope (\_SB)
192
+ {
193
+ Device (PC20)
194
+ {
195
+ Name (_UID, 0x20) // _UID: Unique ID
196
+ Name (_BBN, 0x20) // _BBN: BIOS Bus Number
197
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
198
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
199
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
200
+ {
201
+ CreateDWordField (Arg3, Zero, CDW1)
202
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
203
+ {
204
+ CreateDWordField (Arg3, 0x04, CDW2)
205
+ CreateDWordField (Arg3, 0x08, CDW3)
206
+ Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */
207
+ Local0 &= 0x1F
208
+ If ((Arg1 != One))
209
+ {
210
+ CDW1 |= 0x08
211
+ }
212
+
213
+ If ((CDW3 != Local0))
214
+ {
215
+ CDW1 |= 0x10
216
+ }
217
+
218
+ CDW3 = Local0
219
+ }
220
+ Else
221
+ {
222
+ CDW1 |= 0x04
223
+ }
224
+
225
+ Return (Arg3)
226
+ }
227
+
228
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
229
+ {
230
+ Local0 = Package (0x80){}
231
+ Local1 = Zero
232
+ While ((Local1 < 0x80))
233
+ {
234
+ Local2 = (Local1 >> 0x02)
235
+ Local3 = ((Local1 + Local2) & 0x03)
236
+ If ((Local3 == Zero))
237
+ {
238
+ Local4 = Package (0x04)
239
+ {
240
+ Zero,
241
+ Zero,
242
+ LNKD,
243
+ Zero
244
+ }
245
+ }
246
+
247
+ If ((Local3 == One))
248
+ {
249
+ Local4 = Package (0x04)
250
+ {
251
+ Zero,
252
+ Zero,
253
+ LNKA,
254
+ Zero
255
+ }
256
+ }
257
+
258
+ If ((Local3 == 0x02))
259
+ {
260
+ Local4 = Package (0x04)
261
+ {
262
+ Zero,
263
+ Zero,
264
+ LNKB,
265
+ Zero
266
+ }
267
+ }
268
+
269
+ If ((Local3 == 0x03))
270
+ {
271
+ Local4 = Package (0x04)
272
+ {
273
+ Zero,
274
+ Zero,
275
+ LNKC,
276
+ Zero
277
+ }
278
+ }
279
+
280
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
281
+ Local4 [One] = (Local1 & 0x03)
282
+ Local0 [Local1] = Local4
283
+ Local1++
284
+ }
285
+
286
+ Return (Local0)
287
+ }
288
+
289
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
290
+ {
291
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
292
+ 0x0000, // Granularity
293
+ 0x0020, // Range Minimum
294
+ 0x0020, // Range Maximum
295
+ 0x0000, // Translation Offset
296
+ 0x0001, // Length
297
+ ,, )
298
+ })
299
+ }
300
+ }
301
+
302
+ Scope (\_SB)
303
+ {
304
+ Device (PC10)
305
+ {
306
+ Name (_UID, 0x10) // _UID: Unique ID
307
+ Name (_BBN, 0x10) // _BBN: BIOS Bus Number
308
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
309
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
310
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
311
+ {
312
+ CreateDWordField (Arg3, Zero, CDW1)
313
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
314
+ {
315
+ CreateDWordField (Arg3, 0x04, CDW2)
316
+ CreateDWordField (Arg3, 0x08, CDW3)
317
+ Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */
318
+ Local0 &= 0x1F
319
+ If ((Arg1 != One))
320
+ {
321
+ CDW1 |= 0x08
322
+ }
323
+
324
+ If ((CDW3 != Local0))
325
+ {
326
+ CDW1 |= 0x10
327
+ }
328
+
329
+ CDW3 = Local0
330
+ }
331
+ Else
332
+ {
333
+ CDW1 |= 0x04
334
+ }
335
+
336
+ Return (Arg3)
337
+ }
338
+
339
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
340
+ {
341
+ Local0 = Package (0x80){}
342
+ Local1 = Zero
343
+ While ((Local1 < 0x80))
344
+ {
345
+ Local2 = (Local1 >> 0x02)
346
+ Local3 = ((Local1 + Local2) & 0x03)
347
+ If ((Local3 == Zero))
348
+ {
349
+ Local4 = Package (0x04)
350
+ {
351
+ Zero,
352
+ Zero,
353
+ LNKD,
354
+ Zero
355
+ }
356
+ }
357
+
358
+ If ((Local3 == One))
359
+ {
360
+ Local4 = Package (0x04)
361
+ {
362
+ Zero,
363
+ Zero,
364
+ LNKA,
365
+ Zero
366
+ }
367
+ }
368
+
369
+ If ((Local3 == 0x02))
370
+ {
371
+ Local4 = Package (0x04)
372
+ {
373
+ Zero,
374
+ Zero,
375
+ LNKB,
376
+ Zero
377
+ }
378
+ }
379
+
380
+ If ((Local3 == 0x03))
381
+ {
382
+ Local4 = Package (0x04)
383
+ {
384
+ Zero,
385
+ Zero,
386
+ LNKC,
387
+ Zero
388
+ }
389
+ }
390
+
391
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
392
+ Local4 [One] = (Local1 & 0x03)
393
+ Local0 [Local1] = Local4
394
+ Local1++
395
+ }
396
+
397
+ Return (Local0)
398
+ }
399
+
400
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
401
+ {
402
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
403
+ 0x0000, // Granularity
404
+ 0x0010, // Range Minimum
405
+ 0x0010, // Range Maximum
406
+ 0x0000, // Translation Offset
407
+ 0x0001, // Length
408
+ ,, )
409
+ })
410
+ }
411
+ }
412
+
413
Scope (\_SB.PCI0)
414
{
415
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
416
@@ -XXX,XX +XXX,XX @@
417
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
418
0x0000, // Granularity
419
0x0000, // Range Minimum
420
- 0x00FF, // Range Maximum
421
+ 0x000F, // Range Maximum
422
0x0000, // Translation Offset
423
- 0x0100, // Length
424
+ 0x0010, // Length
425
,, )
426
IO (Decode16,
427
0x0CF8, // Range Minimum
428
@@ -XXX,XX +XXX,XX @@
429
}
430
}
431
432
+ Device (S10)
433
+ {
434
+ Name (_ADR, 0x00020000) // _ADR: Address
435
+ }
436
+
437
+ Device (S18)
438
+ {
439
+ Name (_ADR, 0x00030000) // _ADR: Address
440
+ }
441
+
442
+ Device (S20)
443
+ {
444
+ Name (_ADR, 0x00040000) // _ADR: Address
445
+ }
446
+
447
+ Device (S28)
448
+ {
449
+ Name (_ADR, 0x00050000) // _ADR: Address
450
+ }
451
+
452
Method (PCNT, 0, NotSerialized)
453
{
454
}
455
456
Reviewed-by: Eric Auger <eric.auger@redhat.com>
457
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
458
Message-id: 20211210170415.583179-8-jean-philippe@linaro.org
459
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
460
---
461
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
462
tests/data/acpi/q35/DSDT.viot | Bin 0 -> 9398 bytes
463
tests/data/acpi/q35/VIOT.viot | Bin 0 -> 112 bytes
464
3 files changed, 2 deletions(-)
465
466
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
467
index XXXXXXX..XXXXXXX 100644
468
--- a/tests/qtest/bios-tables-test-allowed-diff.h
469
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
470
@@ -XXX,XX +XXX,XX @@
471
/* List of comma-separated changed AML files to ignore */
472
"tests/data/acpi/virt/VIOT",
473
-"tests/data/acpi/q35/DSDT.viot",
474
-"tests/data/acpi/q35/VIOT.viot",
475
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
476
index XXXXXXX..XXXXXXX 100644
477
GIT binary patch
478
literal 9398
479
zcmeHNO>7&-8J*>iv|O&FB}G~Oi$yp||57BBoWHhc5OS9yDTx$CQgH$r;8Idr*-4Q_
480
z5(9Az1F`}niVsB-)<KW7p`g9Br(A2Gm-gmc1N78GFS!;)e2V(MnH_0{q<{#yMgn&C
481
zn|*J-d9yqFhO_H6z19~`FlPL*u<DkZ*}|)JH;X@mF-FI<cPg<fti9tEN*yB^i5czN
482
zNq&q?!OZ;BE3B7{KWzJ-`Tn~f`9?Qj8~2^N8{Oc8J%57{==w%rS#;nOCp*nTr@iZ1
483
zb+?i;JLQUJ=O0?8*>S~D)a>NF1~WVB6^~_B#yhJ`H+JU@=6aXs`?Yv)J2h=N?drcS
484
zeLZ*n<<Bm^n}6`jfBx#u8&(W}1?)}iF9o#mZ~E2+zwdn7yK3AbIzKnxpZ>JRPm3~#
485
z&ICS{+_OayRW-l=Mtk=~uaS3o8z<_udd|(wqg`&JnVPfCe>BUOO`Su3e>pff_^UW%
486
z&JE^NO`)=Amg~iqRB1pPscP?(>#ZuY8GHCmlEvD$9g3%4Db~Dfz2SATnddvrR-Oe^
487
z;s;dJec!hnzi)ri^I6YN9vtkm{^TdUF8h7gX8-<Qe4p)GQ=)AtYx2VcwdLVAEXEjG
488
z^Mj|UHPqkj-LsWuzQem1>F3atdZn=zv3$#RmZzSHN+6-yyU#8cJb=YDilX&sl}vNm
489
znkgAR^O<3kj4if>{ly5fwRfMWuC5=lrlvKPX~i#654Cp}R_d*JS$9laZ$ra6)<ns8
490
zFZy28G%xP(nit&F>LDi%G<tIc=TY=gl$jSD&Uv!Yat~XR46h%rI$!}a%!|xG7u8Zn
491
zeY8_|n=K>xz_v_W8VX$W-Fg-qFWcT}7MCyz{%%{ia7hZ>Law-k6NOr}VI&_48U=2l
492
zwqDKFE8eTwwozDdms#e?x?5a|v>&JF;2_v0L~z5n%BYU^52<*cWuD4|GYUm@1+?))
493
zte^45>Rz)t*<T5V#={r>@t@{%?^i#W{i=HAZ*Dc9y59Va-+#P!jrGs;u38a{fLr`N
494
zvT@rUu>DljxJ?^&Z?-?vyJn3C>3D=qux{Y*bs5|5n)Qmi$TD^Zdn4GU$ocJS2Hh-<
495
z`xPI^^+v0nUVdjMos8k`WGl7hA`{03ju%<lrgAHSpd^DRf-*}_#Ly0mB!LSfVgWcQ
496
z&T$@~G9)JI=hz5m0vkrel+Xy{Oh7pkAu-V!j*W7rY(bO}Q$nMH2`FbGB&N)QaV4<4
497
zo)~9JXiP9=;}NPl<C@MmXG&;XFlFNrsyfFsonxFSp<}vEgsRSQP3O3#b6nSnP}ON_
498
zI!#Tdsp~|j>ckUB>FI=~GokB5sOq#dotCE4(sd$KbtW~PNlj-`*NIToiD#j5J#9^=
499
zt?NXn>YUJYPG~wObe#xQos*i*NloXZt`niEb4t@WrRki~bs|)CI+{*L)9L6s5vn><
500
zn$DD_Go|Z9sOn5>I@6lYw5}7Os&iV?Ij!lO)^#FOb!If38BJ$K*NIToIiu;E(R9w}
501
zIuWWmPiZ<&X*y5oIuWWmF_XaEC!a&Jn$B5WCqh-{X-(&8P3LJ{Cqh-{8P3dyPr@^t
502
zSqL9?X9Uwd3W@23*s~h*tj0X6GZCuHa~kuU#yqDp5vt7d8uPryJg+kms?5hU=3^T3
503
zF`bD}WnSP+=`t5MQ$FJ_2&Q~+BP6E0f^%BVIW6a$o)e+SX~IDBih-7z6{O~7YTy`&
504
zLjy&Cv?7QikV#>n0>>@MV8oK`Gmun34-FKdlm-J8SZSaNlnhir4-FI{S|bfqV8e)V
505
zss<{chX#reE#g=hsKAC%sF6d-Km}BWs!kZFsFpKfpbC@>6rprQGEjt4Ck#|zITHq|
506
zK*>M_l;<P^MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=xY&!axO<
507
zGhv_#lnhirIg<<&q0|Wj6<E%MfhtfkPyyvkGEjt4Ck#|zITHq|K*>M_lrzad5lWpf
508
zP=V!47^ngz0~JutBm+e#b;3XemNQ|X3X}{~Ksl2P6rt1!0~J`#gn=qhGEf2KOfpb}
509
zQYQ>lU^x>8szAv=1(Y+%KoLrvFi?TzOc<yFB?A>u&LjgxD0RX>1(q{mpbC@>R6seC
510
z3>2Z%2?G^a&V+#~P%=;f<xDbAgi<FARA4z12C6{GKn0XD$v_cGoiI>=<xCi;0wn_#
511
zP|hR+MJRQ`Kn0dFVW0|>3{*fllMEE0)CmI>Sk8ojDo`>|0p(0GP=rz^3{+q_69%e4
512
z$v_2^Gs!>^N}VuJf#pmXr~)Me6;RG314Srx!axxz28u{EP=u<1B2)}iVZuNaCK;&0
513
zBm-5LFi?dF167!0pbC==RAItE6($T+VUmF=Ofpb~2?JG_Fi?d_2C6X0Kouqo6p_5T
514
zFi=FeV!SiSKoR0H$dH(_Z(*Q_WZ%L-5y`$K14StNmJAdjmWs}HV4<vU_xO+1efmLq
515
zZ;W>N_U)fP6Qy6Nw5mbt9Y(#emWSi66=>tq#xoh#Ue=0qyhxi8ZOUe5y0V7VfPUhp
516
zwX=;ymc+i5%sg9Ja~lZ&8oAV@mHc>&CHP9v4R(jhtT?un;O4e9#pno)Xkh7OWgK&a
517
zyj=3Iv0OuoK_;5rOr5f(Kb~ZXDBO+V`OWYo#_C08imwChQxnjdd?wZLDou8aj;$SD
518
zGDYiA3<$Tu<JnHL(KPOChi#zrR32t83}naR$+ym4P_h?z_5#|cW-nw$XD_sOtE62l
519
zrD3@*)NVyiklt0&yF9%+klsBey&I<Y2E<!f(E8TuJte)z(|ZHyy<^gQVfx}=`q&B5
520
z7nSryp1wGczIaUfVwiq$Fn#<4=@*ssi#+|}K>EdF(l3VTOM~ghPLRH&q%ZOGrGfON
521
zW73zx^yR_y<0nX8R??Sw`tm^f@-gYlNFSp|*<gA{q?Zp5Oe-+l#rmyYmKozi9y=P>
522
zVReJU*h=ZuVXiS$ohTbw-O#v9>(yZbGE|)?8(H1ZIKvV!jWa0>vy!3eMA^vdhQ>`s
523
zuMSg{q3T50$m)j1!HixV<}X9liL#N^4c*tL^y)CF8LCc{jjV3yKAqL8!%SzWI#H%q
524
z=bSrQ&)%JCRttF5g4Zf`6l?y@>PzD7MA^D>wBlcH6r1ucwJ<p0O%rZ?JzIY3-QdmZ
525
zzs|n>`a5r3e|z)wcUaqS>nqFQ-8x}eCF4u`OWUxqst-@1rSmUs%WmKP5e0dcb?e2N
526
z;Z|x*!);VwF|Yuhqs^khqOM!@u*jY!WYldISF(V6`BoNd&6Qfk3>X#SuD^7J>p_D=
527
zBPa51y^_n#=cpOt#Zf$ya$Ae9Mfz56n|<i!a=ELS@)%a{^NIH3SDuN<R~sah1km#P
528
zU@?*f%<rG=4W1wgfi;C?_n|W@%lm$&8YfvNOJodIg&IcIpIJQRHr<+ej11GQ6)&eF
529
z2Lam*jIH}#y0>KnY%4JQfOYS$*uU%f#@$U6`N8I3N-lV?5ErFCdv~xDmu2(wexld4
530
z4v^;aVAT2k6GJ^m*FD(Wqc(Qg^)6a<?}h$zLoj}4;PP!+(O{@!a1y-hoAhF_7!z+6
531
zslpAmNtYbjHrw-~#SPVk_FUf>-Obg6yV`8o$8_`PyJe_;bY5_EMBfBfWU!Q=*9HsG
532
z%_Cda{@_Krr!oHVhv9+y+T5qR8zZ2aZ>5r!$*|f$^U%yBUYfR&B!+EYy_PwL!BeUi
533
zJH^}r3r9Q+B)X@Z)fk=P13w&7x#wBtXTZ)g>WITPg5r&pQc!nmyrmk#S(>>b9xnNr
534
zx_b#v9Xv-Y><Wb%?S^0Xe&<)bbKl_=Z|3C$tf|F<bYzE*mfHB;uC)`q-?buaBe?l?
535
zcLTpK*k<49Z32`K?|nSBMFqxTK^_IE-li2fEGdK~(ZdoKBl6ab4a;Hler#`xvEXJG
536
zb?<E%EZExfX>jcOVhS*0rS~RS1dA#xhkv@Nct@#q?LyeKS<$uFec!bw>{@uu$gZ6a
537
zyVen1i{1BKd%~`D7|m$;U0a<I*3I7%^N%N%lGYdU_GS!gaR8T$NA@GzFi~z`l7hdl
538
zarZy6590|88pi(1zq;V(>38zM0sT&<zX;R5$1w3;`_JMG`;&I&0Y23DMx1%@(w(R9
539
z4M$j;D5J+Gy%fijRQsctzFKf&cv|BAz#YLq3CZJWDdtL4u1u1|mkdcUp7|sxJC+?Y
540
z_@@s`v3j}Q7*z>6X~cwUxUL8G1KT)_XTp!KAbs;vCp{K3&~_X@+ew=-D}v`2MbFV0
541
zQsVsL=rXi-pI*G|iiz;VTCutgUs)hDzV1+4?8KcoP3xROf<M%qC6lgVdpFt4<-|uM
542
z=#rl_b1#YjSIl6Toj2z_hOZcKupkdE(LozC(fN=FY(x|sk)ym|;Rq2E1xJWD%Z!ol
543
Gu>S+TT-130
544
545
literal 0
546
HcmV?d00001
547
548
diff --git a/tests/data/acpi/q35/VIOT.viot b/tests/data/acpi/q35/VIOT.viot
549
index XXXXXXX..XXXXXXX 100644
550
GIT binary patch
551
literal 112
552
zcmWIZ^baXu00LVle`k+i1*eDrX9XZ&1PX!JAex!M0Hgv8m>C3sGzdcgBZCA3T-xBj
553
Q0Zb)W9Hva*zW_`e0M!8s0RR91
554
555
literal 0
556
HcmV?d00001
557
558
--
559
2.25.1
560
561
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
The VIOT blob contains the following:
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180115182436.2066-3-f4bug@amsat.org
5
[000h 0000 4] Signature : "VIOT" [Virtual I/O Translation Table]
6
[004h 0004 4] Table Length : 00000058
7
[008h 0008 1] Revision : 00
8
[009h 0009 1] Checksum : 66
9
[00Ah 0010 6] Oem ID : "BOCHS "
10
[010h 0016 8] Oem Table ID : "BXPC "
11
[018h 0024 4] Oem Revision : 00000001
12
[01Ch 0028 4] Asl Compiler ID : "BXPC"
13
[020h 0032 4] Asl Compiler Revision : 00000001
14
15
[024h 0036 2] Node count : 0002
16
[026h 0038 2] Node offset : 0030
17
[028h 0040 8] Reserved : 0000000000000000
18
19
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
20
[031h 0049 1] Reserved : 00
21
[032h 0050 2] Length : 0010
22
23
[034h 0052 2] PCI Segment : 0000
24
[036h 0054 2] PCI BDF number : 0008
25
[038h 0056 8] Reserved : 0000000000000000
26
27
[040h 0064 1] Type : 01 [PCI Range]
28
[041h 0065 1] Reserved : 00
29
[042h 0066 2] Length : 0018
30
31
[044h 0068 4] Endpoint start : 00000000
32
[048h 0072 2] PCI Segment start : 0000
33
[04Ah 0074 2] PCI Segment end : 0000
34
[04Ch 0076 2] PCI BDF start : 0000
35
[04Eh 0078 2] PCI BDF end : 00FF
36
[050h 0080 2] Output node : 0030
37
[052h 0082 6] Reserved : 000000000000
38
39
Acked-by: Ani Sinha <ani@anisinha.ca>
40
Reviewed-by: Eric Auger <eric.auger@redhat.com>
41
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
42
Message-id: 20211210170415.583179-9-jean-philippe@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
44
---
8
include/hw/sd/sdhci.h | 2 --
45
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
9
hw/sd/sdhci.c | 2 --
46
tests/data/acpi/virt/VIOT | Bin 0 -> 88 bytes
10
2 files changed, 4 deletions(-)
47
2 files changed, 1 deletion(-)
11
48
12
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
49
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
13
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/sd/sdhci.h
51
--- a/tests/qtest/bios-tables-test-allowed-diff.h
15
+++ b/include/hw/sd/sdhci.h
52
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
16
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
53
@@ -1,2 +1 @@
17
54
/* List of comma-separated changed AML files to ignore */
18
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
55
-"tests/data/acpi/virt/VIOT",
19
QEMUTimer *transfer_timer;
56
diff --git a/tests/data/acpi/virt/VIOT b/tests/data/acpi/virt/VIOT
20
- qemu_irq eject_cb;
21
- qemu_irq ro_cb;
22
qemu_irq irq;
23
24
/* Registers cleared on reset */
25
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
26
index XXXXXXX..XXXXXXX 100644
57
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/sd/sdhci.c
58
GIT binary patch
28
+++ b/hw/sd/sdhci.c
59
literal 88
29
@@ -XXX,XX +XXX,XX @@ static void sdhci_uninitfn(SDHCIState *s)
60
zcmWIZ^bd((0D?3pe`k+i1*eDrX9XZ&1PX!JAexE60Hgv8m>C3sGzXN&z`)2L0cSHX
30
timer_free(s->insert_timer);
61
I{D-Rq0Q5fy0RR91
31
timer_del(s->transfer_timer);
62
32
timer_free(s->transfer_timer);
63
literal 0
33
- qemu_free_irq(s->eject_cb);
64
HcmV?d00001
34
- qemu_free_irq(s->ro_cb);
65
35
36
g_free(s->fifo_buffer);
37
s->fifo_buffer = NULL;
38
--
66
--
39
2.7.4
67
2.25.1
40
68
41
69
diff view generated by jsdifflib