[Qemu-devel] [PULL 00/24] target-arm queue
[Qemu-devel] [PULL 00/16] target-arm queue
1
More arm patches (mostly the SDHCI ones from Philippe)
1
The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
2
2
3
thanks
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
4
-- PMM
5
4
6
The following changes since commit f521eeee3bd060b460c99e605472b7e03967db43:
5
are available in the Git repository at:
7
6
8
Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180115' into staging (2018-01-15 13:17:47 +0000)
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
9
8
10
are available in the git repository at:
9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
11
10
12
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180116
11
tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
13
14
for you to fetch changes up to 60765b6ceeb4998a0d4220b3a53f1f185061da77:
15
16
sdhci: add a 'dma' property to the sysbus devices (2018-01-16 13:28:21 +0000)
17
12
18
----------------------------------------------------------------
13
----------------------------------------------------------------
19
target-arm queue:
14
target-arm queue:
20
* SDHCI: cleanups and minor bug fixes
15
* Fix coverity nit in int_to_float code
21
* target/arm: minor refactor preparatory to fp16 support
16
* Don't set Invalid for float-to-int(MAXINT)
22
* omap_ssd, ssi-sd, pl181, milkymist-memcard: reset the SD
17
* Fix fp_status_f16 tininess before rounding
23
card on controller reset (fixes migration failures)
18
* Add various missing insns from the v8.2-FP16 extension
24
* target/arm: Handle page table walk load failures correctly
19
* Fix sqrt_f16 exception raising
25
* hw/arm/virt: Add virt-2.12 machine type
20
* sdcard: Correct CRC16 offset in sd_function_switch()
26
* get_phys_addr_pmsav7: Support AP=0b111 for v7M
21
* tcg: Optionally log FPU state in TCG -d cpu logging
27
* hw/intc/armv7m: Support byte and halfword accesses to CFSR
28
22
29
----------------------------------------------------------------
23
----------------------------------------------------------------
30
Andrey Smirnov (1):
24
Alex Bennée (5):
31
sdhci: Implement write method of ACMD12ERRSTS register
25
fpu/softfloat: int_to_float ensure r fully initialised
26
target/arm: Implement FCMP for fp16
27
target/arm: Implement FCSEL for fp16
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
32
30
33
Peter Maydell (8):
31
Peter Maydell (3):
34
hw/intc/armv7m: Support byte and halfword accesses to CFSR
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
35
get_phys_addr_pmsav7: Support AP=0b111 for v7M
33
target/arm: Fix fp_status_f16 tininess before rounding
36
hw/arm/virt: Add virt-2.12 machine type
34
tcg: Optionally log FPU state in TCG -d cpu logging
37
target/arm: Handle page table walk load failures correctly
38
hw/sd/pl181: Reset SD card on controller reset
39
hw/sd/milkymist-memcard: Reset SD card on controller reset
40
hw/sd/ssi-sd: Reset SD card on controller reset
41
hw/sd/omap_mmc: Reset SD card on controller reset
42
35
43
Philippe Mathieu-Daudé (13):
36
Philippe Mathieu-Daudé (1):
44
sdhci: clean up includes
37
sdcard: Correct CRC16 offset in sd_function_switch()
45
sdhci: remove dead code
46
sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties
47
sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init()
48
sdhci: refactor common sysbus/pci realize() into sdhci_common_realize()
49
sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize()
50
sdhci: use qemu_log_mask(UNIMP) instead of fprintf()
51
sdhci: convert the DPRINT() calls into trace events
52
sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h"
53
sdhci: rename the SDHC_CAPAB register
54
sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only
55
sdhci: fix the PCI device, using the PCI address space for DMA
56
sdhci: add a 'dma' property to the sysbus devices
57
38
58
Richard Henderson (2):
39
Richard Henderson (7):
59
target/arm: Split out vfp_expand_imm
40
target/arm: Implement FMOV (general) for fp16
60
target/arm: Add fp16 support to vfp_expand_imm
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
42
target/arm: Implement FCVT (scalar, integer) for fp16
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
44
target/arm: Introduce and use read_fp_hreg
45
target/arm: Implement FP data-processing (2 source) for fp16
46
target/arm: Implement FP data-processing (3 source) for fp16
61
47
62
hw/sd/sdhci-internal.h | 7 +-
48
include/qemu/log.h | 1 +
63
include/hw/sd/sdhci.h | 19 +++-
49
target/arm/helper-a64.h | 2 +
64
target/arm/internals.h | 10 ++
50
target/arm/helper.h | 6 +
65
hw/arm/virt.c | 19 +++-
51
accel/tcg/cpu-exec.c | 9 +-
66
hw/intc/armv7m_nvic.c | 38 ++++---
52
fpu/softfloat.c | 6 +-
67
hw/sd/milkymist-memcard.c | 4 +
53
hw/sd/sd.c | 2 +-
68
hw/sd/omap_mmc.c | 14 ++-
54
target/arm/cpu.c | 2 +
69
hw/sd/pl181.c | 4 +
55
target/arm/helper-a64.c | 10 ++
70
hw/sd/sdhci.c | 266 +++++++++++++++++++++++++++------------------
56
target/arm/helper.c | 38 +++-
71
hw/sd/ssi-sd.c | 25 ++++-
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
72
target/arm/helper.c | 53 ++++++++-
58
util/log.c | 2 +
73
target/arm/op_helper.c | 7 +-
59
11 files changed, 428 insertions(+), 71 deletions(-)
74
target/arm/translate-a64.c | 49 ++++++---
75
hw/sd/trace-events | 14 +++
76
14 files changed, 362 insertions(+), 167 deletions(-)
77
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/24] hw/intc/armv7m: Support byte and halfword accesses to CFSR
Deleted patch
1
The Configurable Fault Status Register for ARMv7M and v8M is
2
supposed to be byte and halfword accessible, but we were only
3
implementing word accesses. Add support for the other access
4
sizes, which are used by the Zephyr RTOS.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reported-by: Andy Gross <andy.gross@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 1512742372-31517-1-git-send-email-peter.maydell@linaro.org
10
---
11
hw/intc/armv7m_nvic.c | 38 ++++++++++++++++++++++----------------
12
1 file changed, 22 insertions(+), 16 deletions(-)
13
14
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/armv7m_nvic.c
17
+++ b/hw/intc/armv7m_nvic.c
18
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
19
val |= (1 << 8);
20
}
21
return val;
22
- case 0xd28: /* Configurable Fault Status. */
23
- /* The BFSR bits [15:8] are shared between security states
24
- * and we store them in the NS copy
25
- */
26
- val = cpu->env.v7m.cfsr[attrs.secure];
27
- val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
28
- return val;
29
case 0xd2c: /* Hard Fault Status. */
30
return cpu->env.v7m.hfsr;
31
case 0xd30: /* Debug Fault Status. */
32
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
33
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
34
nvic_irq_update(s);
35
break;
36
- case 0xd28: /* Configurable Fault Status. */
37
- cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */
38
- if (attrs.secure) {
39
- /* The BFSR bits [15:8] are shared between security states
40
- * and we store them in the NS copy.
41
- */
42
- cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
43
- }
44
- break;
45
case 0xd2c: /* Hard Fault Status. */
46
cpu->env.v7m.hfsr &= ~value; /* W1C */
47
break;
48
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
49
val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
50
}
51
break;
52
+ case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
53
+ /* The BFSR bits [15:8] are shared between security states
54
+ * and we store them in the NS copy
55
+ */
56
+ val = s->cpu->env.v7m.cfsr[attrs.secure];
57
+ val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
58
+ val = extract32(val, (offset - 0xd28) * 8, size * 8);
59
+ break;
60
case 0xfe0 ... 0xfff: /* ID. */
61
if (offset & 3) {
62
val = 0;
63
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
64
}
65
nvic_irq_update(s);
66
return MEMTX_OK;
67
+ case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
68
+ /* All bits are W1C, so construct 32 bit value with 0s in
69
+ * the parts not written by the access size
70
+ */
71
+ value <<= ((offset - 0xd28) * 8);
72
+
73
+ s->cpu->env.v7m.cfsr[attrs.secure] &= ~value;
74
+ if (attrs.secure) {
75
+ /* The BFSR bits [15:8] are shared between security states
76
+ * and we store them in the NS copy.
77
+ */
78
+ s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
79
+ }
80
+ return MEMTX_OK;
81
}
82
if (size == 4) {
83
nvic_writel(s, offset, value, attrs);
84
--
85
2.7.4
86
87
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/24] get_phys_addr_pmsav7: Support AP=0b111 for v7M
Deleted patch
1
For PMSAv7, the v7A/R Arm ARM defines that setting AP to 0b111
2
is an UNPREDICTABLE reserved combination. However, for v7M
3
this value is documented as having the same behaviour as 0b110:
4
read-only for both privileged and unprivileged. Accept this
5
value on an M profile core rather than treating it as a guest
6
error and a no-access page.
7
1
8
Reported-by: Andy Gross <andy.gross@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 1512742402-31669-1-git-send-email-peter.maydell@linaro.org
12
---
13
target/arm/helper.c | 14 ++++++++++++++
14
1 file changed, 14 insertions(+)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
21
case 6:
22
*prot |= PAGE_READ | PAGE_EXEC;
23
break;
24
+ case 7:
25
+ /* for v7M, same as 6; for R profile a reserved value */
26
+ if (arm_feature(env, ARM_FEATURE_M)) {
27
+ *prot |= PAGE_READ | PAGE_EXEC;
28
+ break;
29
+ }
30
+ /* fall through */
31
default:
32
qemu_log_mask(LOG_GUEST_ERROR,
33
"DRACR[%d]: Bad value for AP bits: 0x%"
34
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
35
case 6:
36
*prot |= PAGE_READ | PAGE_EXEC;
37
break;
38
+ case 7:
39
+ /* for v7M, same as 6; for R profile a reserved value */
40
+ if (arm_feature(env, ARM_FEATURE_M)) {
41
+ *prot |= PAGE_READ | PAGE_EXEC;
42
+ break;
43
+ }
44
+ /* fall through */
45
default:
46
qemu_log_mask(LOG_GUEST_ERROR,
47
"DRACR[%d]: Bad value for AP bits: 0x%"
48
--
49
2.7.4
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/24] sdhci: Implement write method of ACMD12ERRSTS register
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
1
From: Andrey Smirnov <andrew.smirnov@gmail.com>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
4
later on so we might as well mirror that.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
7
Message-id: 20180115182436.2066-13-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
hw/sd/sdhci.c | 3 +++
11
fpu/softfloat.c | 2 +-
11
1 file changed, 3 insertions(+)
12
1 file changed, 1 insertion(+), 1 deletion(-)
12
13
13
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sdhci.c
16
--- a/fpu/softfloat.c
16
+++ b/hw/sd/sdhci.c
17
+++ b/fpu/softfloat.c
17
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
18
}
19
19
sdhci_update_irq(s);
20
static FloatParts int_to_float(int64_t a, float_status *status)
20
break;
21
{
21
+ case SDHC_ACMD12ERRSTS:
22
- FloatParts r;
22
+ MASKED_WRITE(s->acmd12errsts, mask, value);
23
+ FloatParts r = {};
23
+ break;
24
if (a == 0) {
24
25
r.cls = float_class_zero;
25
case SDHC_CAPAB:
26
r.sign = false;
26
case SDHC_CAPAB + 4:
27
--
27
--
28
2.7.4
28
2.17.0
29
29
30
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/24] hw/sd/pl181: Reset SD card on controller reset
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
1
Since pl181 is still using the legacy SD card API, the SD
1
In float-to-integer conversion, if the floating point input
2
card created by sd_init() is not plugged into any bus. This
2
converts exactly to the largest or smallest integer that
3
means that the controller has to reset it manually.
3
fits in to the result type, this is not an overflow.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
4
8
5
Failing to do this mostly didn't affect the guest since the
9
Fix the boundary case to take the right half of the if()
6
guest typically does a programmed SD card reset as part of
10
statements.
7
its SD controller driver initialization, but meant that
11
8
migration failed because it's only in sd_reset() that we
12
This fixes a regression from 2.11 introduced by the softfloat
9
set up the wpgrps_size field.
13
refactoring.
10
14
11
Cc: qemu-stable@nongnu.org
15
Cc: qemu-stable@nongnu.org
12
Fixes: https://bugs.launchpad.net/qemu/+bug/1739378
16
Fixes: ab52f973a50
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
16
Message-id: 1515506513-31961-2-git-send-email-peter.maydell@linaro.org
17
---
20
---
18
hw/sd/pl181.c | 4 ++++
21
fpu/softfloat.c | 4 ++--
19
1 file changed, 4 insertions(+)
22
1 file changed, 2 insertions(+), 2 deletions(-)
20
23
21
diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
22
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/sd/pl181.c
26
--- a/fpu/softfloat.c
24
+++ b/hw/sd/pl181.c
27
+++ b/fpu/softfloat.c
25
@@ -XXX,XX +XXX,XX @@ static void pl181_reset(DeviceState *d)
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
26
29
r = UINT64_MAX;
27
/* We can assume our GPIO outputs have been wired up now */
30
}
28
sd_set_cb(s->card, s->cardstatus[0], s->cardstatus[1]);
31
if (p.sign) {
29
+ /* Since we're still using the legacy SD API the card is not plugged
32
- if (r < -(uint64_t) min) {
30
+ * into any bus, and we must reset it manually.
33
+ if (r <= -(uint64_t) min) {
31
+ */
34
return -r;
32
+ device_reset(DEVICE(s->card));
35
} else {
33
}
36
s->float_exception_flags = orig_flags | float_flag_invalid;
34
37
return min;
35
static void pl181_init(Object *obj)
38
}
39
} else {
40
- if (r < max) {
41
+ if (r <= max) {
42
return r;
43
} else {
44
s->float_exception_flags = orig_flags | float_flag_invalid;
36
--
45
--
37
2.7.4
46
2.17.0
38
47
39
48
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/24] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
In commit d81ce0ef2c4f105 we added an extra float_status field
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
3
by setting it to float_tininess_before_rounding. This currently
4
will only cause problems for the new V8_FP16 feature, since the
5
float-to-float conversion code doesn't use it yet. The effect
6
would be that we failed to set the Underflow IEEE exception flag
7
in all the cases where we should.
2
8
3
running qtests:
9
Add the missing initialization.
4
10
5
$ make check-qtest-arm
11
Fixes: d81ce0ef2c4f105
6
GTESTER check-qtest-arm
12
Cc: qemu-stable@nongnu.org
7
SDHC rd_4b @0x44 not implemented
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
SDHC wr_4b @0x40 <- 0x89abcdef not implemented
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
SDHC wr_4b @0x44 <- 0x01234567 not implemented
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
17
---
18
target/arm/cpu.c | 2 ++
19
1 file changed, 2 insertions(+)
10
20
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
13
Message-id: 20180115182436.2066-12-f4bug@amsat.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/sd/sdhci.h | 4 ++--
17
hw/sd/sdhci.c | 23 +++++++++++++++++++----
18
2 files changed, 21 insertions(+), 6 deletions(-)
19
20
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
21
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/sd/sdhci.h
23
--- a/target/arm/cpu.c
23
+++ b/include/hw/sd/sdhci.h
24
+++ b/target/arm/cpu.c
24
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
25
uint64_t admasysaddr; /* ADMA System Address Register */
26
&env->vfp.fp_status);
26
27
set_float_detect_tininess(float_tininess_before_rounding,
27
/* Read-only registers */
28
&env->vfp.standard_fp_status);
28
- uint32_t capareg; /* Capabilities Register */
29
+ set_float_detect_tininess(float_tininess_before_rounding,
29
- uint32_t maxcurr; /* Maximum Current Capabilities Register */
30
+ &env->vfp.fp_status_f16);
30
+ uint64_t capareg; /* Capabilities Register */
31
#ifndef CONFIG_USER_ONLY
31
+ uint64_t maxcurr; /* Maximum Current Capabilities Register */
32
if (kvm_enabled()) {
32
33
kvm_arm_reset_vcpu(cpu);
33
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
34
uint32_t buf_maxsz;
35
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/sd/sdhci.c
38
+++ b/hw/sd/sdhci.c
39
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
40
ret = s->acmd12errsts;
41
break;
42
case SDHC_CAPAB:
43
- ret = s->capareg;
44
+ ret = (uint32_t)s->capareg;
45
+ break;
46
+ case SDHC_CAPAB + 4:
47
+ ret = (uint32_t)(s->capareg >> 32);
48
break;
49
case SDHC_MAXCURR:
50
- ret = s->maxcurr;
51
+ ret = (uint32_t)s->maxcurr;
52
+ break;
53
+ case SDHC_MAXCURR + 4:
54
+ ret = (uint32_t)(s->maxcurr >> 32);
55
break;
56
case SDHC_ADMAERR:
57
ret = s->admaerr;
58
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
59
}
60
sdhci_update_irq(s);
61
break;
62
+
63
+ case SDHC_CAPAB:
64
+ case SDHC_CAPAB + 4:
65
+ case SDHC_MAXCURR:
66
+ case SDHC_MAXCURR + 4:
67
+ qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
68
+ " <- 0x%08x read-only\n", size, offset, value >> shift);
69
+ break;
70
+
71
default:
72
qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
73
"not implemented\n", size, offset, value >> shift);
74
@@ -XXX,XX +XXX,XX @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
75
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
76
/* Capabilities registers provide information on supported features
77
* of this specific host controller implementation */ \
78
- DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
79
- DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)
80
+ DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
81
+ DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
82
83
static void sdhci_initfn(SDHCIState *s)
84
{
85
--
34
--
86
2.7.4
35
2.17.0
87
36
88
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/24] hw/sd/ssi-sd: Reset SD card on controller reset
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
1
Since ssi-sd is still using the legacy SD card API, the SD
1
From: Richard Henderson <richard.henderson@linaro.org>
2
card created by sd_init() is not plugged into any bus. This
3
means that the controller has to reset it manually.
4
2
5
Failing to do this mostly didn't affect the guest since the
3
Adding the fp16 moves to/from general registers.
6
guest typically does a programmed SD card reset as part of
7
its SD controller driver initialization, but meant that
8
migration failed because it's only in sd_reset() that we
9
set up the wpgrps_size field.
10
11
In the case of sd-ssi, we have to implement an entire
12
reset function since there wasn't one previously, and
13
that requires a QOM cast macro that got omitted when this
14
device was QOMified.
15
4
16
Cc: qemu-stable@nongnu.org
5
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
19
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 1515506513-31961-4-git-send-email-peter.maydell@linaro.org
21
---
11
---
22
hw/sd/ssi-sd.c | 25 +++++++++++++++++++++++--
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
23
1 file changed, 23 insertions(+), 2 deletions(-)
13
1 file changed, 21 insertions(+)
24
14
25
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
26
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/sd/ssi-sd.c
17
--- a/target/arm/translate-a64.c
28
+++ b/hw/sd/ssi-sd.c
18
+++ b/target/arm/translate-a64.c
29
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
30
SDState *sd;
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
31
} ssi_sd_state;
21
clear_vec_high(s, true, rd);
32
22
break;
33
+#define TYPE_SSI_SD "ssi-sd"
23
+ case 3:
34
+#define SSI_SD(obj) OBJECT_CHECK(ssi_sd_state, (obj), TYPE_SSI_SD)
24
+ /* 16 bit */
35
+
25
+ tmp = tcg_temp_new_i64();
36
/* State word bits. */
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
37
#define SSI_SDR_LOCKED 0x0001
27
+ write_fp_dreg(s, rd, tmp);
38
#define SSI_SDR_WP_ERASE 0x0002
28
+ tcg_temp_free_i64(tmp);
39
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSISlave *d, Error **errp)
29
+ break;
40
ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
30
+ default:
41
DriveInfo *dinfo;
31
+ g_assert_not_reached();
42
32
}
43
- s->mode = SSI_SD_CMD;
33
} else {
44
/* FIXME use a qdev drive property instead of drive_get_next() */
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
45
dinfo = drive_get_next(IF_SD);
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
46
s->sd = sd_init(dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, true);
36
/* 64 bits from top half */
47
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_realize(SSISlave *d, Error **errp)
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
38
break;
39
+ case 3:
40
+ /* 16 bit */
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
42
+ break;
43
+ default:
44
+ g_assert_not_reached();
45
}
48
}
46
}
49
}
47
}
50
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
51
+static void ssi_sd_reset(DeviceState *dev)
49
case 0xa: /* 64 bit */
52
+{
50
case 0xd: /* 64 bit to top half of quad */
53
+ ssi_sd_state *s = SSI_SD(dev);
51
break;
54
+
52
+ case 0x6: /* 16-bit float, 32-bit int */
55
+ s->mode = SSI_SD_CMD;
53
+ case 0xe: /* 16-bit float, 64-bit int */
56
+ s->cmd = 0;
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
57
+ memset(s->cmdarg, 0, sizeof(s->cmdarg));
55
+ break;
58
+ memset(s->response, 0, sizeof(s->response));
56
+ }
59
+ s->arglen = 0;
57
+ /* fallthru */
60
+ s->response_pos = 0;
58
default:
61
+ s->stopping = 0;
59
/* all other sf/type/rmode combinations are invalid */
62
+
60
unallocated_encoding(s);
63
+ /* Since we're still using the legacy SD API the card is not plugged
64
+ * into any bus, and we must reset it manually.
65
+ */
66
+ device_reset(DEVICE(s->sd));
67
+}
68
+
69
static void ssi_sd_class_init(ObjectClass *klass, void *data)
70
{
71
DeviceClass *dc = DEVICE_CLASS(klass);
72
@@ -XXX,XX +XXX,XX @@ static void ssi_sd_class_init(ObjectClass *klass, void *data)
73
k->transfer = ssi_sd_transfer;
74
k->cs_polarity = SSI_CS_LOW;
75
dc->vmsd = &vmstate_ssi_sd;
76
+ dc->reset = ssi_sd_reset;
77
}
78
79
static const TypeInfo ssi_sd_info = {
80
- .name = "ssi-sd",
81
+ .name = TYPE_SSI_SD,
82
.parent = TYPE_SSI_SLAVE,
83
.instance_size = sizeof(ssi_sd_state),
84
.class_init = ssi_sd_class_init,
85
--
61
--
86
2.7.4
62
2.17.0
87
63
88
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/24] sdhci: rename the SDHC_CAPAB register
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
No sense in emitting code after the exception.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180115182436.2066-11-f4bug@amsat.org
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/sd/sdhci-internal.h | 2 +-
11
target/arm/translate-a64.c | 2 +-
9
hw/sd/sdhci.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
13
12
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/sdhci-internal.h
16
--- a/target/arm/translate-a64.c
15
+++ b/hw/sd/sdhci-internal.h
17
+++ b/target/arm/translate-a64.c
16
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
17
#define SDHC_ACMD12ERRSTS 0x3C
19
default:
18
20
/* all other sf/type/rmode combinations are invalid */
19
/* HWInit Capabilities Register 0x05E80080 */
21
unallocated_encoding(s);
20
-#define SDHC_CAPAREG 0x40
22
- break;
21
+#define SDHC_CAPAB 0x40
23
+ return;
22
#define SDHC_CAN_DO_DMA 0x00400000
24
}
23
#define SDHC_CAN_DO_ADMA2 0x00080000
25
24
#define SDHC_CAN_DO_ADMA1 0x00100000
26
if (!fp_access_check(s)) {
25
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/sd/sdhci.c
28
+++ b/hw/sd/sdhci.c
29
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
30
case SDHC_ACMD12ERRSTS:
31
ret = s->acmd12errsts;
32
break;
33
- case SDHC_CAPAREG:
34
+ case SDHC_CAPAB:
35
ret = s->capareg;
36
break;
37
case SDHC_MAXCURR:
38
--
27
--
39
2.7.4
28
2.17.0
40
29
41
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/24] target/arm: Handle page table walk load failures correctly
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
1
Instead of ignoring the response from address_space_ld*()
1
From: Richard Henderson <richard.henderson@linaro.org>
2
(indicating an attempt to read a page table descriptor from
2
3
an invalid physical address), use it to report the failure
3
Cc: qemu-stable@nongnu.org
4
correctly.
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Since this is another couple of locations where we need to
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
decide the value of the ARMMMUFaultInfo ea bit based on a
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
8
MemTxResult, we factor out that operation into a helper
9
function.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
target/arm/internals.h | 10 ++++++++++
10
target/arm/helper.h | 6 +++
14
target/arm/helper.c | 39 ++++++++++++++++++++++++++++++++++-----
11
target/arm/helper.c | 38 ++++++++++++++-
15
target/arm/op_helper.c | 7 +------
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
16
3 files changed, 45 insertions(+), 11 deletions(-)
13
3 files changed, 122 insertions(+), 18 deletions(-)
17
14
18
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/internals.h
17
--- a/target/arm/helper.h
21
+++ b/target/arm/internals.h
18
+++ b/target/arm/helper.h
22
@@ -XXX,XX +XXX,XX @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
23
return fsc;
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
24
}
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
25
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
26
+static inline bool arm_extabort_type(MemTxResult result)
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
27
+{
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
28
+ /* The EA bit in syndromes and fault status registers is an
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
29
+ * IMPDEF classification of external aborts. ARM implementations
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
30
+ * usually use this to indicate AXI bus Decode error (0) or
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
31
+ * Slave error (1); in QEMU we follow that.
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
32
+ */
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
33
+ return result != MEMTX_DECODE_ERROR;
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
34
+}
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
35
+
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
36
/* Do a page table walk and add page to TLB if possible */
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
37
bool arm_tlb_fill(CPUState *cpu, vaddr address,
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
38
MMUAccessType access_type, int mmu_idx,
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
36
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
41
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
42
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
44
ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
44
#undef VFP_CONV_FIX_A64
45
&txattrs, &s2prot, &s2size, fi, NULL);
45
46
if (ret) {
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
47
+ assert(fi->type != ARMFault_None);
47
- * Therefore we convert to f64 (which does not round), scale,
48
fi->s2addr = addr;
48
- * and then convert f64 to f16 (which may round).
49
fi->stage2 = true;
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
50
fi->s1ptw = true;
50
+ * vice versa for conversion to integer.
51
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
51
+ *
52
ARMCPU *cpu = ARM_CPU(cs);
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
53
CPUARMState *env = &cpu->env;
53
+ * For 64-bit integers, any integer that would cause rounding will also
54
MemTxAttrs attrs = {};
54
+ * overflow to f16 infinity, so there is no double rounding problem.
55
+ MemTxResult result = MEMTX_OK;
55
*/
56
AddressSpace *as;
56
57
+ uint32_t data;
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
58
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
59
attrs.secure = is_secure;
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
60
as = arm_addressspace(cs, attrs);
60
}
61
@@ -XXX,XX +XXX,XX @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
61
62
return 0;
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
63
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
65
+}
66
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
68
+{
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
70
+}
71
+
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
73
{
74
if (unlikely(float16_is_any_nan(f))) {
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
77
}
78
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
80
+{
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
82
+}
83
+
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
85
+{
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
87
+}
88
+
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
90
+{
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
92
+}
93
+
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
95
+{
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
97
+}
98
+
99
/* Set the current fp rounding mode and return the old one.
100
* The argument is a softfloat float_round_ value.
101
*/
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/target/arm/translate-a64.c
105
+++ b/target/arm/translate-a64.c
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
107
bool itof, int rmode, int scale, int sf, int type)
108
{
109
bool is_signed = !(opcode & 1);
110
- bool is_double = type;
111
TCGv_ptr tcg_fpstatus;
112
- TCGv_i32 tcg_shift;
113
+ TCGv_i32 tcg_shift, tcg_single;
114
+ TCGv_i64 tcg_double;
115
116
- tcg_fpstatus = get_fpstatus_ptr(false);
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
118
119
tcg_shift = tcg_const_i32(64 - scale);
120
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
122
tcg_int = tcg_extend;
123
}
124
125
- if (is_double) {
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
127
+ switch (type) {
128
+ case 1: /* float64 */
129
+ tcg_double = tcg_temp_new_i64();
130
if (is_signed) {
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
63
}
240
}
64
if (regime_translation_big_endian(env, mmu_idx)) {
241
65
- return address_space_ldl_be(as, addr, attrs, NULL);
242
tcg_temp_free_ptr(tcg_fpstatus);
66
+ data = address_space_ldl_be(as, addr, attrs, &result);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
67
} else {
244
/* actual FP conversions */
68
- return address_space_ldl_le(as, addr, attrs, NULL);
245
bool itof = extract32(opcode, 1, 1);
69
+ data = address_space_ldl_le(as, addr, attrs, &result);
246
70
}
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
71
+ if (result == MEMTX_OK) {
248
+ if (rmode != 0 && opcode > 1) {
72
+ return data;
249
+ unallocated_encoding(s);
73
+ }
250
+ return;
74
+ fi->type = ARMFault_SyncExternalOnWalk;
75
+ fi->ea = arm_extabort_type(result);
76
+ return 0;
77
}
78
79
static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
80
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
81
ARMCPU *cpu = ARM_CPU(cs);
82
CPUARMState *env = &cpu->env;
83
MemTxAttrs attrs = {};
84
+ MemTxResult result = MEMTX_OK;
85
AddressSpace *as;
86
+ uint32_t data;
87
88
attrs.secure = is_secure;
89
as = arm_addressspace(cs, attrs);
90
@@ -XXX,XX +XXX,XX @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
91
return 0;
92
}
93
if (regime_translation_big_endian(env, mmu_idx)) {
94
- return address_space_ldq_be(as, addr, attrs, NULL);
95
+ data = address_space_ldq_be(as, addr, attrs, &result);
96
} else {
97
- return address_space_ldq_le(as, addr, attrs, NULL);
98
+ data = address_space_ldq_le(as, addr, attrs, &result);
99
+ }
100
+ if (result == MEMTX_OK) {
101
+ return data;
102
}
103
+ fi->type = ARMFault_SyncExternalOnWalk;
104
+ fi->ea = arm_extabort_type(result);
105
+ return 0;
106
}
107
108
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
109
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
110
}
111
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
112
mmu_idx, fi);
113
+ if (fi->type != ARMFault_None) {
114
+ goto do_fault;
115
+ }
116
type = (desc & 3);
117
domain = (desc >> 5) & 0x0f;
118
if (regime_el(env, mmu_idx) == 1) {
119
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
120
}
121
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
122
mmu_idx, fi);
123
+ if (fi->type != ARMFault_None) {
124
+ goto do_fault;
125
+ }
251
+ }
126
switch (desc & 3) {
252
+ switch (type) {
127
case 0: /* Page translation fault. */
253
+ case 0: /* float32 */
128
fi->type = ARMFault_Translation;
254
+ case 1: /* float64 */
129
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
255
+ break;
130
}
256
+ case 3: /* float16 */
131
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
132
mmu_idx, fi);
258
+ break;
133
+ if (fi->type != ARMFault_None) {
259
+ }
134
+ goto do_fault;
260
+ /* fallthru */
135
+ }
261
+ default:
136
type = (desc & 3);
262
unallocated_encoding(s);
137
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
263
return;
138
/* Section translation fault, or attempt to use the encoding
264
}
139
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
140
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
141
desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
142
mmu_idx, fi);
143
+ if (fi->type != ARMFault_None) {
144
+ goto do_fault;
145
+ }
146
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
147
switch (desc & 3) {
148
case 0: /* Page translation fault. */
149
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
150
descaddr &= ~7ULL;
151
nstable = extract32(tableattrs, 4, 1);
152
descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi);
153
- if (fi->s1ptw) {
154
+ if (fi->type != ARMFault_None) {
155
goto do_fault;
156
}
157
158
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
159
index XXXXXXX..XXXXXXX 100644
160
--- a/target/arm/op_helper.c
161
+++ b/target/arm/op_helper.c
162
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
163
/* now we have a real cpu fault */
164
cpu_restore_state(cs, retaddr);
165
166
- /* The EA bit in syndromes and fault status registers is an
167
- * IMPDEF classification of external aborts. ARM implementations
168
- * usually use this to indicate AXI bus Decode error (0) or
169
- * Slave error (1); in QEMU we follow that.
170
- */
171
- fi.ea = (response != MEMTX_DECODE_ERROR);
172
+ fi.ea = arm_extabort_type(response);
173
fi.type = ARMFault_SyncExternal;
174
deliver_fault(cpu, addr, access_type, mmu_idx, &fi);
175
}
176
--
265
--
177
2.7.4
266
2.17.0
178
267
179
268
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/24] sdhci: fix the PCI device, using the PCI address space for DMA
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
While SysBus devices can use the get_system_memory() address space,
3
Cc: qemu-stable@nongnu.org
4
PCI devices should use the bus master address space for DMA.
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20180115182436.2066-14-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
include/hw/sd/sdhci.h | 1 +
10
target/arm/translate-a64.c | 17 +++++++++++++++--
13
hw/sd/sdhci.c | 29 +++++++++++++++--------------
11
1 file changed, 15 insertions(+), 2 deletions(-)
14
2 files changed, 16 insertions(+), 14 deletions(-)
15
12
16
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/sd/sdhci.h
15
--- a/target/arm/translate-a64.c
19
+++ b/include/hw/sd/sdhci.h
16
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
21
/*< public >*/
18
bool sf = extract32(insn, 31, 1);
22
SDBus sdbus;
19
bool itof;
23
MemoryRegion iomem;
20
24
+ AddressSpace *dma_as;
21
- if (sbit || (type > 1)
25
22
- || (!sf && scale < 32)) {
26
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
23
+ if (sbit || (!sf && scale < 32)) {
27
QEMUTimer *transfer_timer;
24
+ unallocated_encoding(s);
28
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
25
+ return;
29
index XXXXXXX..XXXXXXX 100644
26
+ }
30
--- a/hw/sd/sdhci.c
27
+
31
+++ b/hw/sd/sdhci.c
28
+ switch (type) {
32
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
29
+ case 0: /* float32 */
33
s->blkcnt--;
30
+ case 1: /* float64 */
34
}
31
+ break;
35
}
32
+ case 3: /* float16 */
36
- dma_memory_write(&address_space_memory, s->sdmasysad,
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
37
+ dma_memory_write(s->dma_as, s->sdmasysad,
34
+ break;
38
&s->fifo_buffer[begin], s->data_count - begin);
35
+ }
39
s->sdmasysad += s->data_count - begin;
36
+ /* fallthru */
40
if (s->data_count == block_size) {
37
+ default:
41
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
38
unallocated_encoding(s);
42
s->data_count = block_size;
43
boundary_count -= block_size - begin;
44
}
45
- dma_memory_read(&address_space_memory, s->sdmasysad,
46
+ dma_memory_read(s->dma_as, s->sdmasysad,
47
&s->fifo_buffer[begin], s->data_count - begin);
48
s->sdmasysad += s->data_count - begin;
49
if (s->data_count == block_size) {
50
@@ -XXX,XX +XXX,XX @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s)
51
for (n = 0; n < datacnt; n++) {
52
s->fifo_buffer[n] = sdbus_read_data(&s->sdbus);
53
}
54
- dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer,
55
- datacnt);
56
+ dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
57
} else {
58
- dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer,
59
- datacnt);
60
+ dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt);
61
for (n = 0; n < datacnt; n++) {
62
sdbus_write_data(&s->sdbus, s->fifo_buffer[n]);
63
}
64
@@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
65
hwaddr entry_addr = (hwaddr)s->admasysaddr;
66
switch (SDHC_DMA_TYPE(s->hostctl)) {
67
case SDHC_CTRL_ADMA2_32:
68
- dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2,
69
+ dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2,
70
sizeof(adma2));
71
adma2 = le64_to_cpu(adma2);
72
/* The spec does not specify endianness of descriptor table.
73
@@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
74
dscr->incr = 8;
75
break;
76
case SDHC_CTRL_ADMA1_32:
77
- dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1,
78
+ dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1,
79
sizeof(adma1));
80
adma1 = le32_to_cpu(adma1);
81
dscr->addr = (hwaddr)(adma1 & 0xFFFFF000);
82
@@ -XXX,XX +XXX,XX @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
83
}
84
break;
85
case SDHC_CTRL_ADMA2_64:
86
- dma_memory_read(&address_space_memory, entry_addr,
87
+ dma_memory_read(s->dma_as, entry_addr,
88
(uint8_t *)(&dscr->attr), 1);
89
- dma_memory_read(&address_space_memory, entry_addr + 2,
90
+ dma_memory_read(s->dma_as, entry_addr + 2,
91
(uint8_t *)(&dscr->length), 2);
92
dscr->length = le16_to_cpu(dscr->length);
93
- dma_memory_read(&address_space_memory, entry_addr + 4,
94
+ dma_memory_read(s->dma_as, entry_addr + 4,
95
(uint8_t *)(&dscr->addr), 8);
96
dscr->attr = le64_to_cpu(dscr->attr);
97
dscr->attr &= 0xfffffff8;
98
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
99
s->data_count = block_size;
100
length -= block_size - begin;
101
}
102
- dma_memory_write(&address_space_memory, dscr.addr,
103
+ dma_memory_write(s->dma_as, dscr.addr,
104
&s->fifo_buffer[begin],
105
s->data_count - begin);
106
dscr.addr += s->data_count - begin;
107
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
108
s->data_count = block_size;
109
length -= block_size - begin;
110
}
111
- dma_memory_read(&address_space_memory, dscr.addr,
112
+ dma_memory_read(s->dma_as, dscr.addr,
113
&s->fifo_buffer[begin],
114
s->data_count - begin);
115
dscr.addr += s->data_count - begin;
116
@@ -XXX,XX +XXX,XX @@ static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
117
dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
118
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
119
s->irq = pci_allocate_irq(dev);
120
- pci_register_bar(dev, 0, 0, &s->iomem);
121
+ s->dma_as = pci_get_address_space(dev);
122
+ pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem);
123
}
124
125
static void sdhci_pci_exit(PCIDevice *dev)
126
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
127
return;
39
return;
128
}
40
}
129
130
+ s->dma_as = &address_space_memory;
131
+
132
sysbus_init_irq(sbd, &s->irq);
133
sysbus_init_mmio(sbd, &s->iomem);
134
}
135
--
41
--
136
2.7.4
42
2.17.0
137
43
138
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/24] sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize()
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Cc: qemu-stable@nongnu.org
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20180115182436.2066-7-f4bug@amsat.org
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
9
---
8
hw/sd/sdhci.c | 22 ++++++++++++++++++++++
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
9
1 file changed, 22 insertions(+)
11
1 file changed, 14 insertions(+), 16 deletions(-)
10
12
11
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sdhci.c
15
--- a/target/arm/translate-a64.c
14
+++ b/hw/sd/sdhci.c
16
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
16
#include "qemu/bitops.h"
18
return v;
17
#include "hw/sd/sdhci.h"
18
#include "sdhci-internal.h"
19
+#include "qapi/error.h"
20
#include "qemu/log.h"
21
22
/* host controller debug messages */
23
@@ -XXX,XX +XXX,XX @@ static void sdhci_common_realize(SDHCIState *s, Error **errp)
24
SDHC_REGISTERS_MAP_SIZE);
25
}
19
}
26
20
27
+static void sdhci_common_unrealize(SDHCIState *s, Error **errp)
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
28
+{
22
+{
29
+ /* This function is expected to be called only once for each class:
23
+ TCGv_i32 v = tcg_temp_new_i32();
30
+ * - SysBus: via DeviceClass->unrealize(),
24
+
31
+ * - PCI: via PCIDeviceClass->exit().
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
32
+ * However to avoid double-free and/or use-after-free we still nullify
26
+ return v;
33
+ * this variable (better safe than sorry!). */
34
+ g_free(s->fifo_buffer);
35
+ s->fifo_buffer = NULL;
36
+}
27
+}
37
+
28
+
38
static bool sdhci_pending_insert_vmstate_needed(void *opaque)
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
30
* If SVE is not enabled, then there are only 128 bits in the vector.
31
*/
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
39
{
34
{
40
SDHCIState *s = opaque;
35
TCGv_ptr fpst = NULL;
41
@@ -XXX,XX +XXX,XX @@ static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
42
static void sdhci_pci_exit(PCIDevice *dev)
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
43
{
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
44
SDHCIState *s = PCI_SDHCI(dev);
39
45
+
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
46
+ sdhci_common_unrealize(s, &error_abort);
41
-
47
sdhci_uninitfn(s);
42
switch (opcode) {
48
}
43
case 0x0: /* FMOV */
49
44
tcg_gen_mov_i32(tcg_res, tcg_op);
50
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
51
sysbus_init_mmio(sbd, &s->iomem);
46
tcg_temp_free_i64(tcg_op2);
52
}
47
tcg_temp_free_i64(tcg_res);
53
48
} else {
54
+static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp)
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
55
+{
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
56
+ SDHCIState *s = SYSBUS_SDHCI(dev);
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
57
+
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
58
+ sdhci_common_unrealize(s, &error_abort);
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
59
+}
54
60
+
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
61
static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
62
{
57
-
63
DeviceClass *dc = DEVICE_CLASS(klass);
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
64
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
65
dc->props = sdhci_sysbus_properties;
60
66
dc->realize = sdhci_sysbus_realize;
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
67
+ dc->unrealize = sdhci_sysbus_unrealize;
62
68
63
fpst = get_fpstatus_ptr(true);
69
sdhci_common_class_init(klass, data);
64
70
}
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
79
80
if (is_scalar) {
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
84
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
86
-
87
switch (fpop) {
88
case 0x1a: /* FCVTNS */
89
case 0x1b: /* FCVTMS */
71
--
90
--
72
2.7.4
91
2.17.0
73
92
74
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/24] target/arm: Split out vfp_expand_imm
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 binary operations.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
5
Message-id: 20180110063337.21538-2-richard.henderson@linaro.org
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
target/arm/translate-a64.c | 44 ++++++++++++++++++++++++++++----------------
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
9
1 file changed, 28 insertions(+), 16 deletions(-)
13
1 file changed, 65 insertions(+)
10
14
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
16
}
20
tcg_temp_free_i64(tcg_res);
17
}
21
}
18
22
19
+/* The imm8 encodes the sign bit, enough bits to represent an exponent in
23
+/* Floating-point data-processing (2 source) - half precision */
20
+ * the range 01....1xx to 10....0xx, and the most significant 4 bits of
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
21
+ * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
25
+ int rd, int rn, int rm)
22
+ */
23
+static uint64_t vfp_expand_imm(int size, uint8_t imm8)
24
+{
26
+{
25
+ uint64_t imm;
27
+ TCGv_i32 tcg_op1;
28
+ TCGv_i32 tcg_op2;
29
+ TCGv_i32 tcg_res;
30
+ TCGv_ptr fpst;
26
+
31
+
27
+ switch (size) {
32
+ tcg_res = tcg_temp_new_i32();
28
+ case MO_64:
33
+ fpst = get_fpstatus_ptr(true);
29
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
34
+ tcg_op1 = read_fp_hreg(s, rn);
30
+ (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
35
+ tcg_op2 = read_fp_hreg(s, rm);
31
+ extract32(imm8, 0, 6);
36
+
32
+ imm <<= 48;
37
+ switch (opcode) {
38
+ case 0x0: /* FMUL */
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
33
+ break;
40
+ break;
34
+ case MO_32:
41
+ case 0x1: /* FDIV */
35
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
36
+ (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
43
+ break;
37
+ (extract32(imm8, 0, 6) << 3);
44
+ case 0x2: /* FADD */
38
+ imm <<= 16;
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
46
+ break;
47
+ case 0x3: /* FSUB */
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
49
+ break;
50
+ case 0x4: /* FMAX */
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
52
+ break;
53
+ case 0x5: /* FMIN */
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
55
+ break;
56
+ case 0x6: /* FMAXNM */
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
58
+ break;
59
+ case 0x7: /* FMINNM */
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
61
+ break;
62
+ case 0x8: /* FNMUL */
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
39
+ break;
65
+ break;
40
+ default:
66
+ default:
41
+ g_assert_not_reached();
67
+ g_assert_not_reached();
42
+ }
68
+ }
43
+ return imm;
69
+
70
+ write_fp_sreg(s, rd, tcg_res);
71
+
72
+ tcg_temp_free_ptr(fpst);
73
+ tcg_temp_free_i32(tcg_op1);
74
+ tcg_temp_free_i32(tcg_op2);
75
+ tcg_temp_free_i32(tcg_res);
44
+}
76
+}
45
+
77
+
46
/* Floating point immediate
78
/* Floating point data-processing (2 source)
47
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
48
* +---+---+---+-----------+------+---+------------+-------+------+------+
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
49
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
50
return;
82
}
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
84
break;
85
+ case 3:
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
87
+ unallocated_encoding(s);
88
+ return;
89
+ }
90
+ if (!fp_access_check(s)) {
91
+ return;
92
+ }
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
94
+ break;
95
default:
96
unallocated_encoding(s);
51
}
97
}
52
53
- /* The imm8 encodes the sign bit, enough bits to represent
54
- * an exponent in the range 01....1xx to 10....0xx,
55
- * and the most significant 4 bits of the mantissa; see
56
- * VFPExpandImm() in the v8 ARM ARM.
57
- */
58
- if (is_double) {
59
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
60
- (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
61
- extract32(imm8, 0, 6);
62
- imm <<= 48;
63
- } else {
64
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
65
- (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
66
- (extract32(imm8, 0, 6) << 3);
67
- imm <<= 16;
68
- }
69
+ imm = vfp_expand_imm(MO_32 + is_double, imm8);
70
71
tcg_res = tcg_const_i64(imm);
72
write_fp_dreg(s, rd, tcg_res);
73
--
98
--
74
2.7.4
99
2.17.0
75
100
76
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/24] target/arm: Add fp16 support to vfp_expand_imm
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 fma operations.
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
5
Message-id: 20180110063337.21538-3-richard.henderson@linaro.org
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
11
---
8
target/arm/translate-a64.c | 5 +++++
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
9
1 file changed, 5 insertions(+)
13
1 file changed, 48 insertions(+)
10
14
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate-a64.c
14
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate-a64.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t vfp_expand_imm(int size, uint8_t imm8)
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
16
(extract32(imm8, 0, 6) << 3);
20
tcg_temp_free_i64(tcg_res);
17
imm <<= 16;
21
}
22
23
+/* Floating-point data-processing (3 source) - half precision */
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
25
+ int rd, int rn, int rm, int ra)
26
+{
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
30
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
32
+ tcg_op2 = read_fp_hreg(s, rm);
33
+ tcg_op3 = read_fp_hreg(s, ra);
34
+
35
+ /* These are fused multiply-add, and must be done as one
36
+ * floating point operation with no rounding between the
37
+ * multiplication and addition steps.
38
+ * NB that doing the negations here as separate steps is
39
+ * correct : an input NaN should come out with its sign bit
40
+ * flipped if it is a negated-input.
41
+ */
42
+ if (o1 == true) {
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
44
+ }
45
+
46
+ if (o0 != o1) {
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
48
+ }
49
+
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
51
+
52
+ write_fp_sreg(s, rd, tcg_res);
53
+
54
+ tcg_temp_free_ptr(fpst);
55
+ tcg_temp_free_i32(tcg_op1);
56
+ tcg_temp_free_i32(tcg_op2);
57
+ tcg_temp_free_i32(tcg_op3);
58
+ tcg_temp_free_i32(tcg_res);
59
+}
60
+
61
/* Floating point data-processing (3 source)
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
65
}
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
18
break;
67
break;
19
+ case MO_16:
68
+ case 3:
20
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
21
+ (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
70
+ unallocated_encoding(s);
22
+ (extract32(imm8, 0, 6) << 6);
71
+ return;
72
+ }
73
+ if (!fp_access_check(s)) {
74
+ return;
75
+ }
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
23
+ break;
77
+ break;
24
default:
78
default:
25
g_assert_not_reached();
79
unallocated_encoding(s);
26
}
80
}
27
--
81
--
28
2.7.4
82
2.17.0
29
83
30
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/24] sdhci: refactor common sysbus/pci realize() into sdhci_common_realize()
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
These where missed out from the rest of the half-precision work.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180115182436.2066-6-f4bug@amsat.org
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
11
[rth: Diagnose lack of FP16 before fp_access_check]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
14
---
8
hw/sd/sdhci.c | 30 +++++++++++++++++++++---------
15
target/arm/helper-a64.h | 2 +
9
1 file changed, 21 insertions(+), 9 deletions(-)
16
target/arm/helper-a64.c | 10 +++++
10
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
11
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sdhci.c
22
--- a/target/arm/helper-a64.h
14
+++ b/hw/sd/sdhci.c
23
+++ b/target/arm/helper-a64.h
15
@@ -XXX,XX +XXX,XX @@ static void sdhci_uninitfn(SDHCIState *s)
24
@@ -XXX,XX +XXX,XX @@
16
s->fifo_buffer = NULL;
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
36
+++ b/target/arm/helper-a64.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
38
return flags;
17
}
39
}
18
40
19
+static void sdhci_common_realize(SDHCIState *s, Error **errp)
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
20
+{
42
+{
21
+ s->buf_maxsz = sdhci_get_fifolen(s);
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
22
+ s->fifo_buffer = g_malloc0(s->buf_maxsz);
23
+
24
+ memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
25
+ SDHC_REGISTERS_MAP_SIZE);
26
+}
44
+}
27
+
45
+
28
static bool sdhci_pending_insert_vmstate_needed(void *opaque)
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
47
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
49
+}
50
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
29
{
52
{
30
SDHCIState *s = opaque;
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
31
@@ -XXX,XX +XXX,XX @@ static Property sdhci_pci_properties[] = {
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
32
static void sdhci_pci_realize(PCIDevice *dev, Error **errp)
55
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/translate-a64.c
57
+++ b/target/arm/translate-a64.c
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
59
}
60
}
61
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
63
+static void handle_fp_compare(DisasContext *s, int size,
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
33
{
66
{
34
SDHCIState *s = PCI_SDHCI(dev);
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
35
+
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
36
+ sdhci_initfn(s);
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
37
+ sdhci_common_realize(s, errp);
70
38
+ if (errp && *errp) {
71
- if (is_double) {
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
39
+ return;
138
+ return;
40
+ }
139
+ }
41
+
140
+
42
dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */
141
+ switch (type) {
43
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
142
+ case 0:
44
- sdhci_initfn(s);
143
+ size = MO_32;
45
- s->buf_maxsz = sdhci_get_fifolen(s);
144
+ break;
46
- s->fifo_buffer = g_malloc0(s->buf_maxsz);
145
+ case 1:
47
s->irq = pci_allocate_irq(dev);
146
+ size = MO_64;
48
- memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
147
+ break;
49
- SDHC_REGISTERS_MAP_SIZE);
148
+ case 3:
50
pci_register_bar(dev, 0, 0, &s->iomem);
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
51
}
164
}
52
165
53
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
166
/* Floating point conditional compare
54
SDHCIState *s = SYSBUS_SDHCI(dev);
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
55
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
56
169
TCGv_i64 tcg_flags;
57
- s->buf_maxsz = sdhci_get_fifolen(s);
170
TCGLabel *label_continue = NULL;
58
- s->fifo_buffer = g_malloc0(s->buf_maxsz);
171
+ int size;
59
+ sdhci_common_realize(s, errp);
172
60
+ if (errp && *errp) {
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
61
+ return;
185
+ return;
62
+ }
186
+ }
63
+
187
+
64
sysbus_init_irq(sbd, &s->irq);
188
+ switch (type) {
65
- memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci",
189
+ case 0:
66
- SDHC_REGISTERS_MAP_SIZE);
190
+ size = MO_32;
67
sysbus_init_mmio(sbd, &s->iomem);
191
+ break;
68
}
192
+ case 1:
69
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
70
--
214
--
71
2.7.4
215
2.17.0
72
216
73
217
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/24] sdhci: add a 'dma' property to the sysbus devices
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Add a 'dma' property allowing machine creation to provide the address-space
3
These were missed out from the rest of the half-precision work.
4
SDHCI DMA operates on.
5
4
6
[based on a patch from Alistair Francis <alistair.francis@xilinx.com>
5
Cc: qemu-stable@nongnu.org
7
from qemu/xilinx tag xilinx-v2016.1]
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20180115182436.2066-15-f4bug@amsat.org
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
14
---
12
include/hw/sd/sdhci.h | 1 +
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
13
hw/sd/sdhci.c | 18 +++++++++++++++++-
16
1 file changed, 25 insertions(+), 6 deletions(-)
14
2 files changed, 18 insertions(+), 1 deletion(-)
15
17
16
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/sd/sdhci.h
20
--- a/target/arm/translate-a64.c
19
+++ b/include/hw/sd/sdhci.h
21
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
21
SDBus sdbus;
23
unsigned int mos, type, rm, cond, rn, rd;
22
MemoryRegion iomem;
24
TCGv_i64 t_true, t_false, t_zero;
23
AddressSpace *dma_as;
25
DisasCompare64 c;
24
+ MemoryRegion *dma_mr;
26
+ TCGMemOp sz;
25
27
26
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
28
mos = extract32(insn, 29, 3);
27
QEMUTimer *transfer_timer;
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
28
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
30
+ type = extract32(insn, 22, 2);
29
index XXXXXXX..XXXXXXX 100644
31
rm = extract32(insn, 16, 5);
30
--- a/hw/sd/sdhci.c
32
cond = extract32(insn, 12, 4);
31
+++ b/hw/sd/sdhci.c
33
rn = extract32(insn, 5, 5);
32
@@ -XXX,XX +XXX,XX @@ static Property sdhci_sysbus_properties[] = {
34
rd = extract32(insn, 0, 5);
33
DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
35
34
DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
36
- if (mos || type > 1) {
35
false),
37
+ if (mos) {
36
+ DEFINE_PROP_LINK("dma", SDHCIState,
38
+ unallocated_encoding(s);
37
+ dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
39
+ return;
38
DEFINE_PROP_END_OF_LIST(),
39
};
40
41
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_init(Object *obj)
42
static void sdhci_sysbus_finalize(Object *obj)
43
{
44
SDHCIState *s = SYSBUS_SDHCI(obj);
45
+
46
+ if (s->dma_mr) {
47
+ object_unparent(OBJECT(s->dma_mr));
48
+ }
40
+ }
49
+
41
+
50
sdhci_uninitfn(s);
42
+ switch (type) {
51
}
43
+ case 0:
52
44
+ sz = MO_32;
53
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp)
45
+ break;
46
+ case 1:
47
+ sz = MO_64;
48
+ break;
49
+ case 3:
50
+ sz = MO_16;
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
52
+ break;
53
+ }
54
+ /* fallthru */
55
+ default:
56
unallocated_encoding(s);
54
return;
57
return;
55
}
58
}
56
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
57
- s->dma_as = &address_space_memory;
60
return;
58
+ if (s->dma_mr) {
61
}
59
+ address_space_init(s->dma_as, s->dma_mr, "sdhci-dma");
62
60
+ } else {
63
- /* Zero extend sreg inputs to 64 bits now. */
61
+ /* use system_memory() if property "dma" not set */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
62
+ s->dma_as = &address_space_memory;
65
t_true = tcg_temp_new_i64();
63
+ }
66
t_false = tcg_temp_new_i64();
64
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
65
sysbus_init_irq(sbd, &s->irq);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
66
sysbus_init_mmio(sbd, &s->iomem);
69
+ read_vec_element(s, t_true, rn, 0, sz);
67
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp)
70
+ read_vec_element(s, t_false, rm, 0, sz);
68
SDHCIState *s = SYSBUS_SDHCI(dev);
71
69
72
a64_test_cc(&c, cond);
70
sdhci_common_unrealize(s, &error_abort);
73
t_zero = tcg_const_i64(0);
71
+
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
72
+ if (s->dma_mr) {
75
tcg_temp_free_i64(t_false);
73
+ address_space_destroy(s->dma_as);
76
a64_free_cc(&c);
74
+ }
77
75
}
78
- /* Note that sregs write back zeros to the high bits,
76
79
+ /* Note that sregs & hregs write back zeros to the high bits,
77
static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
78
--
83
--
79
2.7.4
84
2.17.0
80
85
81
86
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/24] sdhci: convert the DPRINT() calls into trace events
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
zero-initialize ADMADescr 'dscr' in sdhci_do_adma() to avoid:
3
All the hard work is already done by vfp_expand_imm, we just need to
4
make sure we pick up the correct size.
4
5
5
hw/sd/sdhci.c: In function ‘sdhci_do_adma’:
6
Cc: qemu-stable@nongnu.org
6
hw/sd/sdhci.c:714:29: error: ‘dscr.addr’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
trace_sdhci_adma("link", s->admasysaddr);
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
8
^
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
11
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
12
Message-id: 20180115182436.2066-9-f4bug@amsat.org
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
---
15
hw/sd/sdhci.c | 89 ++++++++++++++++++------------------------------------
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
16
hw/sd/trace-events | 14 +++++++++
17
1 file changed, 17 insertions(+), 3 deletions(-)
17
2 files changed, 44 insertions(+), 59 deletions(-)
18
18
19
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/sd/sdhci.c
21
--- a/target/arm/translate-a64.c
22
+++ b/hw/sd/sdhci.c
22
+++ b/target/arm/translate-a64.c
23
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
24
#include "sdhci-internal.h"
25
#include "qapi/error.h"
26
#include "qemu/log.h"
27
-
28
-/* host controller debug messages */
29
-#ifndef SDHC_DEBUG
30
-#define SDHC_DEBUG 0
31
-#endif
32
-
33
-#define DPRINT_L1(fmt, args...) \
34
- do { \
35
- if (SDHC_DEBUG) { \
36
- fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
37
- } \
38
- } while (0)
39
-#define DPRINT_L2(fmt, args...) \
40
- do { \
41
- if (SDHC_DEBUG > 1) { \
42
- fprintf(stderr, "QEMU SDHC: " fmt, ## args); \
43
- } \
44
- } while (0)
45
-#define ERRPRINT(fmt, args...) \
46
- do { \
47
- if (SDHC_DEBUG) { \
48
- fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \
49
- } \
50
- } while (0)
51
+#include "trace.h"
52
53
#define TYPE_SDHCI_BUS "sdhci-bus"
54
#define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
55
@@ -XXX,XX +XXX,XX @@ static void sdhci_raise_insertion_irq(void *opaque)
56
static void sdhci_set_inserted(DeviceState *dev, bool level)
57
{
24
{
58
SDHCIState *s = (SDHCIState *)dev;
25
int rd = extract32(insn, 0, 5);
59
- DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject");
26
int imm8 = extract32(insn, 13, 8);
60
27
- int is_double = extract32(insn, 22, 2);
61
+ trace_sdhci_set_inserted(level ? "insert" : "eject");
28
+ int type = extract32(insn, 22, 2);
62
if ((s->norintsts & SDHC_NIS_REMOVE) && level) {
29
uint64_t imm;
63
/* Give target some time to notice card ejection */
30
TCGv_i64 tcg_res;
64
timer_mod(s->insert_timer,
31
+ TCGMemOp sz;
65
@@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s)
32
66
s->acmd12errsts = 0;
33
- if (is_double > 1) {
67
request.cmd = s->cmdreg >> 8;
34
+ switch (type) {
68
request.arg = s->argument;
35
+ case 0:
69
- DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg);
36
+ sz = MO_32;
70
+
37
+ break;
71
+ trace_sdhci_send_command(request.cmd, request.arg);
38
+ case 1:
72
rlen = sdbus_do_command(&s->sdbus, &request, response);
39
+ sz = MO_64;
73
40
+ break;
74
if (s->cmdreg & SDHC_CMD_RESPONSE) {
41
+ case 3:
75
@@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s)
42
+ sz = MO_16;
76
s->rspreg[0] = (response[0] << 24) | (response[1] << 16) |
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
77
(response[2] << 8) | response[3];
44
+ break;
78
s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0;
45
+ }
79
- DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]);
46
+ /* fallthru */
80
+ trace_sdhci_response4(s->rspreg[0]);
47
+ default:
81
} else if (rlen == 16) {
48
unallocated_encoding(s);
82
s->rspreg[0] = (response[11] << 24) | (response[12] << 16) |
83
(response[13] << 8) | response[14];
84
@@ -XXX,XX +XXX,XX @@ static void sdhci_send_command(SDHCIState *s)
85
(response[5] << 8) | response[6];
86
s->rspreg[3] = (response[0] << 16) | (response[1] << 8) |
87
response[2];
88
- DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.."
89
- "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n",
90
- s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]);
91
+ trace_sdhci_response16(s->rspreg[3], s->rspreg[2],
92
+ s->rspreg[1], s->rspreg[0]);
93
} else {
94
- ERRPRINT("Timeout waiting for command response\n");
95
+ trace_sdhci_error("timeout waiting for command response");
96
if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) {
97
s->errintsts |= SDHC_EIS_CMDTIMEOUT;
98
s->norintsts |= SDHC_NIS_ERR;
99
@@ -XXX,XX +XXX,XX @@ static void sdhci_end_transfer(SDHCIState *s)
100
101
request.cmd = 0x0C;
102
request.arg = 0;
103
- DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg);
104
+ trace_sdhci_end_transfer(request.cmd, request.arg);
105
sdbus_do_command(&s->sdbus, &request, response);
106
/* Auto CMD12 response goes to the upper Response register */
107
s->rspreg[3] = (response[0] << 24) | (response[1] << 16) |
108
@@ -XXX,XX +XXX,XX @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
109
110
/* first check that a valid data exists in host controller input buffer */
111
if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) {
112
- ERRPRINT("Trying to read from empty buffer\n");
113
+ trace_sdhci_error("read from empty buffer");
114
return 0;
115
}
116
117
@@ -XXX,XX +XXX,XX @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size)
118
s->data_count++;
119
/* check if we've read all valid data (blksize bytes) from buffer */
120
if ((s->data_count) >= (s->blksize & 0x0fff)) {
121
- DPRINT_L2("All %u bytes of data have been read from input buffer\n",
122
- s->data_count);
123
+ trace_sdhci_read_dataport(s->data_count);
124
s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */
125
s->data_count = 0; /* next buff read must start at position [0] */
126
127
@@ -XXX,XX +XXX,XX @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
128
129
/* Check that there is free space left in a buffer */
130
if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) {
131
- ERRPRINT("Can't write to data buffer: buffer full\n");
132
+ trace_sdhci_error("Can't write to data buffer: buffer full");
133
return;
49
return;
134
}
50
}
135
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
136
@@ -XXX,XX +XXX,XX @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
52
return;
137
s->data_count++;
138
value >>= 8;
139
if (s->data_count >= (s->blksize & 0x0fff)) {
140
- DPRINT_L2("write buffer filled with %u bytes of data\n",
141
- s->data_count);
142
+ trace_sdhci_write_dataport(s->data_count);
143
s->data_count = 0;
144
s->prnsts &= ~SDHC_SPACE_AVAILABLE;
145
if (s->prnsts & SDHC_DOING_WRITE) {
146
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
147
{
148
unsigned int n, begin, length;
149
const uint16_t block_size = s->blksize & 0x0fff;
150
- ADMADescr dscr;
151
+ ADMADescr dscr = {};
152
int i;
153
154
for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) {
155
s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH;
156
157
get_adma_description(s, &dscr);
158
- DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n",
159
- dscr.addr, dscr.length, dscr.attr);
160
+ trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr);
161
162
if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) {
163
/* Indicate that error occurred in ST_FDS state */
164
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
165
break;
166
case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */
167
s->admasysaddr = dscr.addr;
168
- DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n",
169
- s->admasysaddr);
170
+ trace_sdhci_adma("link", s->admasysaddr);
171
break;
172
default:
173
s->admasysaddr += dscr.incr;
174
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
175
}
176
177
if (dscr.attr & SDHC_ADMA_ATTR_INT) {
178
- DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n",
179
- s->admasysaddr);
180
+ trace_sdhci_adma("interrupt", s->admasysaddr);
181
if (s->norintstsen & SDHC_NISEN_DMA) {
182
s->norintsts |= SDHC_NIS_DMA;
183
}
184
@@ -XXX,XX +XXX,XX @@ static void sdhci_do_adma(SDHCIState *s)
185
/* ADMA transfer terminates if blkcnt == 0 or by END attribute */
186
if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
187
(s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) {
188
- DPRINT_L2("ADMA transfer completed\n");
189
+ trace_sdhci_adma_transfer_completed();
190
if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) &&
191
(s->trnmod & SDHC_TRNS_BLK_CNT_EN) &&
192
s->blkcnt != 0)) {
193
- ERRPRINT("SD/MMC host ADMA length mismatch\n");
194
+ trace_sdhci_error("SD/MMC host ADMA length mismatch");
195
s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH |
196
SDHC_ADMAERR_STATE_ST_TFR;
197
if (s->errintstsen & SDHC_EISEN_ADMAERR) {
198
- ERRPRINT("Set ADMA error flag\n");
199
+ trace_sdhci_error("Set ADMA error flag");
200
s->errintsts |= SDHC_EIS_ADMAERR;
201
s->norintsts |= SDHC_NIS_ERR;
202
}
203
@@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque)
204
break;
205
case SDHC_CTRL_ADMA1_32:
206
if (!(s->capareg & SDHC_CAN_DO_ADMA1)) {
207
- ERRPRINT("ADMA1 not supported\n");
208
+ trace_sdhci_error("ADMA1 not supported");
209
break;
210
}
211
212
@@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque)
213
break;
214
case SDHC_CTRL_ADMA2_32:
215
if (!(s->capareg & SDHC_CAN_DO_ADMA2)) {
216
- ERRPRINT("ADMA2 not supported\n");
217
+ trace_sdhci_error("ADMA2 not supported");
218
break;
219
}
220
221
@@ -XXX,XX +XXX,XX @@ static void sdhci_data_transfer(void *opaque)
222
case SDHC_CTRL_ADMA2_64:
223
if (!(s->capareg & SDHC_CAN_DO_ADMA2) ||
224
!(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) {
225
- ERRPRINT("64 bit ADMA not supported\n");
226
+ trace_sdhci_error("64 bit ADMA not supported");
227
break;
228
}
229
230
sdhci_do_adma(s);
231
break;
232
default:
233
- ERRPRINT("Unsupported DMA type\n");
234
+ trace_sdhci_error("Unsupported DMA type");
235
break;
236
}
237
} else {
238
@@ -XXX,XX +XXX,XX @@ static inline bool
239
sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num)
240
{
241
if ((s->data_count & 0x3) != byte_num) {
242
- ERRPRINT("Non-sequential access to Buffer Data Port register"
243
- "is prohibited\n");
244
+ trace_sdhci_error("Non-sequential access to Buffer Data Port register"
245
+ "is prohibited\n");
246
return false;
247
}
53
}
248
return true;
54
249
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
250
case SDHC_BDATA:
56
+ imm = vfp_expand_imm(sz, imm8);
251
if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) {
57
252
ret = sdhci_read_dataport(s, size);
58
tcg_res = tcg_const_i64(imm);
253
- DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset,
59
write_fp_dreg(s, rd, tcg_res);
254
- ret, ret);
255
+ trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
256
return ret;
257
}
258
break;
259
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
260
261
ret >>= (offset & 0x3) * 8;
262
ret &= (1ULL << (size * 8)) - 1;
263
- DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret);
264
+ trace_sdhci_access("rd", size << 3, offset, "->", ret, ret);
265
return ret;
266
}
267
268
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
269
"not implemented\n", size, offset, value >> shift);
270
break;
271
}
272
- DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
273
- size, (int)offset, value >> shift, value >> shift);
274
+ trace_sdhci_access("wr", size << 3, offset, "<-",
275
+ value >> shift, value >> shift);
276
}
277
278
static const MemoryRegionOps sdhci_mmio_ops = {
279
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
280
index XXXXXXX..XXXXXXX 100644
281
--- a/hw/sd/trace-events
282
+++ b/hw/sd/trace-events
283
@@ -XXX,XX +XXX,XX @@
284
# See docs/devel/tracing.txt for syntax documentation.
285
286
+# hw/sd/sdhci.c
287
+sdhci_set_inserted(const char *level) "card state changed: %s"
288
+sdhci_send_command(uint8_t cmd, uint32_t arg) "CMD%02u ARG[0x%08x]"
289
+sdhci_error(const char *msg) "%s"
290
+sdhci_response4(uint32_t r0) "RSPREG[31..0]=0x%08x"
291
+sdhci_response16(uint32_t r3, uint32_t r2, uint32_t r1, uint32_t r0) "RSPREG[127..96]=0x%08x, RSPREG[95..64]=0x%08x, RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x"
292
+sdhci_end_transfer(uint8_t cmd, uint32_t arg) "Automatically issue CMD%02u 0x%08x"
293
+sdhci_adma(const char *desc, uint32_t sysad) "%s: admasysaddr=0x%" PRIx32
294
+sdhci_adma_loop(uint64_t addr, uint16_t length, uint8_t attr) "addr=0x%08" PRIx64 ", len=%d, attr=0x%x"
295
+sdhci_adma_transfer_completed(void) ""
296
+sdhci_access(const char *access, unsigned int size, uint64_t offset, const char *dir, uint64_t val, uint64_t val2) "%s%u: addr[0x%04" PRIx64 "] %s 0x%08" PRIx64 " (%" PRIu64 ")"
297
+sdhci_read_dataport(uint16_t data_count) "all %u bytes of data have been read from input buffer"
298
+sdhci_write_dataport(uint16_t data_count) "write buffer filled with %u bytes of data"
299
+
300
# hw/sd/milkymist-memcard.c
301
milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
302
milkymist_memcard_memory_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x"
303
--
60
--
304
2.7.4
61
2.17.0
305
62
306
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/24] sdhci: move MASK_TRNMOD with other SDHC_TRN* defines in "sd-internal.h"
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
We are meant to explicitly pass fpst, not cpu_env.
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
4
5
Message-id: 20180115182436.2066-10-f4bug@amsat.org
5
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
hw/sd/sdhci-internal.h | 1 +
13
target/arm/translate-a64.c | 3 ++-
9
hw/sd/sdhci.c | 3 +--
14
1 file changed, 2 insertions(+), 1 deletion(-)
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
15
12
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/sd/sdhci-internal.h
18
--- a/target/arm/translate-a64.c
15
+++ b/hw/sd/sdhci-internal.h
19
+++ b/target/arm/translate-a64.c
16
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
17
#define SDHC_TRNS_ACMD12 0x0004
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
18
#define SDHC_TRNS_READ 0x0010
22
break;
19
#define SDHC_TRNS_MULTI 0x0020
23
case 0x3: /* FSQRT */
20
+#define SDHC_TRNMOD_MASK 0x0037
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
21
25
+ fpst = get_fpstatus_ptr(true);
22
/* R/W Command Register 0x0 */
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
23
#define SDHC_CMDREG 0x0E
27
break;
24
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
28
case 0x8: /* FRINTN */
25
index XXXXXXX..XXXXXXX 100644
29
case 0x9: /* FRINTP */
26
--- a/hw/sd/sdhci.c
27
+++ b/hw/sd/sdhci.c
28
@@ -XXX,XX +XXX,XX @@
29
(SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \
30
(SDHC_CAPAB_TOCLKFREQ))
31
32
-#define MASK_TRNMOD 0x0037
33
#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
34
35
static uint8_t sdhci_slotint(SDHCIState *s)
36
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
37
if (!(s->capareg & SDHC_CAN_DO_DMA)) {
38
value &= ~SDHC_TRNS_DMA;
39
}
40
- MASKED_WRITE(s->trnmod, mask, value & MASK_TRNMOD);
41
+ MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK);
42
MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16);
43
44
/* Writing to the upper byte of CMDREG triggers SD command generation */
45
--
30
--
46
2.7.4
31
2.17.0
47
32
48
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/24] sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init()
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Now both inherited classes appear as DEVICE_CATEGORY_STORAGE.
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
4
5
The block length is predefined to 512 bits
6
7
and "4.10.2 SD Status":
8
9
The SD Status contains status bits that are related to the SD Memory Card
10
proprietary features and may be used for future application-specific usage.
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
4
15
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
7
Message-id: 20180115182436.2066-5-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
20
---
10
hw/sd/sdhci.c | 18 +++++++++++++-----
21
hw/sd/sd.c | 2 +-
11
1 file changed, 13 insertions(+), 5 deletions(-)
22
1 file changed, 1 insertion(+), 1 deletion(-)
12
23
13
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
14
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sdhci.c
26
--- a/hw/sd/sd.c
16
+++ b/hw/sd/sdhci.c
27
+++ b/hw/sd/sd.c
17
@@ -XXX,XX +XXX,XX @@ const VMStateDescription sdhci_vmstate = {
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
18
},
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
19
};
30
}
20
31
memset(&sd->data[17], 0, 47);
21
+static void sdhci_common_class_init(ObjectClass *klass, void *data)
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
22
+{
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
23
+ DeviceClass *dc = DEVICE_CLASS(klass);
24
+
25
+ set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
26
+ dc->vmsd = &sdhci_vmstate;
27
+ dc->reset = sdhci_poweron_reset;
28
+}
29
+
30
/* --- qdev PCI --- */
31
32
static Property sdhci_pci_properties[] = {
33
@@ -XXX,XX +XXX,XX @@ static void sdhci_pci_class_init(ObjectClass *klass, void *data)
34
k->vendor_id = PCI_VENDOR_ID_REDHAT;
35
k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI;
36
k->class_id = PCI_CLASS_SYSTEM_SDHCI;
37
- set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
38
- dc->vmsd = &sdhci_vmstate;
39
dc->props = sdhci_pci_properties;
40
- dc->reset = sdhci_poweron_reset;
41
+
42
+ sdhci_common_class_init(klass, data);
43
}
34
}
44
35
45
static const TypeInfo sdhci_pci_info = {
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
46
@@ -XXX,XX +XXX,XX @@ static void sdhci_sysbus_class_init(ObjectClass *klass, void *data)
47
{
48
DeviceClass *dc = DEVICE_CLASS(klass);
49
50
- dc->vmsd = &sdhci_vmstate;
51
dc->props = sdhci_sysbus_properties;
52
dc->realize = sdhci_sysbus_realize;
53
- dc->reset = sdhci_poweron_reset;
54
+
55
+ sdhci_common_class_init(klass, data);
56
}
57
58
static const TypeInfo sdhci_sysbus_info = {
59
--
37
--
60
2.7.4
38
2.17.0
61
39
62
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/24] hw/arm/virt: Add virt-2.12 machine type
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
1
Add virt-2.12 machine type.
1
Usually the logging of the CPU state produced by -d cpu is sufficient
2
to diagnose problems, but sometimes you want to see the state of
3
the floating point registers as well. We don't want to enable that
4
by default as it adds a lot of extra data to the log; instead,
5
allow it to be optionally enabled via -d fpu.
2
6
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
4
---
10
---
5
hw/arm/virt.c | 19 +++++++++++++++++--
11
include/qemu/log.h | 1 +
6
1 file changed, 17 insertions(+), 2 deletions(-)
12
accel/tcg/cpu-exec.c | 9 ++++++---
13
util/log.c | 2 ++
14
3 files changed, 9 insertions(+), 3 deletions(-)
7
15
8
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
9
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
10
--- a/hw/arm/virt.c
18
--- a/include/qemu/log.h
11
+++ b/hw/arm/virt.c
19
+++ b/include/qemu/log.h
12
@@ -XXX,XX +XXX,XX @@ static void machvirt_machine_init(void)
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
13
}
21
#define CPU_LOG_PAGE (1 << 14)
14
type_init(machvirt_machine_init);
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
15
23
#define CPU_LOG_TB_OP_IND (1 << 16)
16
-static void virt_2_11_instance_init(Object *obj)
24
+#define CPU_LOG_TB_FPU (1 << 17)
17
+static void virt_2_12_instance_init(Object *obj)
25
18
{
26
/* Lock output for a series of related logs. Since this is not needed
19
VirtMachineState *vms = VIRT_MACHINE(obj);
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
20
VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
21
@@ -XXX,XX +XXX,XX @@ static void virt_2_11_instance_init(Object *obj)
29
index XXXXXXX..XXXXXXX 100644
22
vms->irqmap = a15irqmap;
30
--- a/accel/tcg/cpu-exec.c
23
}
31
+++ b/accel/tcg/cpu-exec.c
24
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
25
+static void virt_machine_2_12_options(MachineClass *mc)
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
26
+{
34
&& qemu_log_in_addr_range(itb->pc)) {
27
+}
35
qemu_log_lock();
28
+DEFINE_VIRT_MACHINE_AS_LATEST(2, 12)
36
+ int flags = 0;
29
+
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
30
+#define VIRT_COMPAT_2_11 \
38
+ flags |= CPU_DUMP_FPU;
31
+ HW_COMPAT_2_11
39
+ }
32
+
40
#if defined(TARGET_I386)
33
+static void virt_2_11_instance_init(Object *obj)
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
34
+{
42
-#else
35
+ virt_2_12_instance_init(obj);
43
- log_cpu_state(cpu, 0);
36
+}
44
+ flags |= CPU_DUMP_CCOP;
37
+
45
#endif
38
static void virt_machine_2_11_options(MachineClass *mc)
46
+ log_cpu_state(cpu, flags);
39
{
47
qemu_log_unlock();
40
+ virt_machine_2_12_options(mc);
48
}
41
+ SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_11);
49
#endif /* DEBUG_DISAS */
42
}
50
diff --git a/util/log.c b/util/log.c
43
-DEFINE_VIRT_MACHINE_AS_LATEST(2, 11)
51
index XXXXXXX..XXXXXXX 100644
44
+DEFINE_VIRT_MACHINE(2, 11)
52
--- a/util/log.c
45
53
+++ b/util/log.c
46
#define VIRT_COMPAT_2_10 \
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
47
HW_COMPAT_2_10
55
"show trace before each executed TB (lots of logs)" },
56
{ CPU_LOG_TB_CPU, "cpu",
57
"show CPU registers before entering a TB (lots of logs)" },
58
+ { CPU_LOG_TB_FPU, "fpu",
59
+ "include FPU registers in the 'cpu' logging" },
60
{ CPU_LOG_MMU, "mmu",
61
"log MMU-related activities" },
62
{ CPU_LOG_PCALL, "pcall",
48
--
63
--
49
2.7.4
64
2.17.0
50
65
51
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/24] hw/sd/milkymist-memcard: Reset SD card on controller reset
Deleted patch
1
Since milkymist-memcard is still using the legacy SD card API,
2
the SD card created by sd_init() is not plugged into any bus.
3
This means that the controller has to reset it manually.
4
1
5
Failing to do this mostly didn't affect the guest since the
6
guest typically does a programmed SD card reset as part of
7
its SD controller driver initialization, but meant that
8
migration failed because it's only in sd_reset() that we
9
set up the wpgrps_size field.
10
11
Cc: qemu-stable@nongnu.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
Message-id: 1515506513-31961-3-git-send-email-peter.maydell@linaro.org
16
---
17
hw/sd/milkymist-memcard.c | 4 ++++
18
1 file changed, 4 insertions(+)
19
20
diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/sd/milkymist-memcard.c
23
+++ b/hw/sd/milkymist-memcard.c
24
@@ -XXX,XX +XXX,XX @@ static void milkymist_memcard_reset(DeviceState *d)
25
for (i = 0; i < R_MAX; i++) {
26
s->regs[i] = 0;
27
}
28
+ /* Since we're still using the legacy SD API the card is not plugged
29
+ * into any bus, and we must reset it manually.
30
+ */
31
+ device_reset(DEVICE(s->card));
32
}
33
34
static int milkymist_memcard_init(SysBusDevice *dev)
35
--
36
2.7.4
37
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/24] hw/sd/omap_mmc: Reset SD card on controller reset
Deleted patch
1
Since omap_mmc is still using the legacy SD card API, the SD
2
card created by sd_init() is not plugged into any bus. This
3
means that the controller has to reset it manually.
4
1
5
Failing to do this mostly didn't affect the guest since the
6
guest typically does a programmed SD card reset as part of
7
its SD controller driver initialization, but would mean that
8
migration fails because it's only in sd_reset() that we
9
set up the wpgrps_size field.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 1515506513-31961-5-git-send-email-peter.maydell@linaro.org
15
---
16
hw/sd/omap_mmc.c | 14 ++++++++++----
17
1 file changed, 10 insertions(+), 4 deletions(-)
18
19
diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/sd/omap_mmc.c
22
+++ b/hw/sd/omap_mmc.c
23
@@ -XXX,XX +XXX,XX @@ void omap_mmc_reset(struct omap_mmc_s *host)
24
host->cdet_enable = 0;
25
qemu_set_irq(host->coverswitch, host->cdet_state);
26
host->clkdiv = 0;
27
+
28
+ /* Since we're still using the legacy SD API the card is not plugged
29
+ * into any bus, and we must reset it manually. When omap_mmc is
30
+ * QOMified this must move into the QOM reset function.
31
+ */
32
+ device_reset(DEVICE(host->card));
33
}
34
35
static uint64_t omap_mmc_read(void *opaque, hwaddr offset,
36
@@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap_mmc_init(hwaddr base,
37
s->lines = 1;    /* TODO: needs to be settable per-board */
38
s->rev = 1;
39
40
- omap_mmc_reset(s);
41
-
42
memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc", 0x800);
43
memory_region_add_subregion(sysmem, base, &s->iomem);
44
45
@@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap_mmc_init(hwaddr base,
46
exit(1);
47
}
48
49
+ omap_mmc_reset(s);
50
+
51
return s;
52
}
53
54
@@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
55
s->lines = 4;
56
s->rev = 2;
57
58
- omap_mmc_reset(s);
59
-
60
memory_region_init_io(&s->iomem, NULL, &omap_mmc_ops, s, "omap.mmc",
61
omap_l4_region_size(ta, 0));
62
omap_l4_attach(ta, 0, &s->iomem);
63
@@ -XXX,XX +XXX,XX @@ struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
64
s->cdet = qemu_allocate_irq(omap_mmc_cover_cb, s, 0);
65
sd_set_cb(s->card, NULL, s->cdet);
66
67
+ omap_mmc_reset(s);
68
+
69
return s;
70
}
71
72
--
73
2.7.4
74
75
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/24] sdhci: clean up includes
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
5
Message-id: 20180115182436.2066-2-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/sd/sdhci-internal.h | 4 ----
9
include/hw/sd/sdhci.h | 7 ++++++-
10
hw/sd/sdhci.c | 1 +
11
3 files changed, 7 insertions(+), 5 deletions(-)
12
13
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/sd/sdhci-internal.h
16
+++ b/hw/sd/sdhci-internal.h
17
@@ -XXX,XX +XXX,XX @@
18
#ifndef SDHCI_INTERNAL_H
19
#define SDHCI_INTERNAL_H
20
21
-#include "hw/sd/sdhci.h"
22
-
23
/* R/W SDMA System Address register 0x0 */
24
#define SDHC_SYSAD 0x00
25
26
@@ -XXX,XX +XXX,XX @@ enum {
27
sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */
28
};
29
30
-extern const VMStateDescription sdhci_vmstate;
31
-
32
#endif
33
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/include/hw/sd/sdhci.h
36
+++ b/include/hw/sd/sdhci.h
37
@@ -XXX,XX +XXX,XX @@
38
#define SDHCI_H
39
40
#include "qemu-common.h"
41
-#include "hw/block/block.h"
42
#include "hw/pci/pci.h"
43
#include "hw/sysbus.h"
44
#include "hw/sd/sd.h"
45
46
/* SD/MMC host controller state */
47
typedef struct SDHCIState {
48
+ /*< private >*/
49
union {
50
PCIDevice pcidev;
51
SysBusDevice busdev;
52
};
53
+
54
+ /*< public >*/
55
SDBus sdbus;
56
MemoryRegion iomem;
57
58
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
59
qemu_irq ro_cb;
60
qemu_irq irq;
61
62
+ /* Registers cleared on reset */
63
uint32_t sdmasysad; /* SDMA System Address register */
64
uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */
65
uint16_t blkcnt; /* Blocks count for current transfer */
66
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
67
uint16_t acmd12errsts; /* Auto CMD12 error status register */
68
uint64_t admasysaddr; /* ADMA System Address Register */
69
70
+ /* Read-only registers */
71
uint32_t capareg; /* Capabilities Register */
72
uint32_t maxcurr; /* Maximum Current Capabilities Register */
73
+
74
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
75
uint32_t buf_maxsz;
76
uint16_t data_count; /* current element in FIFO buffer */
77
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
78
index XXXXXXX..XXXXXXX 100644
79
--- a/hw/sd/sdhci.c
80
+++ b/hw/sd/sdhci.c
81
@@ -XXX,XX +XXX,XX @@
82
#include "sysemu/dma.h"
83
#include "qemu/timer.h"
84
#include "qemu/bitops.h"
85
+#include "hw/sd/sdhci.h"
86
#include "sdhci-internal.h"
87
#include "qemu/log.h"
88
89
--
90
2.7.4
91
92
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/24] sdhci: remove dead code
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
5
Message-id: 20180115182436.2066-3-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
include/hw/sd/sdhci.h | 2 --
9
hw/sd/sdhci.c | 2 --
10
2 files changed, 4 deletions(-)
11
12
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/include/hw/sd/sdhci.h
15
+++ b/include/hw/sd/sdhci.h
16
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
17
18
QEMUTimer *insert_timer; /* timer for 'changing' sd card. */
19
QEMUTimer *transfer_timer;
20
- qemu_irq eject_cb;
21
- qemu_irq ro_cb;
22
qemu_irq irq;
23
24
/* Registers cleared on reset */
25
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/sd/sdhci.c
28
+++ b/hw/sd/sdhci.c
29
@@ -XXX,XX +XXX,XX @@ static void sdhci_uninitfn(SDHCIState *s)
30
timer_free(s->insert_timer);
31
timer_del(s->transfer_timer);
32
timer_free(s->transfer_timer);
33
- qemu_free_irq(s->eject_cb);
34
- qemu_free_irq(s->ro_cb);
35
36
g_free(s->fifo_buffer);
37
s->fifo_buffer = NULL;
38
--
39
2.7.4
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/24] sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Add common/sysbus/pci/sdbus comments to have clearer code blocks separation.
4
5
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Message-id: 20180115182436.2066-4-f4bug@amsat.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
include/hw/sd/sdhci.h | 4 +++-
11
hw/sd/sdhci.c | 25 +++++++++++++++++--------
12
2 files changed, 20 insertions(+), 9 deletions(-)
13
14
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/sd/sdhci.h
17
+++ b/include/hw/sd/sdhci.h
18
@@ -XXX,XX +XXX,XX @@ typedef struct SDHCIState {
19
uint32_t buf_maxsz;
20
uint16_t data_count; /* current element in FIFO buffer */
21
uint8_t stopped_state;/* Current SDHC state */
22
- bool pending_insert_quirk;/* Quirk for Raspberry Pi card insert int */
23
bool pending_insert_state;
24
/* Buffer Data Port Register - virtual access point to R and W buffers */
25
/* Software Reset Register - always reads as 0 */
26
/* Force Event Auto CMD12 Error Interrupt Reg - write only */
27
/* Force Event Error Interrupt Register- write only */
28
/* RO Host Controller Version Register always reads as 0x2401 */
29
+
30
+ /* Configurable properties */
31
+ bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
32
} SDHCIState;
33
34
#define TYPE_PCI_SDHCI "sdhci-pci"
35
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/hw/sd/sdhci.c
38
+++ b/hw/sd/sdhci.c
39
@@ -XXX,XX +XXX,XX @@
40
*/
41
42
#include "qemu/osdep.h"
43
+#include "qapi/error.h"
44
#include "hw/hw.h"
45
#include "sysemu/block-backend.h"
46
#include "sysemu/blockdev.h"
47
@@ -XXX,XX +XXX,XX @@ static inline unsigned int sdhci_get_fifolen(SDHCIState *s)
48
}
49
}
50
51
+/* --- qdev common --- */
52
+
53
+#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
54
+ /* Capabilities registers provide information on supported features
55
+ * of this specific host controller implementation */ \
56
+ DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
57
+ DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)
58
+
59
static void sdhci_initfn(SDHCIState *s)
60
{
61
qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
62
@@ -XXX,XX +XXX,XX @@ const VMStateDescription sdhci_vmstate = {
63
},
64
};
65
66
-/* Capabilities registers provide information on supported features of this
67
- * specific host controller implementation */
68
+/* --- qdev PCI --- */
69
+
70
static Property sdhci_pci_properties[] = {
71
- DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
72
- SDHC_CAPAB_REG_DEFAULT),
73
- DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
74
+ DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
75
DEFINE_PROP_END_OF_LIST(),
76
};
77
78
@@ -XXX,XX +XXX,XX @@ static const TypeInfo sdhci_pci_info = {
79
},
80
};
81
82
+/* --- qdev SysBus --- */
83
+
84
static Property sdhci_sysbus_properties[] = {
85
- DEFINE_PROP_UINT32("capareg", SDHCIState, capareg,
86
- SDHC_CAPAB_REG_DEFAULT),
87
- DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
88
+ DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState),
89
DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk,
90
false),
91
DEFINE_PROP_END_OF_LIST(),
92
@@ -XXX,XX +XXX,XX @@ static const TypeInfo sdhci_sysbus_info = {
93
.class_init = sdhci_sysbus_class_init,
94
};
95
96
+/* --- qdev bus master --- */
97
+
98
static void sdhci_bus_class_init(ObjectClass *klass, void *data)
99
{
100
SDBusClass *sbc = SD_BUS_CLASS(klass);
101
--
102
2.7.4
103
104
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/24] sdhci: use qemu_log_mask(UNIMP) instead of fprintf()
Deleted patch
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
1
3
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
5
Message-id: 20180115182436.2066-8-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
hw/sd/sdhci.c | 7 ++++---
9
1 file changed, 4 insertions(+), 3 deletions(-)
10
11
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/sd/sdhci.c
14
+++ b/hw/sd/sdhci.c
15
@@ -XXX,XX +XXX,XX @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
16
ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
17
break;
18
default:
19
- ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset);
20
+ qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
21
+ "not implemented\n", size, offset);
22
break;
23
}
24
25
@@ -XXX,XX +XXX,XX @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
26
sdhci_update_irq(s);
27
break;
28
default:
29
- ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n",
30
- size, (int)offset, value >> shift, value >> shift);
31
+ qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
32
+ "not implemented\n", size, offset, value >> shift);
33
break;
34
}
35
DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n",
36
--
37
2.7.4
38
39
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.